Mercurial > mplayer.hg
annotate cpudetect.c @ 28992:947ef23ba798
Test if create_vdp_decoder() might succeed by calling it from config()
with a small value for max_reference_frames.
This does not make automatic recovery by using software decoder possible,
but lets MPlayer fail more graciously on - actually existing - buggy
hardware that does not support certain H264 widths when using
hardware accelerated decoding (784, 864, 944, 1024, 1808, 1888 pixels on
NVIDIA G98) and if the user tries to hardware-decode more samples at
the same time than supported.
Might break playback of H264 Intra-Only samples on hardware with very
little video memory.
author | cehoyos |
---|---|
date | Sat, 21 Mar 2009 20:11:05 +0000 |
parents | e1b7d9bf263b |
children | 8450a9da95f7 |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
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7 #if HAVE_MALLOC_H |
3837 | 8 #include <malloc.h> |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #if ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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22 #include <sys/types.h> |
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23 #include <sys/sysctl.h> |
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24 #elif defined(__linux__) |
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25 #include <signal.h> |
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26 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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28 #elif defined(__OS2__) |
26061 | 29 #define INCL_DOS |
30 #include <os2.h> | |
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31 #elif defined(__AMIGAOS4__) |
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32 #include <proto/exec.h> |
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33 #endif |
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34 |
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35 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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36 * help understanding how to use it. Thanks to the Mesa |
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37 * team for SSE support detection and more cpu detect code. |
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38 */ |
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39 |
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40 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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41 |
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42 static void check_os_katmai_support( void ); |
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43 |
2272 | 44 // return TRUE if cpuid supported |
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45 static int has_cpuid(void) |
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46 { |
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47 long a, c; |
2272 | 48 |
49 // code from libavcodec: | |
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50 #if ARCH_X86_64 |
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51 #define PUSHF "pushfq\n\t" |
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52 #define POPF "popfq\n\t" |
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53 #else |
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54 #define PUSHF "pushfl\n\t" |
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55 #define POPF "popfl\n\t" |
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56 #endif |
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57 __asm__ volatile ( |
2272 | 58 /* See if CPUID instruction is supported ... */ |
59 /* ... Get copies of EFLAGS into eax and ecx */ | |
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60 PUSHF |
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61 "pop %0\n\t" |
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62 "mov %0, %1\n\t" |
2272 | 63 |
64 /* ... Toggle the ID bit in one copy and store */ | |
65 /* to the EFLAGS reg */ | |
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66 "xor $0x200000, %0\n\t" |
2272 | 67 "push %0\n\t" |
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68 POPF |
2272 | 69 |
70 /* ... Get the (hopefully modified) EFLAGS */ | |
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71 PUSHF |
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72 "pop %0\n\t" |
2272 | 73 : "=a" (a), "=c" (c) |
74 : | |
75 : "cc" | |
76 ); | |
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77 #undef PUSHF |
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78 #undef POPF |
2272 | 79 |
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80 return a != c; |
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81 } |
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82 |
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83 static void |
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84 do_cpuid(unsigned int ax, unsigned int *p) |
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85 { |
2272 | 86 #if 0 |
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87 __asm__ volatile( |
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88 "cpuid;" |
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89 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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90 : "0" (ax) |
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91 ); |
2272 | 92 #else |
93 // code from libavcodec: | |
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94 __asm__ volatile |
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95 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 96 "cpuid\n\t" |
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97 "xchg %%"REG_b", %%"REG_S |
3403 | 98 : "=a" (p[0]), "=S" (p[1]), |
2272 | 99 "=c" (p[2]), "=d" (p[3]) |
100 : "0" (ax)); | |
101 #endif | |
102 | |
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103 } |
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104 |
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105 void GetCpuCaps( CpuCaps *caps) |
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106 { |
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107 unsigned int regs[4]; |
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108 unsigned int regs2[4]; |
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109 |
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111 caps->isX86=1; |
8860 | 112 caps->cl_size=32; /* default */ |
2288 | 113 if (!has_cpuid()) { |
6134 | 114 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 115 return; |
116 } | |
117 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 118 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 119 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 120 if (regs[0]>=0x00000001) |
2280 | 121 { |
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122 char *tmpstr, *ptmpstr; |
8860 | 123 unsigned cl_size; |
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124 |
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125 do_cpuid(0x00000001, regs2); |
2301 | 126 |
2288 | 127 caps->cpuType=(regs2[0] >> 8)&0xf; |
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128 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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129 |
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130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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131 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 132 if(caps->cpuType==0xf){ |
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133 // use extended family (P4, IA64, K8) |
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134 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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135 } |
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136 if(caps->cpuType==0xf || caps->cpuType==6) |
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137 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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138 |
3403 | 139 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 140 |
141 // general feature flags: | |
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142 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 143 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
144 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
145 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
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146 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 |
28015 | 147 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 |
2288 | 148 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 149 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
150 if(cl_size) caps->cl_size = cl_size; | |
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151 |
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152 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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153 while(*ptmpstr == ' ') // strip leading spaces |
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154 ptmpstr++; |
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155 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); |
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156 free(tmpstr); |
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157 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", |
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158 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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159 |
2288 | 160 } |
161 do_cpuid(0x80000000, regs); | |
162 if (regs[0]>=0x80000001) { | |
6134 | 163 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 164 do_cpuid(0x80000001, regs2); |
3840 | 165 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
166 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 167 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
168 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
28015 | 169 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 |
2288 | 170 } |
8860 | 171 if(regs[0]>=0x80000006) |
172 { | |
173 do_cpuid(0x80000006, regs2); | |
174 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
175 caps->cl_size = regs2[2] & 0xFF; | |
176 } | |
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177 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 178 #if 0 |
5937 | 179 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 180 gCpuCaps.hasMMX, |
181 gCpuCaps.hasMMX2, | |
182 gCpuCaps.hasSSE, | |
183 gCpuCaps.hasSSE2, | |
184 gCpuCaps.has3DNow, | |
185 gCpuCaps.has3DNowExt ); | |
186 #endif | |
187 | |
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188 /* FIXME: Does SSE2 need more OS support, too? */ |
26060 | 189 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
190 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \ | |
26061 | 191 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \ |
192 || defined(__OS2__) | |
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193 if (caps->hasSSE) |
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194 check_os_katmai_support(); |
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195 if (!caps->hasSSE) |
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196 caps->hasSSE2 = 0; |
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197 #else |
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198 caps->hasSSE=0; |
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199 caps->hasSSE2 = 0; |
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200 #endif |
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201 // caps->has3DNow=1; |
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202 // caps->hasMMX2 = 0; |
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203 // caps->hasMMX = 0; |
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204 |
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205 #ifndef RUNTIME_CPUDETECT |
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206 #if !HAVE_MMX |
6134 | 207 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 208 caps->hasMMX=0; |
209 #endif | |
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210 #if !HAVE_MMX2 |
6134 | 211 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 212 caps->hasMMX2=0; |
213 #endif | |
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214 #if !HAVE_SSE |
6134 | 215 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 216 caps->hasSSE=0; |
217 #endif | |
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218 #if !HAVE_SSE2 |
6134 | 219 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 220 caps->hasSSE2=0; |
221 #endif | |
28335 | 222 #if !HAVE_AMD3DNOW |
6134 | 223 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 224 caps->has3DNow=0; |
225 #endif | |
28335 | 226 #if !HAVE_AMD3DNOWEXT |
6134 | 227 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 228 caps->has3DNowExt=0; |
229 #endif | |
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230 #endif // RUNTIME_CPUDETECT |
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231 } |
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232 |
2301 | 233 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
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234 char vendor[13]; |
2303 | 235 char *retname; |
13628 | 236 int i; |
2301 | 237 |
18869 | 238 if (NULL==(retname=malloc(256))) { |
5937 | 239 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 240 exit(1); |
241 } | |
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242 retname[0] = '\0'; |
2303 | 243 |
3837 | 244 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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245 |
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246 do_cpuid(0x80000000,regs); |
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247 if (regs[0] >= 0x80000004) |
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248 { |
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249 // CPU has built-in namestring |
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250 for (i = 0x80000002; i <= 0x80000004; i++) |
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251 { |
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252 do_cpuid(i, regs); |
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253 strncat(retname, (char*)regs, 16); |
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254 } |
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255 } |
2301 | 256 return retname; |
257 } | |
258 | |
28295 | 259 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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260 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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261 { |
6134 | 262 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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263 |
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264 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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265 * instructions are 3 bytes long. We must increment the instruction |
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266 * pointer manually to avoid repeated execution of the offending |
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267 * instruction. |
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268 * |
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269 * If the SIGILL is caused by a divide-by-zero when unmasked |
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270 * exceptions aren't supported, the SIMD FPU status and control |
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271 * word will be restored at the end of the test, so we don't need |
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272 * to worry about doing it here. Besides, we may not be able to... |
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273 */ |
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274 sc.eip += 3; |
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275 |
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276 gCpuCaps.hasSSE=0; |
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277 } |
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278 #endif /* __linux__ && _POSIX_SOURCE */ |
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279 |
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280 #if defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 281 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
282 { | |
283 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
284 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
285 ep->ContextRecord->Eip +=3; | |
286 gCpuCaps.hasSSE=0; | |
287 return EXCEPTION_CONTINUE_EXECUTION; | |
288 } | |
289 return EXCEPTION_CONTINUE_SEARCH; | |
290 } | |
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291 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 292 |
26061 | 293 #ifdef __OS2__ |
294 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
295 PEXCEPTIONREGISTRATIONRECORD p2, | |
296 PCONTEXTRECORD p3, | |
297 PVOID p4 ) | |
298 { | |
299 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
300 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
301 | |
302 p3->ctx_RegEip += 3; | |
303 gCpuCaps.hasSSE = 0; | |
304 | |
305 return XCPT_CONTINUE_EXECUTION; | |
306 } | |
307 return XCPT_CONTINUE_SEARCH; | |
308 } | |
309 #endif | |
310 | |
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311 /* If we're running on a processor that can do SSE, let's see if we |
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312 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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313 * haven't been configured for a Pentium III but are running on one, |
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314 * and RedHat patched 2.2 kernels that have broken exception handling |
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315 * support for user space apps that do SSE. |
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316 */ |
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317 |
21848 | 318 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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319 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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320 #elif defined(__APPLE__) |
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321 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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322 #endif |
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323 |
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324 static void check_os_katmai_support( void ) |
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325 { |
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326 #if ARCH_X86_64 |
14455 | 327 gCpuCaps.hasSSE=1; |
328 gCpuCaps.hasSSE2=1; | |
21848 | 329 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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330 int has_sse=0, ret; |
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331 size_t len=sizeof(has_sse); |
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332 |
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333 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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334 if (ret || !has_sse) |
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335 gCpuCaps.hasSSE=0; |
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336 |
12143 | 337 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
338 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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339 int has_sse, has_sse2, ret, mib[2]; |
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340 size_t varlen; |
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341 |
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342 mib[0] = CTL_MACHDEP; |
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343 mib[1] = CPU_SSE; |
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344 varlen = sizeof(has_sse); |
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345 |
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346 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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347 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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348 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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349 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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350 |
8533
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351 mib[1] = CPU_SSE2; |
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352 varlen = sizeof(has_sse2); |
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353 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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354 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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355 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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356 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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357 #else |
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358 gCpuCaps.hasSSE = 0; |
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359 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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360 #endif |
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361 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 362 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
363 if ( gCpuCaps.hasSSE ) { | |
364 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
365 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
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366 __asm__ volatile ("xorps %xmm0, %xmm0"); |
10440 | 367 SetUnhandledExceptionFilter(exc_fil); |
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368 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
10440 | 369 } |
26061 | 370 #elif defined(__OS2__) |
371 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
372 if ( gCpuCaps.hasSSE ) { | |
373 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
374 DosSetExceptionHandler( &RegRec ); | |
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375 __asm__ volatile ("xorps %xmm0, %xmm0"); |
26061 | 376 DosUnsetExceptionHandler( &RegRec ); |
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377 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
26061 | 378 } |
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379 #elif defined(__linux__) |
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380 #if defined(_POSIX_SOURCE) |
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381 struct sigaction saved_sigill; |
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382 |
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383 /* Save the original signal handlers. |
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384 */ |
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385 sigaction( SIGILL, NULL, &saved_sigill ); |
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386 |
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387 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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388 |
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389 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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390 * supports the extended FPU save and restore required for SSE. If |
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arpi
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391 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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392 * doesn't support Streaming SIMD Exceptions, even if the processor |
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393 * does. |
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394 */ |
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395 if ( gCpuCaps.hasSSE ) { |
6134 | 396 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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397 |
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398 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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399 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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400 |
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401 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
2268
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402 } |
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403 |
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404 /* Restore the original signal handlers. |
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arpi
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405 */ |
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406 sigaction( SIGILL, &saved_sigill, NULL ); |
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407 |
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408 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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409 * safe to go ahead and hook out the SSE code throughout Mesa. |
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410 */ |
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411 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
2268
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412 #else |
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413 /* We can't use POSIX signal handling to test the availability of |
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arpi
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414 * SSE, so we disable it by default. |
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arpi
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415 */ |
5937 | 416 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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417 gCpuCaps.hasSSE=0; |
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418 #endif /* _POSIX_SOURCE */ |
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419 #else |
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420 /* Do nothing on other platforms for now. |
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arpi
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421 */ |
6134 | 422 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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423 gCpuCaps.hasSSE=0; |
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arpi
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424 #endif /* __linux__ */ |
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arpi
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425 } |
20577 | 426 #else /* ARCH_X86 */ |
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michael
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427 |
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428 #ifdef __APPLE__ |
9003 | 429 #include <sys/sysctl.h> |
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430 #elif defined(__AMIGAOS4__) |
25338
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Ahem, fix breakage of last commit: The AltiVec detection code has three
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431 /* nothing */ |
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432 #else |
9003 | 433 #include <signal.h> |
434 #include <setjmp.h> | |
435 | |
436 static sigjmp_buf jmpbuf; | |
437 static volatile sig_atomic_t canjump = 0; | |
438 | |
439 static void sigill_handler (int sig) | |
440 { | |
441 if (!canjump) { | |
442 signal (sig, SIG_DFL); | |
443 raise (sig); | |
444 } | |
445 | |
446 canjump = 0; | |
447 siglongjmp (jmpbuf, 1); | |
448 } | |
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449 #endif /* __APPLE__ */ |
9003 | 450 |
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451 void GetCpuCaps( CpuCaps *caps) |
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452 { |
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453 caps->cpuType=0; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
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454 caps->cpuModel=0; |
3403 | 455 caps->cpuStepping=0; |
3146
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456 caps->hasMMX=0; |
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457 caps->hasMMX2=0; |
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458 caps->has3DNow=0; |
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459 caps->has3DNowExt=0; |
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460 caps->hasSSE=0; |
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461 caps->hasSSE2=0; |
28901
e1b7d9bf263b
SSE3 support patch by Zhou Zongyi, zhouzongyi pset.suntec net
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462 caps->hasSSE3=0; |
27926
a02c39208d49
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gpoirier
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463 caps->hasSSSE3=0; |
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464 caps->hasSSE4a=0; |
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465 caps->isX86=0; |
9003 | 466 caps->hasAltiVec = 0; |
28297
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gpoirier
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|
467 #if HAVE_ALTIVEC |
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468 #ifdef __APPLE__ |
9003 | 469 /* |
470 rip-off from ffmpeg altivec detection code. | |
471 this code also appears on Apple's AltiVec pages. | |
472 */ | |
473 { | |
474 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
475 int has_vu = 0; | |
476 size_t len = sizeof(has_vu); | |
477 int err; | |
478 | |
479 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
480 | |
481 if (err == 0) | |
482 if (has_vu != 0) | |
483 caps->hasAltiVec = 1; | |
484 } | |
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485 #elif defined(__AMIGAOS4__) |
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486 ULONG result = 0; |
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487 |
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488 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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489 if (result == VECTORTYPE_ALTIVEC) |
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490 caps->hasAltiVec = 1; |
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491 #else |
9003 | 492 /* no Darwin, do it the brute-force way */ |
493 /* this is borrowed from the libmpeg2 library */ | |
494 { | |
495 signal (SIGILL, sigill_handler); | |
496 if (sigsetjmp (jmpbuf, 1)) { | |
497 signal (SIGILL, SIG_DFL); | |
498 } else { | |
499 canjump = 1; | |
500 | |
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501 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 502 "vand %%v0, %%v0, %%v0" |
9003 | 503 : |
504 : "r" (-1)); | |
505 | |
506 signal (SIGILL, SIG_DFL); | |
507 caps->hasAltiVec = 1; | |
508 } | |
509 } | |
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510 #endif /* __APPLE__ */ |
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Print information about detected CPU in verbose mode only.
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511 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 512 #endif /* HAVE_ALTIVEC */ |
11962
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gabucino
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513 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
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514 if (ARCH_IA64) |
28458
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515 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); |
11962
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gabucino
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516 |
28342
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diego
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changeset
|
517 if (ARCH_SPARC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
518 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
519 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
520 if (ARCH_ARM) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
521 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
522 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
523 if (ARCH_PPC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
524 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
525 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
526 if (ARCH_ALPHA) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
527 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
528 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
529 if (ARCH_SGI_MIPS) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
530 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
531 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
532 if (ARCH_PA_RISC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
533 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
534 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
535 if (ARCH_S390) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
536 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
537 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
538 if (ARCH_S390X) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
539 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
540 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
541 if (ARCH_VAX) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
542 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); |
25340 | 543 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
544 if (ARCH_XTENSA) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
545 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
546 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
547 #endif /* !ARCH_X86 */ |