Mercurial > mplayer.hg
annotate cpudetect.c @ 32799:9855da8e3aa9
Revert r32884: For some files, -demuxer lavf is needed to playback XAN DPCM audio.
author | cehoyos |
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date | Fri, 11 Feb 2011 12:50:49 +0000 |
parents | fdf3f93c2828 |
children | 5e3f013bf4c2 |
rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
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19 #include "config.h" |
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20 #include "cpudetect.h" |
5937 | 21 #include "mp_msg.h" |
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22 |
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23 CpuCaps gCpuCaps; |
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24 |
3837 | 25 #include <stdlib.h> |
26 | |
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27 #if ARCH_X86 |
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28 |
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29 #include <stdio.h> |
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30 #include <string.h> |
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31 |
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33 #include <sys/param.h> |
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34 #include <sys/sysctl.h> |
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35 #include <machine/cpu.h> |
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36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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37 #include <sys/types.h> |
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38 #include <sys/sysctl.h> |
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39 #elif defined(__linux__) |
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40 #include <signal.h> |
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41 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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43 #elif defined(__OS2__) |
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45 #include <os2.h> | |
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46 #elif defined(__AMIGAOS4__) |
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47 #include <proto/exec.h> |
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48 #endif |
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49 |
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50 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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51 * help understanding how to use it. Thanks to the Mesa |
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52 * team for SSE support detection and more cpu detect code. |
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53 */ |
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54 |
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55 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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56 |
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57 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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58 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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59 { |
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60 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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61 |
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62 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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63 * instructions are 3 bytes long. We must increment the instruction |
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64 * pointer manually to avoid repeated execution of the offending |
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65 * instruction. |
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66 * |
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67 * If the SIGILL is caused by a divide-by-zero when unmasked |
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68 * exceptions aren't supported, the SIMD FPU status and control |
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69 * word will be restored at the end of the test, so we don't need |
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70 * to worry about doing it here. Besides, we may not be able to... |
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71 */ |
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72 sc.eip += 3; |
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73 |
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74 gCpuCaps.hasSSE=0; |
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75 } |
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76 #endif /* __linux__ && _POSIX_SOURCE */ |
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77 |
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78 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
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79 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
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80 { |
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81 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ |
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82 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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83 ep->ContextRecord->Eip +=3; |
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84 gCpuCaps.hasSSE=0; |
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85 return EXCEPTION_CONTINUE_EXECUTION; |
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86 } |
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87 return EXCEPTION_CONTINUE_SEARCH; |
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88 } |
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89 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
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90 |
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91 #ifdef __OS2__ |
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92 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1, |
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93 PEXCEPTIONREGISTRATIONRECORD p2, |
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94 PCONTEXTRECORD p3, |
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95 PVOID p4) |
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96 { |
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97 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ |
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98 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); |
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99 |
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100 p3->ctx_RegEip += 3; |
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101 gCpuCaps.hasSSE = 0; |
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102 |
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103 return XCPT_CONTINUE_EXECUTION; |
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104 } |
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105 return XCPT_CONTINUE_SEARCH; |
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106 } |
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107 #endif |
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108 |
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109 /* If we're running on a processor that can do SSE, let's see if we |
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110 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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111 * haven't been configured for a Pentium III but are running on one, |
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112 * and RedHat patched 2.2 kernels that have broken exception handling |
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113 * support for user space apps that do SSE. |
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114 */ |
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115 |
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116 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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117 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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118 #elif defined(__APPLE__) |
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119 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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120 #endif |
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121 |
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122 static void check_os_katmai_support( void ) |
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123 { |
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124 #if ARCH_X86_64 |
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125 gCpuCaps.hasSSE=1; |
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126 gCpuCaps.hasSSE2=1; |
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127 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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128 int has_sse=0, ret; |
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129 size_t len=sizeof(has_sse); |
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130 |
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131 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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132 if (ret || !has_sse) |
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133 gCpuCaps.hasSSE=0; |
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134 |
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135 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
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136 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) |
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137 int has_sse, has_sse2, ret, mib[2]; |
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138 size_t varlen; |
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139 |
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140 mib[0] = CTL_MACHDEP; |
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141 mib[1] = CPU_SSE; |
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142 varlen = sizeof(has_sse); |
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143 |
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144 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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145 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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146 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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147 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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148 |
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149 mib[1] = CPU_SSE2; |
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150 varlen = sizeof(has_sse2); |
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151 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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152 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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153 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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154 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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155 #else |
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156 gCpuCaps.hasSSE = 0; |
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157 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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158 #endif |
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159 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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160 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
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161 if ( gCpuCaps.hasSSE ) { |
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162 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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163 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); |
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164 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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165 SetUnhandledExceptionFilter(exc_fil); |
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166 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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167 } |
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168 #elif defined(__OS2__) |
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169 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; |
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170 if ( gCpuCaps.hasSSE ) { |
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171 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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172 DosSetExceptionHandler( &RegRec ); |
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173 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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174 DosUnsetExceptionHandler( &RegRec ); |
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175 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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176 } |
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177 #elif defined(__linux__) |
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178 #if defined(_POSIX_SOURCE) |
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179 struct sigaction saved_sigill; |
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180 |
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181 /* Save the original signal handlers. |
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182 */ |
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183 sigaction( SIGILL, NULL, &saved_sigill ); |
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184 |
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185 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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186 |
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187 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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188 * supports the extended FPU save and restore required for SSE. If |
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189 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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190 * doesn't support Streaming SIMD Exceptions, even if the processor |
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191 * does. |
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192 */ |
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193 if ( gCpuCaps.hasSSE ) { |
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194 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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195 |
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196 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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197 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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198 |
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199 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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200 } |
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201 |
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202 /* Restore the original signal handlers. |
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203 */ |
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204 sigaction( SIGILL, &saved_sigill, NULL ); |
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205 |
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206 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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207 * safe to go ahead and hook out the SSE code throughout Mesa. |
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208 */ |
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209 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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210 #else |
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211 /* We can't use POSIX signal handling to test the availability of |
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212 * SSE, so we disable it by default. |
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213 */ |
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214 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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215 gCpuCaps.hasSSE=0; |
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216 #endif /* _POSIX_SOURCE */ |
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217 #else |
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218 /* Do nothing on other platforms for now. |
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219 */ |
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220 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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221 gCpuCaps.hasSSE=0; |
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222 #endif /* __linux__ */ |
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223 } |
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224 |
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225 |
2272 | 226 // return TRUE if cpuid supported |
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227 static int has_cpuid(void) |
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228 { |
2272 | 229 // code from libavcodec: |
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230 #if ARCH_X86_64 |
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231 return 1; |
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232 #else |
31077 | 233 long a, c; |
234 __asm__ volatile ( | |
235 /* See if CPUID instruction is supported ... */ | |
236 /* ... Get copies of EFLAGS into eax and ecx */ | |
237 "pushfl\n\t" | |
238 "pop %0\n\t" | |
239 "mov %0, %1\n\t" | |
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240 |
31077 | 241 /* ... Toggle the ID bit in one copy and store */ |
242 /* to the EFLAGS reg */ | |
243 "xor $0x200000, %0\n\t" | |
244 "push %0\n\t" | |
245 "popfl\n\t" | |
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246 |
31077 | 247 /* ... Get the (hopefully modified) EFLAGS */ |
248 "pushfl\n\t" | |
249 "pop %0\n\t" | |
250 : "=a" (a), "=c" (c) | |
251 : | |
252 : "cc" | |
253 ); | |
2272 | 254 |
31077 | 255 return a != c; |
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256 #endif |
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257 } |
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258 |
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259 void |
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260 do_cpuid(unsigned int ax, unsigned int *p) |
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261 { |
2272 | 262 // code from libavcodec: |
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263 __asm__ volatile |
31077 | 264 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 265 "cpuid\n\t" |
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266 "xchg %%"REG_b", %%"REG_S |
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267 : "=a" (p[0]), "=S" (p[1]), |
2272 | 268 "=c" (p[2]), "=d" (p[3]) |
269 : "0" (ax)); | |
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270 } |
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271 |
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272 void GetCpuCaps( CpuCaps *caps) |
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273 { |
31077 | 274 unsigned int regs[4]; |
275 unsigned int regs2[4]; | |
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276 |
31077 | 277 memset(caps, 0, sizeof(*caps)); |
278 caps->isX86=1; | |
279 caps->cl_size=32; /* default */ | |
280 if (!has_cpuid()) { | |
281 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); | |
282 return; | |
283 } | |
284 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
285 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", | |
286 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
287 if (regs[0]>=0x00000001) | |
288 { | |
289 char *tmpstr, *ptmpstr; | |
290 unsigned cl_size; | |
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291 |
31077 | 292 do_cpuid(0x00000001, regs2); |
2301 | 293 |
31077 | 294 caps->cpuType=(regs2[0] >> 8)&0xf; |
295 caps->cpuModel=(regs2[0] >> 4)&0xf; | |
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296 |
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297 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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298 // System Instructions, Table 3-2: Effective family computation, page 120. |
31077 | 299 if(caps->cpuType==0xf){ |
300 // use extended family (P4, IA64, K8) | |
301 caps->cpuType=0xf+((regs2[0]>>20)&255); | |
302 } | |
303 if(caps->cpuType==0xf || caps->cpuType==6) | |
304 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; | |
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305 |
31077 | 306 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 307 |
31077 | 308 // general feature flags: |
309 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 | |
310 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
311 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
312 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
313 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 | |
314 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 | |
315 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too | |
316 cl_size = ((regs2[1] >> 8) & 0xFF)*8; | |
317 if(cl_size) caps->cl_size = cl_size; | |
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318 |
31077 | 319 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
320 while(*ptmpstr == ' ') // strip leading spaces | |
321 ptmpstr++; | |
322 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); | |
323 free(tmpstr); | |
324 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", | |
325 caps->cpuType, caps->cpuModel, caps->cpuStepping); | |
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326 |
31077 | 327 } |
328 do_cpuid(0x80000000, regs); | |
329 if (regs[0]>=0x80000001) { | |
330 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
331 do_cpuid(0x80000001, regs2); | |
332 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
333 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
334 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 | |
335 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
336 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 | |
337 } | |
338 if(regs[0]>=0x80000006) | |
339 { | |
340 do_cpuid(0x80000006, regs2); | |
341 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
342 caps->cl_size = regs2[2] & 0xFF; | |
343 } | |
344 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 345 #if 0 |
31077 | 346 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
347 gCpuCaps.hasMMX, | |
348 gCpuCaps.hasMMX2, | |
349 gCpuCaps.hasSSE, | |
350 gCpuCaps.hasSSE2, | |
351 gCpuCaps.has3DNow, | |
352 gCpuCaps.has3DNowExt); | |
2288 | 353 #endif |
354 | |
31077 | 355 /* FIXME: Does SSE2 need more OS support, too? */ |
356 if (caps->hasSSE) | |
357 check_os_katmai_support(); | |
358 if (!caps->hasSSE) | |
359 caps->hasSSE2 = 0; | |
360 // caps->has3DNow=1; | |
361 // caps->hasMMX2 = 0; | |
362 // caps->hasMMX = 0; | |
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363 |
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364 #if !CONFIG_RUNTIME_CPUDETECT |
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365 #if !HAVE_MMX |
31077 | 366 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
367 caps->hasMMX=0; | |
4829 | 368 #endif |
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369 #if !HAVE_MMX2 |
31077 | 370 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
371 caps->hasMMX2=0; | |
4829 | 372 #endif |
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373 #if !HAVE_SSE |
31077 | 374 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
375 caps->hasSSE=0; | |
4829 | 376 #endif |
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377 #if !HAVE_SSE2 |
31077 | 378 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
379 caps->hasSSE2=0; | |
4829 | 380 #endif |
28335 | 381 #if !HAVE_AMD3DNOW |
31077 | 382 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
383 caps->has3DNow=0; | |
4829 | 384 #endif |
28335 | 385 #if !HAVE_AMD3DNOWEXT |
31077 | 386 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
387 caps->has3DNowExt=0; | |
4829 | 388 #endif |
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389 #endif // CONFIG_RUNTIME_CPUDETECT |
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390 } |
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391 |
2301 | 392 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
31077 | 393 char vendor[13]; |
394 char *retname; | |
395 int i; | |
2301 | 396 |
31077 | 397 if (NULL==(retname=malloc(256))) { |
398 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); | |
399 exit(1); | |
400 } | |
401 retname[0] = '\0'; | |
2303 | 402 |
31077 | 403 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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404 |
31077 | 405 do_cpuid(0x80000000,regs); |
406 if (regs[0] >= 0x80000004) | |
407 { | |
408 // CPU has built-in namestring | |
409 for (i = 0x80000002; i <= 0x80000004; i++) | |
410 { | |
411 do_cpuid(i, regs); | |
412 strncat(retname, (char*)regs, 16); | |
413 } | |
414 } | |
415 return retname; | |
2301 | 416 } |
417 | |
20577 | 418 #else /* ARCH_X86 */ |
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419 |
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420 #ifdef __APPLE__ |
9003 | 421 #include <sys/sysctl.h> |
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422 #elif defined(__AMIGAOS4__) |
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423 /* nothing */ |
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424 #else |
9003 | 425 #include <signal.h> |
426 #include <setjmp.h> | |
427 | |
428 static sigjmp_buf jmpbuf; | |
429 static volatile sig_atomic_t canjump = 0; | |
430 | |
431 static void sigill_handler (int sig) | |
432 { | |
433 if (!canjump) { | |
434 signal (sig, SIG_DFL); | |
435 raise (sig); | |
436 } | |
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437 |
9003 | 438 canjump = 0; |
439 siglongjmp (jmpbuf, 1); | |
440 } | |
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441 #endif /* __APPLE__ */ |
9003 | 442 |
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443 void GetCpuCaps( CpuCaps *caps) |
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444 { |
31077 | 445 caps->cpuType=0; |
446 caps->cpuModel=0; | |
447 caps->cpuStepping=0; | |
448 caps->hasMMX=0; | |
449 caps->hasMMX2=0; | |
450 caps->has3DNow=0; | |
451 caps->has3DNowExt=0; | |
452 caps->hasSSE=0; | |
453 caps->hasSSE2=0; | |
454 caps->hasSSE3=0; | |
455 caps->hasSSSE3=0; | |
456 caps->hasSSE4a=0; | |
457 caps->isX86=0; | |
458 caps->hasAltiVec = 0; | |
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459 #if HAVE_ALTIVEC |
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460 #ifdef __APPLE__ |
9003 | 461 /* |
462 rip-off from ffmpeg altivec detection code. | |
463 this code also appears on Apple's AltiVec pages. | |
464 */ | |
31077 | 465 { |
466 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
467 int has_vu = 0; | |
468 size_t len = sizeof(has_vu); | |
469 int err; | |
9003 | 470 |
31077 | 471 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 472 |
31077 | 473 if (err == 0) |
474 if (has_vu != 0) | |
475 caps->hasAltiVec = 1; | |
476 } | |
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477 #elif defined(__AMIGAOS4__) |
31077 | 478 ULONG result = 0; |
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479 |
31077 | 480 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
481 if (result == VECTORTYPE_ALTIVEC) | |
482 caps->hasAltiVec = 1; | |
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483 #else |
9003 | 484 /* no Darwin, do it the brute-force way */ |
485 /* this is borrowed from the libmpeg2 library */ | |
31077 | 486 { |
487 signal (SIGILL, sigill_handler); | |
488 if (sigsetjmp (jmpbuf, 1)) { | |
9003 | 489 signal (SIGILL, SIG_DFL); |
31077 | 490 } else { |
9003 | 491 canjump = 1; |
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492 |
31077 | 493 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 494 "vand %%v0, %%v0, %%v0" |
9003 | 495 : |
496 : "r" (-1)); | |
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497 |
31077 | 498 signal (SIGILL, SIG_DFL); |
499 caps->hasAltiVec = 1; | |
9003 | 500 } |
31077 | 501 } |
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502 #endif /* __APPLE__ */ |
31077 | 503 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 504 #endif /* HAVE_ALTIVEC */ |
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505 |
31077 | 506 if (ARCH_IA64) |
507 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); | |
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508 |
31077 | 509 if (ARCH_SPARC) |
510 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); | |
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511 |
31077 | 512 if (ARCH_ARM) |
513 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); | |
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514 |
31077 | 515 if (ARCH_PPC) |
516 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); | |
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517 |
31077 | 518 if (ARCH_ALPHA) |
519 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); | |
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520 |
31077 | 521 if (ARCH_MIPS) |
522 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
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523 |
31077 | 524 if (ARCH_PA_RISC) |
525 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); | |
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526 |
31077 | 527 if (ARCH_S390) |
528 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); | |
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529 |
31077 | 530 if (ARCH_S390X) |
531 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); | |
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532 |
31077 | 533 if (ARCH_VAX) |
534 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); | |
25340 | 535 |
31077 | 536 if (ARCH_XTENSA) |
537 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); | |
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538 } |
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539 #endif /* !ARCH_X86 */ |