Mercurial > mplayer.hg
annotate cpudetect.c @ 23510:a6c619ee9d30
Teletext support for tv:// (v4l and v4l2 only)
modified patch from Otvos Attila oattila at chello dot hu
Module uses zvbi library for all low-level VBI operations (like I/O with vbi
device, converting vbi pages into usefull vbi_page stuctures, rendering them
into RGB32 images).
All teletext related stuff (except properties, slave commands and rendering
osd in text mode or RGB32 rendered teletext pages in spu mode) is implemented
in tvi_vbi.c
New properties:
teletext_page - switching between pages
teletext_mode - switch between on/off/opaque/transparent modes
teletext_format - (currently read-only) allows to get format info
(black/white,gray,text)
teletext_half_page - trivial zooming (displaying top/bottom half of teletext
page)
New slave commands:
teletext_add_dec - user interface for jumping to any page by editing page number
interactively
teletext_go_link - goes though links, specified on current page
author | voroshil |
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date | Sun, 10 Jun 2007 00:06:12 +0000 |
parents | 3ff1eade91f9 |
children | 2f31f31deccc |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
20577 | 12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
21848 | 23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
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36 #ifdef __AMIGAOS4__ |
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37 #include <proto/exec.h> |
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38 #endif |
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39 |
2272 | 40 //#define X86_FXSR_MAGIC |
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41 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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42 * help understanding how to use it. Thanks to the Mesa |
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43 * team for SSE support detection and more cpu detect code. |
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44 */ |
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45 |
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46 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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47 |
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48 static void check_os_katmai_support( void ); |
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49 |
2272 | 50 #if 1 |
51 // return TRUE if cpuid supported | |
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52 static int has_cpuid(void) |
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53 { |
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54 long a, c; |
2272 | 55 |
56 // code from libavcodec: | |
57 __asm__ __volatile__ ( | |
58 /* See if CPUID instruction is supported ... */ | |
59 /* ... Get copies of EFLAGS into eax and ecx */ | |
60 "pushf\n\t" | |
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61 "pop %0\n\t" |
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62 "mov %0, %1\n\t" |
2272 | 63 |
64 /* ... Toggle the ID bit in one copy and store */ | |
65 /* to the EFLAGS reg */ | |
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66 "xor $0x200000, %0\n\t" |
2272 | 67 "push %0\n\t" |
68 "popf\n\t" | |
69 | |
70 /* ... Get the (hopefully modified) EFLAGS */ | |
71 "pushf\n\t" | |
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72 "pop %0\n\t" |
2272 | 73 : "=a" (a), "=c" (c) |
74 : | |
75 : "cc" | |
76 ); | |
77 | |
78 return (a!=c); | |
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79 } |
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80 #endif |
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81 |
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82 static void |
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83 do_cpuid(unsigned int ax, unsigned int *p) |
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84 { |
2272 | 85 #if 0 |
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86 __asm __volatile( |
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87 "cpuid;" |
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88 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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89 : "0" (ax) |
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90 ); |
2272 | 91 #else |
92 // code from libavcodec: | |
93 __asm __volatile | |
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94 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 95 "cpuid\n\t" |
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96 "xchg %%"REG_b", %%"REG_S |
3403 | 97 : "=a" (p[0]), "=S" (p[1]), |
2272 | 98 "=c" (p[2]), "=d" (p[3]) |
99 : "0" (ax)); | |
100 #endif | |
101 | |
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102 } |
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103 |
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104 void GetCpuCaps( CpuCaps *caps) |
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105 { |
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106 unsigned int regs[4]; |
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107 unsigned int regs2[4]; |
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108 |
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110 caps->isX86=1; |
8860 | 111 caps->cl_size=32; /* default */ |
2288 | 112 if (!has_cpuid()) { |
6134 | 113 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 114 return; |
115 } | |
116 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 117 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 118 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 119 if (regs[0]>=0x00000001) |
2280 | 120 { |
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121 char *tmpstr, *ptmpstr; |
8860 | 122 unsigned cl_size; |
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123 |
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124 do_cpuid(0x00000001, regs2); |
2301 | 125 |
2288 | 126 caps->cpuType=(regs2[0] >> 8)&0xf; |
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127 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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128 |
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129 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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130 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 131 if(caps->cpuType==0xf){ |
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132 // use extended family (P4, IA64, K8) |
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133 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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134 } |
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135 if(caps->cpuType==0xf || caps->cpuType==6) |
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136 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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137 |
3403 | 138 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 139 |
140 // general feature flags: | |
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141 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 142 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
143 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
144 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 145 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 146 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
147 if(cl_size) caps->cl_size = cl_size; | |
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148 |
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149 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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150 while(*ptmpstr == ' ') // strip leading spaces |
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151 ptmpstr++; |
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152 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
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153 free(tmpstr); |
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154 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
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155 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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156 |
2288 | 157 } |
158 do_cpuid(0x80000000, regs); | |
159 if (regs[0]>=0x80000001) { | |
6134 | 160 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 161 do_cpuid(0x80000001, regs2); |
3840 | 162 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
163 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 164 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
165 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
166 } | |
8860 | 167 if(regs[0]>=0x80000006) |
168 { | |
169 do_cpuid(0x80000006, regs2); | |
170 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
171 caps->cl_size = regs2[2] & 0xFF; | |
172 } | |
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173 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 174 #if 0 |
5937 | 175 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 176 gCpuCaps.hasMMX, |
177 gCpuCaps.hasMMX2, | |
178 gCpuCaps.hasSSE, | |
179 gCpuCaps.hasSSE2, | |
180 gCpuCaps.has3DNow, | |
181 gCpuCaps.has3DNowExt ); | |
182 #endif | |
183 | |
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184 /* FIXME: Does SSE2 need more OS support, too? */ |
21848 | 185 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__) |
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186 if (caps->hasSSE) |
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187 check_os_katmai_support(); |
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188 if (!caps->hasSSE) |
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189 caps->hasSSE2 = 0; |
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190 #else |
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191 caps->hasSSE=0; |
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192 caps->hasSSE2 = 0; |
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193 #endif |
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194 // caps->has3DNow=1; |
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195 // caps->hasMMX2 = 0; |
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196 // caps->hasMMX = 0; |
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197 |
4829 | 198 #ifndef HAVE_MMX |
6134 | 199 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 200 caps->hasMMX=0; |
201 #endif | |
202 #ifndef HAVE_MMX2 | |
6134 | 203 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 204 caps->hasMMX2=0; |
205 #endif | |
206 #ifndef HAVE_SSE | |
6134 | 207 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 208 caps->hasSSE=0; |
209 #endif | |
210 #ifndef HAVE_SSE2 | |
6134 | 211 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 212 caps->hasSSE2=0; |
213 #endif | |
214 #ifndef HAVE_3DNOW | |
6134 | 215 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 216 caps->has3DNow=0; |
217 #endif | |
218 #ifndef HAVE_3DNOWEX | |
6134 | 219 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 220 caps->has3DNowExt=0; |
221 #endif | |
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222 } |
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223 |
2301 | 224 |
225 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
226 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
227 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
228 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
229 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
230 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
231 | |
232 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
233 #include "cputable.h" /* get cpuname and cpuvendors */ | |
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234 char vendor[13]; |
2303 | 235 char *retname; |
13628 | 236 int i; |
2301 | 237 |
18869 | 238 if (NULL==(retname=malloc(256))) { |
5937 | 239 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 240 exit(1); |
241 } | |
242 | |
3837 | 243 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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244 |
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245 do_cpuid(0x80000000,regs); |
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246 if (regs[0] >= 0x80000004) |
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247 { |
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248 // CPU has built-in namestring |
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249 retname[0] = '\0'; |
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250 for (i = 0x80000002; i <= 0x80000004; i++) |
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251 { |
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252 do_cpuid(i, regs); |
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253 strncat(retname, (char*)regs, 16); |
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254 } |
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255 return retname; |
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256 } |
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257 |
2301 | 258 for(i=0; i<MAX_VENDORS; i++){ |
259 if(!strcmp(cpuvendors[i].string,vendor)){ | |
260 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 261 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 262 } else { |
13628 | 263 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 264 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
265 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
266 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
267 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
268 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
269 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
270 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 271 "to the MPlayer-Developers, so we can add it to the list!\n"); |
272 } | |
273 } | |
274 } | |
14478 | 275 retname[255] = 0; |
2301 | 276 |
277 //printf("Detected CPU: %s\n", retname); | |
278 return retname; | |
279 } | |
280 | |
281 #undef CPUID_EXTFAMILY | |
282 #undef CPUID_EXTMODEL | |
283 #undef CPUID_TYPE | |
284 #undef CPUID_FAMILY | |
285 #undef CPUID_MODEL | |
286 #undef CPUID_STEPPING | |
287 | |
288 | |
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289 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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290 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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291 { |
6134 | 292 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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293 |
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294 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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295 * instructions are 3 bytes long. We must increment the instruction |
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296 * pointer manually to avoid repeated execution of the offending |
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297 * instruction. |
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298 * |
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299 * If the SIGILL is caused by a divide-by-zero when unmasked |
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300 * exceptions aren't supported, the SIMD FPU status and control |
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301 * word will be restored at the end of the test, so we don't need |
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302 * to worry about doing it here. Besides, we may not be able to... |
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303 */ |
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304 sc.eip += 3; |
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305 |
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306 gCpuCaps.hasSSE=0; |
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307 } |
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308 |
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309 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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310 { |
6134 | 311 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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312 |
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313 if ( sc.fpstate->magic != 0xffff ) { |
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314 /* Our signal context has the extended FPU state, so reset the |
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315 * divide-by-zero exception mask and clear the divide-by-zero |
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316 * exception bit. |
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317 */ |
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318 sc.fpstate->mxcsr |= 0x00000200; |
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319 sc.fpstate->mxcsr &= 0xfffffffb; |
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320 } else { |
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321 /* If we ever get here, we're completely hosed. |
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322 */ |
6134 | 323 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
324 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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325 } |
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326 } |
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327 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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328 |
10440 | 329 #ifdef WIN32 |
330 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
331 { | |
332 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
333 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
334 ep->ContextRecord->Eip +=3; | |
335 gCpuCaps.hasSSE=0; | |
336 return EXCEPTION_CONTINUE_EXECUTION; | |
337 } | |
338 return EXCEPTION_CONTINUE_SEARCH; | |
339 } | |
340 #endif /* WIN32 */ | |
341 | |
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342 /* If we're running on a processor that can do SSE, let's see if we |
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343 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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344 * haven't been configured for a Pentium III but are running on one, |
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345 * and RedHat patched 2.2 kernels that have broken exception handling |
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346 * support for user space apps that do SSE. |
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347 */ |
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348 |
21848 | 349 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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350 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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351 #elif defined(__APPLE__) |
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352 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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353 #endif |
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354 |
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355 static void check_os_katmai_support( void ) |
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356 { |
14455 | 357 #ifdef ARCH_X86_64 |
358 gCpuCaps.hasSSE=1; | |
359 gCpuCaps.hasSSE2=1; | |
21848 | 360 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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361 int has_sse=0, ret; |
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362 size_t len=sizeof(has_sse); |
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363 |
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364 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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365 if (ret || !has_sse) |
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366 gCpuCaps.hasSSE=0; |
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367 |
12143 | 368 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
369 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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370 int has_sse, has_sse2, ret, mib[2]; |
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371 size_t varlen; |
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372 |
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373 mib[0] = CTL_MACHDEP; |
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374 mib[1] = CPU_SSE; |
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375 varlen = sizeof(has_sse); |
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376 |
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377 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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378 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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379 if (ret < 0 || !has_sse) { |
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380 gCpuCaps.hasSSE=0; |
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381 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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382 } else { |
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Ok, here is a better patch, which even adds a fix to compile it on older
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383 gCpuCaps.hasSSE=1; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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384 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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385 } |
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Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
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386 |
8533
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387 mib[1] = CPU_SSE2; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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388 varlen = sizeof(has_sse2); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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389 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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390 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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391 if (ret < 0 || !has_sse2) { |
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Ok, here is a better patch, which even adds a fix to compile it on older
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392 gCpuCaps.hasSSE2=0; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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393 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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394 } else { |
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Ok, here is a better patch, which even adds a fix to compile it on older
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395 gCpuCaps.hasSSE2=1; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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396 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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397 } |
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398 #else |
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399 gCpuCaps.hasSSE = 0; |
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400 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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401 #endif |
10440 | 402 #elif defined(WIN32) |
403 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
404 if ( gCpuCaps.hasSSE ) { | |
405 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
406 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
407 __asm __volatile ("xorps %xmm0, %xmm0"); | |
408 SetUnhandledExceptionFilter(exc_fil); | |
409 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
410 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
411 } | |
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412 #elif defined(__linux__) |
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413 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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414 struct sigaction saved_sigill; |
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415 struct sigaction saved_sigfpe; |
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416 |
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417 /* Save the original signal handlers. |
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418 */ |
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419 sigaction( SIGILL, NULL, &saved_sigill ); |
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420 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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421 |
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422 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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423 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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424 |
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425 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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426 * supports the extended FPU save and restore required for SSE. If |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff
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427 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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428 * doesn't support Streaming SIMD Exceptions, even if the processor |
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429 * does. |
72ff2179d396
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arpi
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430 */ |
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arpi
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diff
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431 if ( gCpuCaps.hasSSE ) { |
6134 | 432 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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433 |
2272 | 434 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
435 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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436 |
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437 if ( gCpuCaps.hasSSE ) { |
6134 | 438 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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439 } else { |
6134 | 440 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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441 } |
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442 } |
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443 |
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444 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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arpi
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445 * it supports unmasked SIMD FPU exceptions. If we unmask the |
72ff2179d396
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arpi
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446 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
72ff2179d396
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arpi
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447 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
72ff2179d396
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arpi
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448 * as expected, we're okay but we need to clean up after it. |
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arpi
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449 * |
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arpi
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450 * Are we being too stringent in our requirement that the OS support |
72ff2179d396
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arpi
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451 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
72ff2179d396
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arpi
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diff
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452 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
72ff2179d396
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arpi
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453 * doesn't even support them. We at least know the user-space SSE |
72ff2179d396
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arpi
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454 * support is good in kernels that do support unmasked exceptions, |
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arpi
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455 * and therefore to be safe I'm going to leave this test in here. |
72ff2179d396
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456 */ |
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457 if ( gCpuCaps.hasSSE ) { |
6134 | 458 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
2268
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459 |
2272 | 460 // test_os_katmai_exception_support(); |
2268
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461 |
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462 if ( gCpuCaps.hasSSE ) { |
6134 | 463 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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464 } else { |
6134 | 465 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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466 } |
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467 } |
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arpi
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468 |
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arpi
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469 /* Restore the original signal handlers. |
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arpi
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470 */ |
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arpi
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471 sigaction( SIGILL, &saved_sigill, NULL ); |
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arpi
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diff
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472 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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arpi
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473 |
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arpi
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474 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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arpi
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475 * safe to go ahead and hook out the SSE code throughout Mesa. |
72ff2179d396
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arpi
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476 */ |
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arpi
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diff
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477 if ( gCpuCaps.hasSSE ) { |
6134 | 478 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
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479 } else { |
6134 | 480 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
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481 } |
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arpi
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482 #else |
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arpi
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diff
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483 /* We can't use POSIX signal handling to test the availability of |
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arpi
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484 * SSE, so we disable it by default. |
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485 */ |
5937 | 486 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
2268
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487 gCpuCaps.hasSSE=0; |
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488 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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489 #else |
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490 /* Do nothing on other platforms for now. |
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491 */ |
6134 | 492 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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493 gCpuCaps.hasSSE=0; |
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494 #endif /* __linux__ */ |
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495 } |
20577 | 496 #else /* ARCH_X86 */ |
3146
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497 |
9003 | 498 #ifdef SYS_DARWIN |
499 #include <sys/sysctl.h> | |
500 #else | |
17702
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add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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|
501 #ifndef __AMIGAOS4__ |
9003 | 502 #include <signal.h> |
503 #include <setjmp.h> | |
504 | |
505 static sigjmp_buf jmpbuf; | |
506 static volatile sig_atomic_t canjump = 0; | |
507 | |
508 static void sigill_handler (int sig) | |
509 { | |
510 if (!canjump) { | |
511 signal (sig, SIG_DFL); | |
512 raise (sig); | |
513 } | |
514 | |
515 canjump = 0; | |
516 siglongjmp (jmpbuf, 1); | |
517 } | |
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518 #endif //__AMIGAOS4__ |
9003 | 519 #endif |
520 | |
3146
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521 void GetCpuCaps( CpuCaps *caps) |
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522 { |
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523 caps->cpuType=0; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
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524 caps->cpuModel=0; |
3403 | 525 caps->cpuStepping=0; |
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526 caps->hasMMX=0; |
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527 caps->hasMMX2=0; |
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528 caps->has3DNow=0; |
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529 caps->has3DNowExt=0; |
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530 caps->hasSSE=0; |
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531 caps->hasSSE2=0; |
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532 caps->isX86=0; |
9003 | 533 caps->hasAltiVec = 0; |
534 #ifdef HAVE_ALTIVEC | |
535 #ifdef SYS_DARWIN | |
536 /* | |
537 rip-off from ffmpeg altivec detection code. | |
538 this code also appears on Apple's AltiVec pages. | |
539 */ | |
540 { | |
541 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
542 int has_vu = 0; | |
543 size_t len = sizeof(has_vu); | |
544 int err; | |
545 | |
546 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
547 | |
548 if (err == 0) | |
549 if (has_vu != 0) | |
550 caps->hasAltiVec = 1; | |
551 } | |
552 #else /* SYS_DARWIN */ | |
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553 #ifdef __AMIGAOS4__ |
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554 ULONG result = 0; |
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555 |
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556 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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557 if (result == VECTORTYPE_ALTIVEC) |
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558 caps->hasAltiVec = 1; |
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559 #else |
9003 | 560 /* no Darwin, do it the brute-force way */ |
561 /* this is borrowed from the libmpeg2 library */ | |
562 { | |
563 signal (SIGILL, sigill_handler); | |
564 if (sigsetjmp (jmpbuf, 1)) { | |
565 signal (SIGILL, SIG_DFL); | |
566 } else { | |
567 canjump = 1; | |
568 | |
569 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 570 "vand %%v0, %%v0, %%v0" |
9003 | 571 : |
572 : "r" (-1)); | |
573 | |
574 signal (SIGILL, SIG_DFL); | |
575 caps->hasAltiVec = 1; | |
576 } | |
577 } | |
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578 #endif //__AMIGAOS4__ |
9003 | 579 #endif /* SYS_DARWIN */ |
9324 | 580 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 581 #endif /* HAVE_ALTIVEC */ |
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582 |
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583 #ifdef ARCH_IA64 |
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584 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
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585 #endif |
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586 |
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587 #ifdef ARCH_SPARC |
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588 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
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589 #endif |
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590 |
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591 #ifdef ARCH_ARMV4L |
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592 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
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593 #endif |
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594 |
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595 #ifdef ARCH_POWERPC |
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596 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
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597 #endif |
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598 |
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599 #ifdef ARCH_ALPHA |
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600 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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601 #endif |
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602 |
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603 #ifdef ARCH_SGI_MIPS |
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604 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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605 #endif |
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606 |
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607 #ifdef ARCH_PA_RISC |
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608 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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609 #endif |
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610 |
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611 #ifdef ARCH_S390 |
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612 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
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613 #endif |
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614 |
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615 #ifdef ARCH_S390X |
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616 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
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617 #endif |
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618 |
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619 #ifdef ARCH_VAX |
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620 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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621 #endif |
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622 } |
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623 #endif /* !ARCH_X86 */ |