Mercurial > mplayer.hg
annotate cpudetect.c @ 30992:bf1afb0fa07d
Make ASS processing work with both subtitle formats, the MKV one and the
"standard" one FFmpeg uses.
author | reimar |
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date | Mon, 12 Apr 2010 21:04:17 +0000 |
parents | e97f3f59fb19 |
children | dd7f15a3fb1b |
rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
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19 #include "config.h" |
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20 #include "cpudetect.h" |
5937 | 21 #include "mp_msg.h" |
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22 |
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23 CpuCaps gCpuCaps; |
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24 |
3837 | 25 #include <stdlib.h> |
26 | |
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27 #if ARCH_X86 |
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28 |
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29 #include <stdio.h> |
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30 #include <string.h> |
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31 |
12143 | 32 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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33 #include <sys/param.h> |
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34 #include <sys/sysctl.h> |
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35 #include <machine/cpu.h> |
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36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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37 #include <sys/types.h> |
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38 #include <sys/sysctl.h> |
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39 #elif defined(__linux__) |
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40 #include <signal.h> |
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41 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 42 #include <windows.h> |
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43 #elif defined(__OS2__) |
26061 | 44 #define INCL_DOS |
45 #include <os2.h> | |
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46 #elif defined(__AMIGAOS4__) |
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47 #include <proto/exec.h> |
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48 #endif |
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49 |
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50 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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51 * help understanding how to use it. Thanks to the Mesa |
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52 * team for SSE support detection and more cpu detect code. |
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53 */ |
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54 |
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55 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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56 |
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57 static void check_os_katmai_support( void ); |
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58 |
2272 | 59 // return TRUE if cpuid supported |
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60 static int has_cpuid(void) |
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61 { |
2272 | 62 // code from libavcodec: |
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63 #if ARCH_X86_64 |
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64 return 1; |
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65 #else |
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66 long a, c; |
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67 __asm__ volatile ( |
2272 | 68 /* See if CPUID instruction is supported ... */ |
69 /* ... Get copies of EFLAGS into eax and ecx */ | |
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70 "pushfl\n\t" |
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71 "pop %0\n\t" |
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72 "mov %0, %1\n\t" |
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73 |
2272 | 74 /* ... Toggle the ID bit in one copy and store */ |
75 /* to the EFLAGS reg */ | |
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76 "xor $0x200000, %0\n\t" |
2272 | 77 "push %0\n\t" |
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78 "popfl\n\t" |
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79 |
2272 | 80 /* ... Get the (hopefully modified) EFLAGS */ |
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81 "pushfl\n\t" |
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82 "pop %0\n\t" |
2272 | 83 : "=a" (a), "=c" (c) |
84 : | |
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85 : "cc" |
2272 | 86 ); |
87 | |
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88 return a != c; |
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89 #endif |
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90 } |
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91 |
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92 static void |
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93 do_cpuid(unsigned int ax, unsigned int *p) |
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94 { |
2272 | 95 #if 0 |
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96 __asm__ volatile( |
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97 "cpuid;" |
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98 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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99 : "0" (ax) |
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100 ); |
2272 | 101 #else |
102 // code from libavcodec: | |
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103 __asm__ volatile |
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104 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 105 "cpuid\n\t" |
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106 "xchg %%"REG_b", %%"REG_S |
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107 : "=a" (p[0]), "=S" (p[1]), |
2272 | 108 "=c" (p[2]), "=d" (p[3]) |
109 : "0" (ax)); | |
110 #endif | |
111 | |
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112 } |
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113 |
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114 void GetCpuCaps( CpuCaps *caps) |
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115 { |
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116 unsigned int regs[4]; |
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117 unsigned int regs2[4]; |
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118 |
8860 | 119 memset(caps, 0, sizeof(*caps)); |
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120 caps->isX86=1; |
8860 | 121 caps->cl_size=32; /* default */ |
2288 | 122 if (!has_cpuid()) { |
6134 | 123 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 124 return; |
125 } | |
126 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 127 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 128 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 129 if (regs[0]>=0x00000001) |
2280 | 130 { |
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131 char *tmpstr, *ptmpstr; |
8860 | 132 unsigned cl_size; |
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133 |
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134 do_cpuid(0x00000001, regs2); |
2301 | 135 |
2288 | 136 caps->cpuType=(regs2[0] >> 8)&0xf; |
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137 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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138 |
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139 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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140 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 141 if(caps->cpuType==0xf){ |
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142 // use extended family (P4, IA64, K8) |
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143 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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144 } |
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145 if(caps->cpuType==0xf || caps->cpuType==6) |
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146 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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147 |
3403 | 148 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 149 |
150 // general feature flags: | |
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151 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 152 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
153 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
154 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
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155 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 |
28015 | 156 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 |
2288 | 157 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 158 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
159 if(cl_size) caps->cl_size = cl_size; | |
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160 |
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161 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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162 while(*ptmpstr == ' ') // strip leading spaces |
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163 ptmpstr++; |
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164 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); |
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165 free(tmpstr); |
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166 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", |
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167 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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168 |
2288 | 169 } |
170 do_cpuid(0x80000000, regs); | |
171 if (regs[0]>=0x80000001) { | |
6134 | 172 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 173 do_cpuid(0x80000001, regs2); |
3840 | 174 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
175 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 176 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
177 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
28015 | 178 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 |
2288 | 179 } |
8860 | 180 if(regs[0]>=0x80000006) |
181 { | |
182 do_cpuid(0x80000006, regs2); | |
183 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
184 caps->cl_size = regs2[2] & 0xFF; | |
185 } | |
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186 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 187 #if 0 |
5937 | 188 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 189 gCpuCaps.hasMMX, |
190 gCpuCaps.hasMMX2, | |
191 gCpuCaps.hasSSE, | |
192 gCpuCaps.hasSSE2, | |
193 gCpuCaps.has3DNow, | |
194 gCpuCaps.has3DNowExt ); | |
195 #endif | |
196 | |
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197 /* FIXME: Does SSE2 need more OS support, too? */ |
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198 if (caps->hasSSE) |
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199 check_os_katmai_support(); |
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200 if (!caps->hasSSE) |
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201 caps->hasSSE2 = 0; |
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202 // caps->has3DNow=1; |
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203 // caps->hasMMX2 = 0; |
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204 // caps->hasMMX = 0; |
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205 |
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206 #if !CONFIG_RUNTIME_CPUDETECT |
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207 #if !HAVE_MMX |
6134 | 208 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 209 caps->hasMMX=0; |
210 #endif | |
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211 #if !HAVE_MMX2 |
6134 | 212 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 213 caps->hasMMX2=0; |
214 #endif | |
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215 #if !HAVE_SSE |
6134 | 216 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 217 caps->hasSSE=0; |
218 #endif | |
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219 #if !HAVE_SSE2 |
6134 | 220 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 221 caps->hasSSE2=0; |
222 #endif | |
28335 | 223 #if !HAVE_AMD3DNOW |
6134 | 224 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 225 caps->has3DNow=0; |
226 #endif | |
28335 | 227 #if !HAVE_AMD3DNOWEXT |
6134 | 228 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 229 caps->has3DNowExt=0; |
230 #endif | |
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231 #endif // CONFIG_RUNTIME_CPUDETECT |
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232 } |
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233 |
2301 | 234 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
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235 char vendor[13]; |
2303 | 236 char *retname; |
13628 | 237 int i; |
2301 | 238 |
18869 | 239 if (NULL==(retname=malloc(256))) { |
5937 | 240 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 241 exit(1); |
242 } | |
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243 retname[0] = '\0'; |
2303 | 244 |
3837 | 245 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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246 |
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247 do_cpuid(0x80000000,regs); |
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248 if (regs[0] >= 0x80000004) |
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249 { |
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250 // CPU has built-in namestring |
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251 for (i = 0x80000002; i <= 0x80000004; i++) |
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252 { |
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253 do_cpuid(i, regs); |
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254 strncat(retname, (char*)regs, 16); |
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255 } |
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256 } |
2301 | 257 return retname; |
258 } | |
259 | |
28295 | 260 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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261 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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262 { |
6134 | 263 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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264 |
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265 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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266 * instructions are 3 bytes long. We must increment the instruction |
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267 * pointer manually to avoid repeated execution of the offending |
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268 * instruction. |
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269 * |
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270 * If the SIGILL is caused by a divide-by-zero when unmasked |
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271 * exceptions aren't supported, the SIMD FPU status and control |
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272 * word will be restored at the end of the test, so we don't need |
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273 * to worry about doing it here. Besides, we may not be able to... |
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274 */ |
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275 sc.eip += 3; |
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276 |
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277 gCpuCaps.hasSSE=0; |
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278 } |
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279 #endif /* __linux__ && _POSIX_SOURCE */ |
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280 |
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281 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
10440 | 282 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
283 { | |
284 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
285 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
286 ep->ContextRecord->Eip +=3; | |
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287 gCpuCaps.hasSSE=0; |
10440 | 288 return EXCEPTION_CONTINUE_EXECUTION; |
289 } | |
290 return EXCEPTION_CONTINUE_SEARCH; | |
291 } | |
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292 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 293 |
26061 | 294 #ifdef __OS2__ |
295 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
296 PEXCEPTIONREGISTRATIONRECORD p2, | |
297 PCONTEXTRECORD p3, | |
298 PVOID p4 ) | |
299 { | |
300 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
301 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
302 | |
303 p3->ctx_RegEip += 3; | |
304 gCpuCaps.hasSSE = 0; | |
305 | |
306 return XCPT_CONTINUE_EXECUTION; | |
307 } | |
308 return XCPT_CONTINUE_SEARCH; | |
309 } | |
310 #endif | |
311 | |
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312 /* If we're running on a processor that can do SSE, let's see if we |
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313 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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314 * haven't been configured for a Pentium III but are running on one, |
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315 * and RedHat patched 2.2 kernels that have broken exception handling |
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316 * support for user space apps that do SSE. |
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317 */ |
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318 |
21848 | 319 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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320 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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321 #elif defined(__APPLE__) |
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322 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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323 #endif |
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324 |
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325 static void check_os_katmai_support( void ) |
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326 { |
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327 #if ARCH_X86_64 |
14455 | 328 gCpuCaps.hasSSE=1; |
329 gCpuCaps.hasSSE2=1; | |
21848 | 330 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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331 int has_sse=0, ret; |
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332 size_t len=sizeof(has_sse); |
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333 |
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334 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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335 if (ret || !has_sse) |
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336 gCpuCaps.hasSSE=0; |
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337 |
12143 | 338 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
339 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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340 int has_sse, has_sse2, ret, mib[2]; |
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341 size_t varlen; |
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342 |
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343 mib[0] = CTL_MACHDEP; |
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344 mib[1] = CPU_SSE; |
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345 varlen = sizeof(has_sse); |
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346 |
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347 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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348 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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349 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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350 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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351 |
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352 mib[1] = CPU_SSE2; |
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353 varlen = sizeof(has_sse2); |
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354 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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355 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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356 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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357 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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358 #else |
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359 gCpuCaps.hasSSE = 0; |
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360 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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361 #endif |
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362 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 363 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
364 if ( gCpuCaps.hasSSE ) { | |
365 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
366 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
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367 __asm__ volatile ("xorps %xmm0, %xmm0"); |
10440 | 368 SetUnhandledExceptionFilter(exc_fil); |
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369 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
10440 | 370 } |
26061 | 371 #elif defined(__OS2__) |
372 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
373 if ( gCpuCaps.hasSSE ) { | |
374 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
375 DosSetExceptionHandler( &RegRec ); | |
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376 __asm__ volatile ("xorps %xmm0, %xmm0"); |
26061 | 377 DosUnsetExceptionHandler( &RegRec ); |
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378 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
26061 | 379 } |
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380 #elif defined(__linux__) |
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381 #if defined(_POSIX_SOURCE) |
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382 struct sigaction saved_sigill; |
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383 |
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384 /* Save the original signal handlers. |
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385 */ |
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386 sigaction( SIGILL, NULL, &saved_sigill ); |
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387 |
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388 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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389 |
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390 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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391 * supports the extended FPU save and restore required for SSE. If |
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392 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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393 * doesn't support Streaming SIMD Exceptions, even if the processor |
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394 * does. |
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395 */ |
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396 if ( gCpuCaps.hasSSE ) { |
6134 | 397 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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398 |
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399 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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400 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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401 |
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402 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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403 } |
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404 |
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405 /* Restore the original signal handlers. |
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406 */ |
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407 sigaction( SIGILL, &saved_sigill, NULL ); |
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408 |
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409 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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410 * safe to go ahead and hook out the SSE code throughout Mesa. |
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411 */ |
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412 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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413 #else |
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414 /* We can't use POSIX signal handling to test the availability of |
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415 * SSE, so we disable it by default. |
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416 */ |
5937 | 417 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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418 gCpuCaps.hasSSE=0; |
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419 #endif /* _POSIX_SOURCE */ |
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420 #else |
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421 /* Do nothing on other platforms for now. |
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422 */ |
6134 | 423 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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424 gCpuCaps.hasSSE=0; |
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425 #endif /* __linux__ */ |
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426 } |
20577 | 427 #else /* ARCH_X86 */ |
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428 |
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429 #ifdef __APPLE__ |
9003 | 430 #include <sys/sysctl.h> |
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431 #elif defined(__AMIGAOS4__) |
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432 /* nothing */ |
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433 #else |
9003 | 434 #include <signal.h> |
435 #include <setjmp.h> | |
436 | |
437 static sigjmp_buf jmpbuf; | |
438 static volatile sig_atomic_t canjump = 0; | |
439 | |
440 static void sigill_handler (int sig) | |
441 { | |
442 if (!canjump) { | |
443 signal (sig, SIG_DFL); | |
444 raise (sig); | |
445 } | |
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446 |
9003 | 447 canjump = 0; |
448 siglongjmp (jmpbuf, 1); | |
449 } | |
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450 #endif /* __APPLE__ */ |
9003 | 451 |
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452 void GetCpuCaps( CpuCaps *caps) |
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453 { |
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454 caps->cpuType=0; |
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455 caps->cpuModel=0; |
3403 | 456 caps->cpuStepping=0; |
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457 caps->hasMMX=0; |
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458 caps->hasMMX2=0; |
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459 caps->has3DNow=0; |
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460 caps->has3DNowExt=0; |
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461 caps->hasSSE=0; |
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462 caps->hasSSE2=0; |
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463 caps->hasSSE3=0; |
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464 caps->hasSSSE3=0; |
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465 caps->hasSSE4a=0; |
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466 caps->isX86=0; |
9003 | 467 caps->hasAltiVec = 0; |
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468 #if HAVE_ALTIVEC |
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469 #ifdef __APPLE__ |
9003 | 470 /* |
471 rip-off from ffmpeg altivec detection code. | |
472 this code also appears on Apple's AltiVec pages. | |
473 */ | |
474 { | |
475 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
476 int has_vu = 0; | |
477 size_t len = sizeof(has_vu); | |
478 int err; | |
479 | |
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480 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 481 |
482 if (err == 0) | |
483 if (has_vu != 0) | |
484 caps->hasAltiVec = 1; | |
485 } | |
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486 #elif defined(__AMIGAOS4__) |
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487 ULONG result = 0; |
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488 |
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489 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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490 if (result == VECTORTYPE_ALTIVEC) |
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491 caps->hasAltiVec = 1; |
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492 #else |
9003 | 493 /* no Darwin, do it the brute-force way */ |
494 /* this is borrowed from the libmpeg2 library */ | |
495 { | |
496 signal (SIGILL, sigill_handler); | |
497 if (sigsetjmp (jmpbuf, 1)) { | |
498 signal (SIGILL, SIG_DFL); | |
499 } else { | |
500 canjump = 1; | |
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501 |
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502 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 503 "vand %%v0, %%v0, %%v0" |
9003 | 504 : |
505 : "r" (-1)); | |
29263
0f1b5b68af32
whitespace cosmetics: Remove all trailing whitespace.
diego
parents:
29114
diff
changeset
|
506 |
9003 | 507 signal (SIGILL, SIG_DFL); |
508 caps->hasAltiVec = 1; | |
509 } | |
510 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
511 #endif /* __APPLE__ */ |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
512 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 513 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
514 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
515 if (ARCH_IA64) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
516 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
517 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
518 if (ARCH_SPARC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
519 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
520 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
521 if (ARCH_ARM) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
522 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
523 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
524 if (ARCH_PPC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
525 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
526 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
527 if (ARCH_ALPHA) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
528 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
529 |
30882 | 530 if (ARCH_MIPS) |
531 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
532 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
533 if (ARCH_PA_RISC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
534 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
535 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
536 if (ARCH_S390) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
537 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
538 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
539 if (ARCH_S390X) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
540 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
541 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
542 if (ARCH_VAX) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
543 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); |
25340 | 544 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
545 if (ARCH_XTENSA) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
546 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
547 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
548 #endif /* !ARCH_X86 */ |