Mercurial > mplayer.hg
annotate cpudetect.c @ 35369:dac86d3464e2
Also free the noauth_url entry in the URL struct.
author | reimar |
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date | Fri, 23 Nov 2012 19:26:01 +0000 |
parents | 3e1a4184b70e |
children | b4ce15212bfc |
rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
34198 | 19 #include "libavutil/x86_cpu.h" |
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20 #include "config.h" |
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21 #include "cpudetect.h" |
5937 | 22 #include "mp_msg.h" |
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23 |
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24 CpuCaps gCpuCaps; |
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25 |
3837 | 26 #include <stdlib.h> |
27 | |
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28 #if ARCH_X86 |
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29 |
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30 #include <stdio.h> |
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31 #include <string.h> |
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32 |
12143 | 33 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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34 #include <sys/param.h> |
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35 #include <sys/sysctl.h> |
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36 #include <machine/cpu.h> |
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37 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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38 #include <sys/types.h> |
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39 #include <sys/sysctl.h> |
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40 #elif defined(__linux__) |
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41 #include <signal.h> |
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42 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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44 #elif defined(__OS2__) |
26061 | 45 #define INCL_DOS |
46 #include <os2.h> | |
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47 #elif defined(__AMIGAOS4__) |
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48 #include <proto/exec.h> |
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49 #endif |
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50 |
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51 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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52 * help understanding how to use it. Thanks to the Mesa |
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53 * team for SSE support detection and more cpu detect code. |
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54 */ |
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55 |
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56 #if CONFIG_RUNTIME_CPUDETECT |
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57 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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58 |
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59 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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60 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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61 { |
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62 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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63 |
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64 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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65 * instructions are 3 bytes long. We must increment the instruction |
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66 * pointer manually to avoid repeated execution of the offending |
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67 * instruction. |
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68 * |
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69 * If the SIGILL is caused by a divide-by-zero when unmasked |
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70 * exceptions aren't supported, the SIMD FPU status and control |
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71 * word will be restored at the end of the test, so we don't need |
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72 * to worry about doing it here. Besides, we may not be able to... |
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73 */ |
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74 sc.eip += 3; |
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75 |
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76 gCpuCaps.hasSSE=0; |
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77 } |
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78 #endif /* __linux__ && _POSIX_SOURCE */ |
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79 |
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80 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
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81 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
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82 { |
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83 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ |
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84 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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85 ep->ContextRecord->Eip +=3; |
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86 gCpuCaps.hasSSE=0; |
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87 return EXCEPTION_CONTINUE_EXECUTION; |
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88 } |
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89 return EXCEPTION_CONTINUE_SEARCH; |
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90 } |
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91 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
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92 |
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93 #ifdef __OS2__ |
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94 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1, |
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95 PEXCEPTIONREGISTRATIONRECORD p2, |
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96 PCONTEXTRECORD p3, |
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97 PVOID p4) |
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98 { |
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99 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ |
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100 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); |
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101 |
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102 p3->ctx_RegEip += 3; |
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103 gCpuCaps.hasSSE = 0; |
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104 |
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105 return XCPT_CONTINUE_EXECUTION; |
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106 } |
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107 return XCPT_CONTINUE_SEARCH; |
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108 } |
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109 #endif |
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110 |
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111 /* If we're running on a processor that can do SSE, let's see if we |
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112 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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113 * haven't been configured for a Pentium III but are running on one, |
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114 * and RedHat patched 2.2 kernels that have broken exception handling |
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115 * support for user space apps that do SSE. |
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116 */ |
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117 |
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118 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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119 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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120 #elif defined(__APPLE__) |
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121 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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122 #endif |
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123 |
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124 static void check_os_katmai_support( void ) |
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125 { |
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126 #if ARCH_X86_64 |
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127 gCpuCaps.hasSSE=1; |
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128 gCpuCaps.hasSSE2=1; |
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129 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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130 int has_sse=0, ret; |
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131 size_t len=sizeof(has_sse); |
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132 |
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133 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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134 if (ret || !has_sse) |
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135 gCpuCaps.hasSSE=0; |
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136 |
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137 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
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138 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) |
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139 int has_sse, has_sse2, ret, mib[2]; |
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140 size_t varlen; |
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141 |
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142 mib[0] = CTL_MACHDEP; |
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143 mib[1] = CPU_SSE; |
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144 varlen = sizeof(has_sse); |
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145 |
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146 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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147 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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148 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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149 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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150 |
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151 mib[1] = CPU_SSE2; |
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152 varlen = sizeof(has_sse2); |
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153 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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154 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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155 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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156 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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157 #else |
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158 gCpuCaps.hasSSE = 0; |
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159 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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160 #endif |
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161 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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162 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
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163 if ( gCpuCaps.hasSSE ) { |
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164 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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165 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); |
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166 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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167 SetUnhandledExceptionFilter(exc_fil); |
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168 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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169 } |
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170 #elif defined(__OS2__) |
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171 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; |
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172 if ( gCpuCaps.hasSSE ) { |
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173 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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174 DosSetExceptionHandler( &RegRec ); |
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175 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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176 DosUnsetExceptionHandler( &RegRec ); |
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177 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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178 } |
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179 #elif defined(__linux__) |
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180 #if defined(_POSIX_SOURCE) |
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181 struct sigaction saved_sigill; |
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182 |
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183 /* Save the original signal handlers. |
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184 */ |
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185 sigaction( SIGILL, NULL, &saved_sigill ); |
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186 |
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187 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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188 |
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189 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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190 * supports the extended FPU save and restore required for SSE. If |
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191 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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192 * doesn't support Streaming SIMD Exceptions, even if the processor |
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193 * does. |
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194 */ |
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195 if ( gCpuCaps.hasSSE ) { |
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196 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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197 |
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198 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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199 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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200 |
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201 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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202 } |
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203 |
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204 /* Restore the original signal handlers. |
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205 */ |
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206 sigaction( SIGILL, &saved_sigill, NULL ); |
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207 |
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208 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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209 * safe to go ahead and hook out the SSE code throughout Mesa. |
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210 */ |
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211 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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212 #else |
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213 /* We can't use POSIX signal handling to test the availability of |
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214 * SSE, so we disable it by default. |
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215 */ |
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216 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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217 gCpuCaps.hasSSE=0; |
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218 #endif /* _POSIX_SOURCE */ |
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219 #else |
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220 /* Do nothing on other platforms for now. |
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221 */ |
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222 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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223 gCpuCaps.hasSSE=0; |
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224 #endif /* __linux__ */ |
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225 } |
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226 #endif |
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227 |
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228 |
2272 | 229 // return TRUE if cpuid supported |
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230 static int has_cpuid(void) |
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231 { |
2272 | 232 // code from libavcodec: |
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233 #if ARCH_X86_64 |
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234 return 1; |
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235 #else |
31077 | 236 long a, c; |
237 __asm__ volatile ( | |
238 /* See if CPUID instruction is supported ... */ | |
239 /* ... Get copies of EFLAGS into eax and ecx */ | |
240 "pushfl\n\t" | |
241 "pop %0\n\t" | |
242 "mov %0, %1\n\t" | |
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243 |
31077 | 244 /* ... Toggle the ID bit in one copy and store */ |
245 /* to the EFLAGS reg */ | |
246 "xor $0x200000, %0\n\t" | |
247 "push %0\n\t" | |
248 "popfl\n\t" | |
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249 |
31077 | 250 /* ... Get the (hopefully modified) EFLAGS */ |
251 "pushfl\n\t" | |
252 "pop %0\n\t" | |
253 : "=a" (a), "=c" (c) | |
254 : | |
255 : "cc" | |
256 ); | |
2272 | 257 |
31077 | 258 return a != c; |
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259 #endif |
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260 } |
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261 |
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262 void |
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263 do_cpuid(unsigned int ax, unsigned int *p) |
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264 { |
2272 | 265 // code from libavcodec: |
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266 __asm__ volatile |
31077 | 267 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 268 "cpuid\n\t" |
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269 "xchg %%"REG_b", %%"REG_S |
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270 : "=a" (p[0]), "=S" (p[1]), |
2272 | 271 "=c" (p[2]), "=d" (p[3]) |
272 : "0" (ax)); | |
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273 } |
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274 |
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275 void GetCpuCaps( CpuCaps *caps) |
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276 { |
31077 | 277 unsigned int regs[4]; |
278 unsigned int regs2[4]; | |
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279 |
31077 | 280 memset(caps, 0, sizeof(*caps)); |
281 caps->isX86=1; | |
282 caps->cl_size=32; /* default */ | |
283 if (!has_cpuid()) { | |
284 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); | |
285 return; | |
286 } | |
287 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
288 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", | |
289 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
290 if (regs[0]>=0x00000001) | |
291 { | |
292 char *tmpstr, *ptmpstr; | |
293 unsigned cl_size; | |
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294 |
31077 | 295 do_cpuid(0x00000001, regs2); |
2301 | 296 |
31077 | 297 caps->cpuType=(regs2[0] >> 8)&0xf; |
298 caps->cpuModel=(regs2[0] >> 4)&0xf; | |
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299 |
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300 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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301 // System Instructions, Table 3-2: Effective family computation, page 120. |
31077 | 302 if(caps->cpuType==0xf){ |
303 // use extended family (P4, IA64, K8) | |
304 caps->cpuType=0xf+((regs2[0]>>20)&255); | |
305 } | |
306 if(caps->cpuType==0xf || caps->cpuType==6) | |
307 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; | |
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308 |
31077 | 309 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 310 |
31077 | 311 // general feature flags: |
312 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 | |
313 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
314 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
315 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
316 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 | |
317 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 | |
35101 | 318 caps->hasSSE4 = (regs2[2] & (1 << 19 )) >> 19; // 0x0080000 |
319 caps->hasSSE42 = (regs2[2] & (1 << 20)) >> 20; // 0x0100000 | |
320 caps->hasAVX = (regs2[2] & (1 << 28 )) >> 28; // 0x10000000 | |
31077 | 321 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
322 cl_size = ((regs2[1] >> 8) & 0xFF)*8; | |
323 if(cl_size) caps->cl_size = cl_size; | |
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324 |
31077 | 325 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
326 while(*ptmpstr == ' ') // strip leading spaces | |
327 ptmpstr++; | |
328 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); | |
329 free(tmpstr); | |
330 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", | |
331 caps->cpuType, caps->cpuModel, caps->cpuStepping); | |
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332 |
31077 | 333 } |
334 do_cpuid(0x80000000, regs); | |
335 if (regs[0]>=0x80000001) { | |
336 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
337 do_cpuid(0x80000001, regs2); | |
338 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
339 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
340 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 | |
341 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
342 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 | |
343 } | |
344 if(regs[0]>=0x80000006) | |
345 { | |
346 do_cpuid(0x80000006, regs2); | |
347 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
348 caps->cl_size = regs2[2] & 0xFF; | |
349 } | |
350 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 351 #if 0 |
31077 | 352 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
353 gCpuCaps.hasMMX, | |
354 gCpuCaps.hasMMX2, | |
355 gCpuCaps.hasSSE, | |
356 gCpuCaps.hasSSE2, | |
357 gCpuCaps.has3DNow, | |
358 gCpuCaps.has3DNowExt); | |
2288 | 359 #endif |
360 | |
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361 #if CONFIG_RUNTIME_CPUDETECT |
31077 | 362 /* FIXME: Does SSE2 need more OS support, too? */ |
363 if (caps->hasSSE) | |
364 check_os_katmai_support(); | |
365 if (!caps->hasSSE) | |
366 caps->hasSSE2 = 0; | |
367 // caps->has3DNow=1; | |
368 // caps->hasMMX2 = 0; | |
369 // caps->hasMMX = 0; | |
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370 |
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371 #else |
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372 #if !HAVE_MMX |
31077 | 373 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
374 caps->hasMMX=0; | |
4829 | 375 #endif |
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376 #if !HAVE_MMX2 |
31077 | 377 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
378 caps->hasMMX2=0; | |
4829 | 379 #endif |
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380 #if !HAVE_SSE |
31077 | 381 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
382 caps->hasSSE=0; | |
4829 | 383 #endif |
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384 #if !HAVE_SSE2 |
31077 | 385 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
386 caps->hasSSE2=0; | |
4829 | 387 #endif |
28335 | 388 #if !HAVE_AMD3DNOW |
31077 | 389 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
390 caps->has3DNow=0; | |
4829 | 391 #endif |
28335 | 392 #if !HAVE_AMD3DNOWEXT |
31077 | 393 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
394 caps->has3DNowExt=0; | |
4829 | 395 #endif |
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396 #endif // CONFIG_RUNTIME_CPUDETECT |
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397 } |
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398 |
2301 | 399 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
31077 | 400 char vendor[13]; |
401 char *retname; | |
402 int i; | |
2301 | 403 |
31077 | 404 if (NULL==(retname=malloc(256))) { |
405 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); | |
406 exit(1); | |
407 } | |
408 retname[0] = '\0'; | |
2303 | 409 |
31077 | 410 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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411 |
31077 | 412 do_cpuid(0x80000000,regs); |
413 if (regs[0] >= 0x80000004) | |
414 { | |
415 // CPU has built-in namestring | |
416 for (i = 0x80000002; i <= 0x80000004; i++) | |
417 { | |
418 do_cpuid(i, regs); | |
419 strncat(retname, (char*)regs, 16); | |
420 } | |
421 } | |
422 return retname; | |
2301 | 423 } |
424 | |
20577 | 425 #else /* ARCH_X86 */ |
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426 |
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427 #ifdef __APPLE__ |
9003 | 428 #include <sys/sysctl.h> |
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429 #elif defined(__AMIGAOS4__) |
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430 /* nothing */ |
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431 #else |
9003 | 432 #include <signal.h> |
433 #include <setjmp.h> | |
434 | |
435 static sigjmp_buf jmpbuf; | |
436 static volatile sig_atomic_t canjump = 0; | |
437 | |
438 static void sigill_handler (int sig) | |
439 { | |
440 if (!canjump) { | |
441 signal (sig, SIG_DFL); | |
442 raise (sig); | |
443 } | |
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444 |
9003 | 445 canjump = 0; |
446 siglongjmp (jmpbuf, 1); | |
447 } | |
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448 #endif /* __APPLE__ */ |
9003 | 449 |
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450 void GetCpuCaps( CpuCaps *caps) |
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451 { |
31077 | 452 caps->cpuType=0; |
453 caps->cpuModel=0; | |
454 caps->cpuStepping=0; | |
455 caps->hasMMX=0; | |
456 caps->hasMMX2=0; | |
457 caps->has3DNow=0; | |
458 caps->has3DNowExt=0; | |
459 caps->hasSSE=0; | |
460 caps->hasSSE2=0; | |
461 caps->hasSSE3=0; | |
462 caps->hasSSSE3=0; | |
35101 | 463 caps->hasSSE4=0; |
464 caps->hasSSE42=0; | |
31077 | 465 caps->hasSSE4a=0; |
35101 | 466 caps->hasAVX=0; |
31077 | 467 caps->isX86=0; |
468 caps->hasAltiVec = 0; | |
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469 #if HAVE_ALTIVEC |
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470 #ifdef __APPLE__ |
9003 | 471 /* |
472 rip-off from ffmpeg altivec detection code. | |
473 this code also appears on Apple's AltiVec pages. | |
474 */ | |
31077 | 475 { |
476 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
477 int has_vu = 0; | |
478 size_t len = sizeof(has_vu); | |
479 int err; | |
9003 | 480 |
31077 | 481 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 482 |
31077 | 483 if (err == 0) |
484 if (has_vu != 0) | |
485 caps->hasAltiVec = 1; | |
486 } | |
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487 #elif defined(__AMIGAOS4__) |
31077 | 488 ULONG result = 0; |
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489 |
31077 | 490 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
491 if (result == VECTORTYPE_ALTIVEC) | |
492 caps->hasAltiVec = 1; | |
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493 #else |
9003 | 494 /* no Darwin, do it the brute-force way */ |
495 /* this is borrowed from the libmpeg2 library */ | |
31077 | 496 { |
497 signal (SIGILL, sigill_handler); | |
498 if (sigsetjmp (jmpbuf, 1)) { | |
9003 | 499 signal (SIGILL, SIG_DFL); |
31077 | 500 } else { |
9003 | 501 canjump = 1; |
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502 |
31077 | 503 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 504 "vand %%v0, %%v0, %%v0" |
9003 | 505 : |
506 : "r" (-1)); | |
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507 |
31077 | 508 signal (SIGILL, SIG_DFL); |
509 caps->hasAltiVec = 1; | |
9003 | 510 } |
31077 | 511 } |
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512 #endif /* __APPLE__ */ |
31077 | 513 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 514 #endif /* HAVE_ALTIVEC */ |
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515 |
31077 | 516 if (ARCH_IA64) |
517 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); | |
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518 |
31077 | 519 if (ARCH_SPARC) |
520 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); | |
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521 |
31077 | 522 if (ARCH_ARM) |
523 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); | |
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524 |
31077 | 525 if (ARCH_PPC) |
526 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); | |
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527 |
31077 | 528 if (ARCH_ALPHA) |
529 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); | |
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530 |
31077 | 531 if (ARCH_MIPS) |
532 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
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533 |
31077 | 534 if (ARCH_PA_RISC) |
535 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); | |
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536 |
31077 | 537 if (ARCH_S390) |
538 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); | |
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539 |
31077 | 540 if (ARCH_S390X) |
541 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); | |
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542 |
31077 | 543 if (ARCH_VAX) |
544 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); | |
25340 | 545 |
31077 | 546 if (ARCH_XTENSA) |
547 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); | |
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548 } |
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549 #endif /* !ARCH_X86 */ |