Mercurial > mplayer.hg
annotate cpudetect.c @ 33672:e576232a39d5
Prevent balance from hopping.
Only recalculate the balance if the balance has changed, not if just
the volume has changed.
Because (at least with my soundcard) not all volume values can be
stored, but seem to be mapped onto a discrete value set, recalculation
the balance from the volume isn't accurate enough.
author | ib |
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date | Tue, 28 Jun 2011 18:16:06 +0000 |
parents | 5e3f013bf4c2 |
children | 064be070d8c8 |
rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
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19 #include "config.h" |
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20 #include "cpudetect.h" |
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22 |
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23 CpuCaps gCpuCaps; |
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24 |
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26 | |
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27 #if ARCH_X86 |
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28 |
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29 #include <stdio.h> |
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30 #include <string.h> |
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31 |
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33 #include <sys/param.h> |
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34 #include <sys/sysctl.h> |
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35 #include <machine/cpu.h> |
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36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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37 #include <sys/types.h> |
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38 #include <sys/sysctl.h> |
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39 #elif defined(__linux__) |
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40 #include <signal.h> |
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41 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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43 #elif defined(__OS2__) |
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45 #include <os2.h> | |
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46 #elif defined(__AMIGAOS4__) |
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47 #include <proto/exec.h> |
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48 #endif |
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49 |
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50 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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51 * help understanding how to use it. Thanks to the Mesa |
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52 * team for SSE support detection and more cpu detect code. |
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53 */ |
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54 |
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55 #if CONFIG_RUNTIME_CPUDETECT |
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56 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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57 |
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58 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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59 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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60 { |
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61 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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62 |
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63 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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64 * instructions are 3 bytes long. We must increment the instruction |
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65 * pointer manually to avoid repeated execution of the offending |
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66 * instruction. |
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67 * |
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68 * If the SIGILL is caused by a divide-by-zero when unmasked |
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69 * exceptions aren't supported, the SIMD FPU status and control |
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70 * word will be restored at the end of the test, so we don't need |
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71 * to worry about doing it here. Besides, we may not be able to... |
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72 */ |
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73 sc.eip += 3; |
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74 |
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75 gCpuCaps.hasSSE=0; |
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76 } |
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77 #endif /* __linux__ && _POSIX_SOURCE */ |
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78 |
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79 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
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80 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
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81 { |
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82 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ |
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83 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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84 ep->ContextRecord->Eip +=3; |
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85 gCpuCaps.hasSSE=0; |
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86 return EXCEPTION_CONTINUE_EXECUTION; |
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87 } |
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88 return EXCEPTION_CONTINUE_SEARCH; |
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89 } |
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90 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
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91 |
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92 #ifdef __OS2__ |
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93 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1, |
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94 PEXCEPTIONREGISTRATIONRECORD p2, |
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95 PCONTEXTRECORD p3, |
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96 PVOID p4) |
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97 { |
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98 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ |
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99 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); |
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100 |
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101 p3->ctx_RegEip += 3; |
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102 gCpuCaps.hasSSE = 0; |
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103 |
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104 return XCPT_CONTINUE_EXECUTION; |
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105 } |
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106 return XCPT_CONTINUE_SEARCH; |
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107 } |
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108 #endif |
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109 |
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110 /* If we're running on a processor that can do SSE, let's see if we |
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111 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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112 * haven't been configured for a Pentium III but are running on one, |
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113 * and RedHat patched 2.2 kernels that have broken exception handling |
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114 * support for user space apps that do SSE. |
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115 */ |
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116 |
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117 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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118 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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119 #elif defined(__APPLE__) |
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120 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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121 #endif |
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122 |
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123 static void check_os_katmai_support( void ) |
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124 { |
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125 #if ARCH_X86_64 |
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126 gCpuCaps.hasSSE=1; |
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127 gCpuCaps.hasSSE2=1; |
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128 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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129 int has_sse=0, ret; |
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130 size_t len=sizeof(has_sse); |
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131 |
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132 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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133 if (ret || !has_sse) |
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134 gCpuCaps.hasSSE=0; |
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135 |
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136 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
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137 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) |
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138 int has_sse, has_sse2, ret, mib[2]; |
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139 size_t varlen; |
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140 |
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141 mib[0] = CTL_MACHDEP; |
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142 mib[1] = CPU_SSE; |
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143 varlen = sizeof(has_sse); |
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144 |
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145 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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146 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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147 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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148 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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149 |
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150 mib[1] = CPU_SSE2; |
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151 varlen = sizeof(has_sse2); |
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152 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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153 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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154 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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155 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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156 #else |
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157 gCpuCaps.hasSSE = 0; |
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158 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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159 #endif |
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160 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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161 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
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162 if ( gCpuCaps.hasSSE ) { |
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163 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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164 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); |
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165 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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166 SetUnhandledExceptionFilter(exc_fil); |
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167 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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168 } |
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169 #elif defined(__OS2__) |
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170 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; |
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171 if ( gCpuCaps.hasSSE ) { |
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172 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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173 DosSetExceptionHandler( &RegRec ); |
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174 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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175 DosUnsetExceptionHandler( &RegRec ); |
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176 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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177 } |
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178 #elif defined(__linux__) |
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179 #if defined(_POSIX_SOURCE) |
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180 struct sigaction saved_sigill; |
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181 |
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182 /* Save the original signal handlers. |
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183 */ |
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184 sigaction( SIGILL, NULL, &saved_sigill ); |
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185 |
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186 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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187 |
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188 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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189 * supports the extended FPU save and restore required for SSE. If |
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190 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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191 * doesn't support Streaming SIMD Exceptions, even if the processor |
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192 * does. |
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193 */ |
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194 if ( gCpuCaps.hasSSE ) { |
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195 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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196 |
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197 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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198 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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199 |
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200 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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201 } |
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202 |
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203 /* Restore the original signal handlers. |
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204 */ |
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205 sigaction( SIGILL, &saved_sigill, NULL ); |
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206 |
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207 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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208 * safe to go ahead and hook out the SSE code throughout Mesa. |
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209 */ |
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210 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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211 #else |
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212 /* We can't use POSIX signal handling to test the availability of |
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213 * SSE, so we disable it by default. |
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214 */ |
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215 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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216 gCpuCaps.hasSSE=0; |
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217 #endif /* _POSIX_SOURCE */ |
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218 #else |
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219 /* Do nothing on other platforms for now. |
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220 */ |
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221 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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222 gCpuCaps.hasSSE=0; |
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223 #endif /* __linux__ */ |
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224 } |
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225 #endif |
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226 |
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227 |
2272 | 228 // return TRUE if cpuid supported |
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229 static int has_cpuid(void) |
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230 { |
2272 | 231 // code from libavcodec: |
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232 #if ARCH_X86_64 |
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233 return 1; |
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234 #else |
31077 | 235 long a, c; |
236 __asm__ volatile ( | |
237 /* See if CPUID instruction is supported ... */ | |
238 /* ... Get copies of EFLAGS into eax and ecx */ | |
239 "pushfl\n\t" | |
240 "pop %0\n\t" | |
241 "mov %0, %1\n\t" | |
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242 |
31077 | 243 /* ... Toggle the ID bit in one copy and store */ |
244 /* to the EFLAGS reg */ | |
245 "xor $0x200000, %0\n\t" | |
246 "push %0\n\t" | |
247 "popfl\n\t" | |
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248 |
31077 | 249 /* ... Get the (hopefully modified) EFLAGS */ |
250 "pushfl\n\t" | |
251 "pop %0\n\t" | |
252 : "=a" (a), "=c" (c) | |
253 : | |
254 : "cc" | |
255 ); | |
2272 | 256 |
31077 | 257 return a != c; |
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258 #endif |
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259 } |
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260 |
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261 void |
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262 do_cpuid(unsigned int ax, unsigned int *p) |
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263 { |
2272 | 264 // code from libavcodec: |
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265 __asm__ volatile |
31077 | 266 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 267 "cpuid\n\t" |
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268 "xchg %%"REG_b", %%"REG_S |
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269 : "=a" (p[0]), "=S" (p[1]), |
2272 | 270 "=c" (p[2]), "=d" (p[3]) |
271 : "0" (ax)); | |
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272 } |
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273 |
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274 void GetCpuCaps( CpuCaps *caps) |
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275 { |
31077 | 276 unsigned int regs[4]; |
277 unsigned int regs2[4]; | |
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278 |
31077 | 279 memset(caps, 0, sizeof(*caps)); |
280 caps->isX86=1; | |
281 caps->cl_size=32; /* default */ | |
282 if (!has_cpuid()) { | |
283 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); | |
284 return; | |
285 } | |
286 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
287 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", | |
288 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
289 if (regs[0]>=0x00000001) | |
290 { | |
291 char *tmpstr, *ptmpstr; | |
292 unsigned cl_size; | |
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293 |
31077 | 294 do_cpuid(0x00000001, regs2); |
2301 | 295 |
31077 | 296 caps->cpuType=(regs2[0] >> 8)&0xf; |
297 caps->cpuModel=(regs2[0] >> 4)&0xf; | |
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298 |
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299 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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300 // System Instructions, Table 3-2: Effective family computation, page 120. |
31077 | 301 if(caps->cpuType==0xf){ |
302 // use extended family (P4, IA64, K8) | |
303 caps->cpuType=0xf+((regs2[0]>>20)&255); | |
304 } | |
305 if(caps->cpuType==0xf || caps->cpuType==6) | |
306 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; | |
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307 |
31077 | 308 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 309 |
31077 | 310 // general feature flags: |
311 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 | |
312 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
313 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
314 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
315 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 | |
316 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 | |
317 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too | |
318 cl_size = ((regs2[1] >> 8) & 0xFF)*8; | |
319 if(cl_size) caps->cl_size = cl_size; | |
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320 |
31077 | 321 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
322 while(*ptmpstr == ' ') // strip leading spaces | |
323 ptmpstr++; | |
324 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); | |
325 free(tmpstr); | |
326 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", | |
327 caps->cpuType, caps->cpuModel, caps->cpuStepping); | |
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328 |
31077 | 329 } |
330 do_cpuid(0x80000000, regs); | |
331 if (regs[0]>=0x80000001) { | |
332 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
333 do_cpuid(0x80000001, regs2); | |
334 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
335 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
336 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 | |
337 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
338 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 | |
339 } | |
340 if(regs[0]>=0x80000006) | |
341 { | |
342 do_cpuid(0x80000006, regs2); | |
343 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
344 caps->cl_size = regs2[2] & 0xFF; | |
345 } | |
346 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 347 #if 0 |
31077 | 348 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
349 gCpuCaps.hasMMX, | |
350 gCpuCaps.hasMMX2, | |
351 gCpuCaps.hasSSE, | |
352 gCpuCaps.hasSSE2, | |
353 gCpuCaps.has3DNow, | |
354 gCpuCaps.has3DNowExt); | |
2288 | 355 #endif |
356 | |
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357 #if CONFIG_RUNTIME_CPUDETECT |
31077 | 358 /* FIXME: Does SSE2 need more OS support, too? */ |
359 if (caps->hasSSE) | |
360 check_os_katmai_support(); | |
361 if (!caps->hasSSE) | |
362 caps->hasSSE2 = 0; | |
363 // caps->has3DNow=1; | |
364 // caps->hasMMX2 = 0; | |
365 // caps->hasMMX = 0; | |
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366 |
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367 #else |
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368 #if !HAVE_MMX |
31077 | 369 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
370 caps->hasMMX=0; | |
4829 | 371 #endif |
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372 #if !HAVE_MMX2 |
31077 | 373 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
374 caps->hasMMX2=0; | |
4829 | 375 #endif |
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376 #if !HAVE_SSE |
31077 | 377 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
378 caps->hasSSE=0; | |
4829 | 379 #endif |
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380 #if !HAVE_SSE2 |
31077 | 381 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
382 caps->hasSSE2=0; | |
4829 | 383 #endif |
28335 | 384 #if !HAVE_AMD3DNOW |
31077 | 385 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
386 caps->has3DNow=0; | |
4829 | 387 #endif |
28335 | 388 #if !HAVE_AMD3DNOWEXT |
31077 | 389 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
390 caps->has3DNowExt=0; | |
4829 | 391 #endif |
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392 #endif // CONFIG_RUNTIME_CPUDETECT |
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393 } |
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394 |
2301 | 395 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
31077 | 396 char vendor[13]; |
397 char *retname; | |
398 int i; | |
2301 | 399 |
31077 | 400 if (NULL==(retname=malloc(256))) { |
401 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); | |
402 exit(1); | |
403 } | |
404 retname[0] = '\0'; | |
2303 | 405 |
31077 | 406 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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407 |
31077 | 408 do_cpuid(0x80000000,regs); |
409 if (regs[0] >= 0x80000004) | |
410 { | |
411 // CPU has built-in namestring | |
412 for (i = 0x80000002; i <= 0x80000004; i++) | |
413 { | |
414 do_cpuid(i, regs); | |
415 strncat(retname, (char*)regs, 16); | |
416 } | |
417 } | |
418 return retname; | |
2301 | 419 } |
420 | |
20577 | 421 #else /* ARCH_X86 */ |
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422 |
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423 #ifdef __APPLE__ |
9003 | 424 #include <sys/sysctl.h> |
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425 #elif defined(__AMIGAOS4__) |
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426 /* nothing */ |
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427 #else |
9003 | 428 #include <signal.h> |
429 #include <setjmp.h> | |
430 | |
431 static sigjmp_buf jmpbuf; | |
432 static volatile sig_atomic_t canjump = 0; | |
433 | |
434 static void sigill_handler (int sig) | |
435 { | |
436 if (!canjump) { | |
437 signal (sig, SIG_DFL); | |
438 raise (sig); | |
439 } | |
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440 |
9003 | 441 canjump = 0; |
442 siglongjmp (jmpbuf, 1); | |
443 } | |
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444 #endif /* __APPLE__ */ |
9003 | 445 |
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446 void GetCpuCaps( CpuCaps *caps) |
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447 { |
31077 | 448 caps->cpuType=0; |
449 caps->cpuModel=0; | |
450 caps->cpuStepping=0; | |
451 caps->hasMMX=0; | |
452 caps->hasMMX2=0; | |
453 caps->has3DNow=0; | |
454 caps->has3DNowExt=0; | |
455 caps->hasSSE=0; | |
456 caps->hasSSE2=0; | |
457 caps->hasSSE3=0; | |
458 caps->hasSSSE3=0; | |
459 caps->hasSSE4a=0; | |
460 caps->isX86=0; | |
461 caps->hasAltiVec = 0; | |
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462 #if HAVE_ALTIVEC |
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463 #ifdef __APPLE__ |
9003 | 464 /* |
465 rip-off from ffmpeg altivec detection code. | |
466 this code also appears on Apple's AltiVec pages. | |
467 */ | |
31077 | 468 { |
469 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
470 int has_vu = 0; | |
471 size_t len = sizeof(has_vu); | |
472 int err; | |
9003 | 473 |
31077 | 474 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 475 |
31077 | 476 if (err == 0) |
477 if (has_vu != 0) | |
478 caps->hasAltiVec = 1; | |
479 } | |
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480 #elif defined(__AMIGAOS4__) |
31077 | 481 ULONG result = 0; |
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482 |
31077 | 483 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
484 if (result == VECTORTYPE_ALTIVEC) | |
485 caps->hasAltiVec = 1; | |
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486 #else |
9003 | 487 /* no Darwin, do it the brute-force way */ |
488 /* this is borrowed from the libmpeg2 library */ | |
31077 | 489 { |
490 signal (SIGILL, sigill_handler); | |
491 if (sigsetjmp (jmpbuf, 1)) { | |
9003 | 492 signal (SIGILL, SIG_DFL); |
31077 | 493 } else { |
9003 | 494 canjump = 1; |
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495 |
31077 | 496 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 497 "vand %%v0, %%v0, %%v0" |
9003 | 498 : |
499 : "r" (-1)); | |
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500 |
31077 | 501 signal (SIGILL, SIG_DFL); |
502 caps->hasAltiVec = 1; | |
9003 | 503 } |
31077 | 504 } |
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505 #endif /* __APPLE__ */ |
31077 | 506 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 507 #endif /* HAVE_ALTIVEC */ |
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508 |
31077 | 509 if (ARCH_IA64) |
510 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); | |
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511 |
31077 | 512 if (ARCH_SPARC) |
513 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); | |
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514 |
31077 | 515 if (ARCH_ARM) |
516 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); | |
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517 |
31077 | 518 if (ARCH_PPC) |
519 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); | |
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520 |
31077 | 521 if (ARCH_ALPHA) |
522 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); | |
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523 |
31077 | 524 if (ARCH_MIPS) |
525 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
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526 |
31077 | 527 if (ARCH_PA_RISC) |
528 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); | |
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529 |
31077 | 530 if (ARCH_S390) |
531 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); | |
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532 |
31077 | 533 if (ARCH_S390X) |
534 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); | |
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535 |
31077 | 536 if (ARCH_VAX) |
537 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); | |
25340 | 538 |
31077 | 539 if (ARCH_XTENSA) |
540 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); | |
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541 } |
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542 #endif /* !ARCH_X86 */ |