Mercurial > mplayer.hg
annotate cpudetect.c @ 18410:f07c9898029f
typo/wording fixes
author | diego |
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date | Tue, 09 May 2006 14:07:26 +0000 |
parents | 485f04e5a58c |
children | 739849dfb699 |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #if defined(ARCH_X86) || defined(ARCH_X86_64) |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
15566 | 23 #if defined(__FreeBSD__) || defined(__DragonFly__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
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36 #ifdef __AMIGAOS4__ |
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37 #include <proto/exec.h> |
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38 #endif |
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39 |
2272 | 40 //#define X86_FXSR_MAGIC |
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41 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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42 * help understanding how to use it. Thanks to the Mesa |
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43 * team for SSE support detection and more cpu detect code. |
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44 */ |
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45 |
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46 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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47 |
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48 static void check_os_katmai_support( void ); |
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49 |
2272 | 50 #if 1 |
51 // return TRUE if cpuid supported | |
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52 static int has_cpuid(void) |
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53 { |
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54 long a, c; |
2272 | 55 |
56 // code from libavcodec: | |
57 __asm__ __volatile__ ( | |
58 /* See if CPUID instruction is supported ... */ | |
59 /* ... Get copies of EFLAGS into eax and ecx */ | |
60 "pushf\n\t" | |
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61 "pop %0\n\t" |
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62 "mov %0, %1\n\t" |
2272 | 63 |
64 /* ... Toggle the ID bit in one copy and store */ | |
65 /* to the EFLAGS reg */ | |
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66 "xor $0x200000, %0\n\t" |
2272 | 67 "push %0\n\t" |
68 "popf\n\t" | |
69 | |
70 /* ... Get the (hopefully modified) EFLAGS */ | |
71 "pushf\n\t" | |
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72 "pop %0\n\t" |
2272 | 73 : "=a" (a), "=c" (c) |
74 : | |
75 : "cc" | |
76 ); | |
77 | |
78 return (a!=c); | |
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79 } |
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80 #endif |
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81 |
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82 static void |
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83 do_cpuid(unsigned int ax, unsigned int *p) |
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84 { |
2272 | 85 #if 0 |
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86 __asm __volatile( |
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87 "cpuid;" |
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88 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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89 : "0" (ax) |
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90 ); |
2272 | 91 #else |
92 // code from libavcodec: | |
93 __asm __volatile | |
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94 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 95 "cpuid\n\t" |
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96 "xchg %%"REG_b", %%"REG_S |
3403 | 97 : "=a" (p[0]), "=S" (p[1]), |
2272 | 98 "=c" (p[2]), "=d" (p[3]) |
99 : "0" (ax)); | |
100 #endif | |
101 | |
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102 } |
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103 |
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104 void GetCpuCaps( CpuCaps *caps) |
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105 { |
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106 unsigned int regs[4]; |
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107 unsigned int regs2[4]; |
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108 |
8860 | 109 memset(caps, 0, sizeof(*caps)); |
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110 caps->isX86=1; |
8860 | 111 caps->cl_size=32; /* default */ |
2288 | 112 if (!has_cpuid()) { |
6134 | 113 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 114 return; |
115 } | |
116 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 117 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 118 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 119 if (regs[0]>=0x00000001) |
2280 | 120 { |
2303 | 121 char *tmpstr; |
8860 | 122 unsigned cl_size; |
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123 |
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124 do_cpuid(0x00000001, regs2); |
2301 | 125 |
2288 | 126 caps->cpuType=(regs2[0] >> 8)&0xf; |
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127 |
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128 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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129 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 130 if(caps->cpuType==0xf){ |
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131 // use extended family (P4, IA64, K8) |
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132 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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133 } |
3403 | 134 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 135 |
136 // general feature flags: | |
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137 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 138 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
139 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
140 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 141 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 142 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
143 if(cl_size) caps->cl_size = cl_size; | |
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144 |
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145 tmpstr=GetCpuFriendlyName(regs, regs2); |
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146 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
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147 free(tmpstr); |
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148 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
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149 caps->cpuType, caps->cpuStepping); |
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150 |
2288 | 151 } |
152 do_cpuid(0x80000000, regs); | |
153 if (regs[0]>=0x80000001) { | |
6134 | 154 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 155 do_cpuid(0x80000001, regs2); |
3840 | 156 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
157 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 158 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
159 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
160 } | |
8860 | 161 if(regs[0]>=0x80000006) |
162 { | |
163 do_cpuid(0x80000006, regs2); | |
164 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
165 caps->cl_size = regs2[2] & 0xFF; | |
166 } | |
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167 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 168 #if 0 |
5937 | 169 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 170 gCpuCaps.hasMMX, |
171 gCpuCaps.hasMMX2, | |
172 gCpuCaps.hasSSE, | |
173 gCpuCaps.hasSSE2, | |
174 gCpuCaps.has3DNow, | |
175 gCpuCaps.has3DNowExt ); | |
176 #endif | |
177 | |
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178 /* FIXME: Does SSE2 need more OS support, too? */ |
15566 | 179 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) |
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180 if (caps->hasSSE) |
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181 check_os_katmai_support(); |
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182 if (!caps->hasSSE) |
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183 caps->hasSSE2 = 0; |
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184 #else |
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185 caps->hasSSE=0; |
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186 caps->hasSSE2 = 0; |
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187 #endif |
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188 // caps->has3DNow=1; |
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189 // caps->hasMMX2 = 0; |
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190 // caps->hasMMX = 0; |
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191 |
4829 | 192 #ifndef HAVE_MMX |
6134 | 193 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 194 caps->hasMMX=0; |
195 #endif | |
196 #ifndef HAVE_MMX2 | |
6134 | 197 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 198 caps->hasMMX2=0; |
199 #endif | |
200 #ifndef HAVE_SSE | |
6134 | 201 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 202 caps->hasSSE=0; |
203 #endif | |
204 #ifndef HAVE_SSE2 | |
6134 | 205 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 206 caps->hasSSE2=0; |
207 #endif | |
208 #ifndef HAVE_3DNOW | |
6134 | 209 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 210 caps->has3DNow=0; |
211 #endif | |
212 #ifndef HAVE_3DNOWEX | |
6134 | 213 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 214 caps->has3DNowExt=0; |
215 #endif | |
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216 } |
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217 |
2301 | 218 |
219 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
220 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
221 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
222 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
223 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
224 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
225 | |
226 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
227 #include "cputable.h" /* get cpuname and cpuvendors */ | |
13628 | 228 char vendor[17]; |
2303 | 229 char *retname; |
13628 | 230 int i; |
2301 | 231 |
2417 | 232 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 233 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 234 exit(1); |
235 } | |
236 | |
3837 | 237 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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238 |
2301 | 239 for(i=0; i<MAX_VENDORS; i++){ |
240 if(!strcmp(cpuvendors[i].string,vendor)){ | |
241 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 242 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 243 } else { |
13628 | 244 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 245 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
246 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
247 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
248 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
249 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
250 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
251 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 252 "to the MPlayer-Developers, so we can add it to the list!\n"); |
253 } | |
254 } | |
255 } | |
14478 | 256 retname[255] = 0; |
2301 | 257 |
258 //printf("Detected CPU: %s\n", retname); | |
259 return retname; | |
260 } | |
261 | |
262 #undef CPUID_EXTFAMILY | |
263 #undef CPUID_EXTMODEL | |
264 #undef CPUID_TYPE | |
265 #undef CPUID_FAMILY | |
266 #undef CPUID_MODEL | |
267 #undef CPUID_STEPPING | |
268 | |
269 | |
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270 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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271 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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272 { |
6134 | 273 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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274 |
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275 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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276 * instructions are 3 bytes long. We must increment the instruction |
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277 * pointer manually to avoid repeated execution of the offending |
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278 * instruction. |
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279 * |
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280 * If the SIGILL is caused by a divide-by-zero when unmasked |
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281 * exceptions aren't supported, the SIMD FPU status and control |
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282 * word will be restored at the end of the test, so we don't need |
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283 * to worry about doing it here. Besides, we may not be able to... |
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284 */ |
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285 sc.eip += 3; |
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286 |
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287 gCpuCaps.hasSSE=0; |
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288 } |
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289 |
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290 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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291 { |
6134 | 292 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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293 |
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294 if ( sc.fpstate->magic != 0xffff ) { |
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295 /* Our signal context has the extended FPU state, so reset the |
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296 * divide-by-zero exception mask and clear the divide-by-zero |
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297 * exception bit. |
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298 */ |
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299 sc.fpstate->mxcsr |= 0x00000200; |
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300 sc.fpstate->mxcsr &= 0xfffffffb; |
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301 } else { |
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302 /* If we ever get here, we're completely hosed. |
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303 */ |
6134 | 304 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
305 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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306 } |
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307 } |
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308 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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309 |
10440 | 310 #ifdef WIN32 |
311 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
312 { | |
313 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
314 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
315 ep->ContextRecord->Eip +=3; | |
316 gCpuCaps.hasSSE=0; | |
317 return EXCEPTION_CONTINUE_EXECUTION; | |
318 } | |
319 return EXCEPTION_CONTINUE_SEARCH; | |
320 } | |
321 #endif /* WIN32 */ | |
322 | |
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323 /* If we're running on a processor that can do SSE, let's see if we |
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324 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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325 * haven't been configured for a Pentium III but are running on one, |
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326 * and RedHat patched 2.2 kernels that have broken exception handling |
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327 * support for user space apps that do SSE. |
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328 */ |
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329 static void check_os_katmai_support( void ) |
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330 { |
14455 | 331 #ifdef ARCH_X86_64 |
332 gCpuCaps.hasSSE=1; | |
333 gCpuCaps.hasSSE2=1; | |
15566 | 334 #elif defined(__FreeBSD__) || defined(__DragonFly__) |
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335 int has_sse=0, ret; |
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336 size_t len=sizeof(has_sse); |
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337 |
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338 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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339 if (ret || !has_sse) |
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340 gCpuCaps.hasSSE=0; |
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341 |
12143 | 342 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
343 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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344 int has_sse, has_sse2, ret, mib[2]; |
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345 size_t varlen; |
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346 |
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347 mib[0] = CTL_MACHDEP; |
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348 mib[1] = CPU_SSE; |
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349 varlen = sizeof(has_sse); |
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350 |
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351 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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352 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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353 if (ret < 0 || !has_sse) { |
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354 gCpuCaps.hasSSE=0; |
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355 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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356 } else { |
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357 gCpuCaps.hasSSE=1; |
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358 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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359 } |
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360 |
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361 mib[1] = CPU_SSE2; |
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362 varlen = sizeof(has_sse2); |
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363 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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364 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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365 if (ret < 0 || !has_sse2) { |
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366 gCpuCaps.hasSSE2=0; |
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367 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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368 } else { |
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369 gCpuCaps.hasSSE2=1; |
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370 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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371 } |
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372 #else |
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373 gCpuCaps.hasSSE = 0; |
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374 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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375 #endif |
10440 | 376 #elif defined(WIN32) |
377 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
378 if ( gCpuCaps.hasSSE ) { | |
379 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
380 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
381 __asm __volatile ("xorps %xmm0, %xmm0"); | |
382 SetUnhandledExceptionFilter(exc_fil); | |
383 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
384 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
385 } | |
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386 #elif defined(__linux__) |
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387 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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388 struct sigaction saved_sigill; |
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389 struct sigaction saved_sigfpe; |
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390 |
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391 /* Save the original signal handlers. |
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392 */ |
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393 sigaction( SIGILL, NULL, &saved_sigill ); |
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394 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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395 |
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396 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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397 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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398 |
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399 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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400 * supports the extended FPU save and restore required for SSE. If |
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401 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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402 * doesn't support Streaming SIMD Exceptions, even if the processor |
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403 * does. |
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404 */ |
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405 if ( gCpuCaps.hasSSE ) { |
6134 | 406 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
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407 |
2272 | 408 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
409 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
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410 |
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411 if ( gCpuCaps.hasSSE ) { |
6134 | 412 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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413 } else { |
6134 | 414 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
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415 } |
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416 } |
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417 |
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418 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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419 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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420 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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421 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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422 * as expected, we're okay but we need to clean up after it. |
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423 * |
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424 * Are we being too stringent in our requirement that the OS support |
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425 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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426 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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427 * doesn't even support them. We at least know the user-space SSE |
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428 * support is good in kernels that do support unmasked exceptions, |
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429 * and therefore to be safe I'm going to leave this test in here. |
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430 */ |
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431 if ( gCpuCaps.hasSSE ) { |
6134 | 432 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
2268
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433 |
2272 | 434 // test_os_katmai_exception_support(); |
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435 |
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436 if ( gCpuCaps.hasSSE ) { |
6134 | 437 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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438 } else { |
6134 | 439 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
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440 } |
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441 } |
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442 |
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443 /* Restore the original signal handlers. |
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444 */ |
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445 sigaction( SIGILL, &saved_sigill, NULL ); |
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446 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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447 |
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448 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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449 * safe to go ahead and hook out the SSE code throughout Mesa. |
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450 */ |
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451 if ( gCpuCaps.hasSSE ) { |
6134 | 452 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
2268
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453 } else { |
6134 | 454 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
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455 } |
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456 #else |
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457 /* We can't use POSIX signal handling to test the availability of |
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458 * SSE, so we disable it by default. |
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459 */ |
5937 | 460 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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461 gCpuCaps.hasSSE=0; |
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462 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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463 #else |
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464 /* Do nothing on other platforms for now. |
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465 */ |
6134 | 466 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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467 gCpuCaps.hasSSE=0; |
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468 #endif /* __linux__ */ |
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469 } |
13720
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470 #else /* ARCH_X86 || ARCH_X86_64 */ |
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471 |
9003 | 472 #ifdef SYS_DARWIN |
473 #include <sys/sysctl.h> | |
474 #else | |
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475 #ifndef __AMIGAOS4__ |
9003 | 476 #include <signal.h> |
477 #include <setjmp.h> | |
478 | |
479 static sigjmp_buf jmpbuf; | |
480 static volatile sig_atomic_t canjump = 0; | |
481 | |
482 static void sigill_handler (int sig) | |
483 { | |
484 if (!canjump) { | |
485 signal (sig, SIG_DFL); | |
486 raise (sig); | |
487 } | |
488 | |
489 canjump = 0; | |
490 siglongjmp (jmpbuf, 1); | |
491 } | |
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492 #endif //__AMIGAOS4__ |
9003 | 493 #endif |
494 | |
3146
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495 void GetCpuCaps( CpuCaps *caps) |
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496 { |
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497 caps->cpuType=0; |
3403 | 498 caps->cpuStepping=0; |
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499 caps->hasMMX=0; |
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500 caps->hasMMX2=0; |
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501 caps->has3DNow=0; |
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502 caps->has3DNowExt=0; |
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503 caps->hasSSE=0; |
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504 caps->hasSSE2=0; |
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505 caps->isX86=0; |
9003 | 506 caps->hasAltiVec = 0; |
507 #ifdef HAVE_ALTIVEC | |
508 #ifdef SYS_DARWIN | |
509 /* | |
510 rip-off from ffmpeg altivec detection code. | |
511 this code also appears on Apple's AltiVec pages. | |
512 */ | |
513 { | |
514 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
515 int has_vu = 0; | |
516 size_t len = sizeof(has_vu); | |
517 int err; | |
518 | |
519 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
520 | |
521 if (err == 0) | |
522 if (has_vu != 0) | |
523 caps->hasAltiVec = 1; | |
524 } | |
525 #else /* SYS_DARWIN */ | |
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526 #ifdef __AMIGAOS4__ |
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527 ULONG result = 0; |
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528 |
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529 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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530 if (result == VECTORTYPE_ALTIVEC) |
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531 caps->hasAltiVec = 1; |
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532 #else |
9003 | 533 /* no Darwin, do it the brute-force way */ |
534 /* this is borrowed from the libmpeg2 library */ | |
535 { | |
536 signal (SIGILL, sigill_handler); | |
537 if (sigsetjmp (jmpbuf, 1)) { | |
538 signal (SIGILL, SIG_DFL); | |
539 } else { | |
540 canjump = 1; | |
541 | |
542 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 543 "vand %%v0, %%v0, %%v0" |
9003 | 544 : |
545 : "r" (-1)); | |
546 | |
547 signal (SIGILL, SIG_DFL); | |
548 caps->hasAltiVec = 1; | |
549 } | |
550 } | |
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551 #endif //__AMIGAOS4__ |
9003 | 552 #endif /* SYS_DARWIN */ |
9324 | 553 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 554 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
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|
555 |
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556 #ifdef ARCH_IA64 |
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557 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
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558 #endif |
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|
559 |
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560 #ifdef ARCH_SPARC |
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561 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
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562 #endif |
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563 |
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564 #ifdef ARCH_ARMV4L |
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565 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
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|
566 #endif |
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|
567 |
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568 #ifdef ARCH_POWERPC |
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569 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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570 #endif |
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571 |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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572 #ifdef ARCH_ALPHA |
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573 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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574 #endif |
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575 |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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576 #ifdef ARCH_SGI_MIPS |
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577 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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578 #endif |
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579 |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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580 #ifdef ARCH_PA_RISC |
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581 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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582 #endif |
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|
583 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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584 #ifdef ARCH_S390 |
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585 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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586 #endif |
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587 |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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588 #ifdef ARCH_S390X |
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589 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
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590 #endif |
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|
591 |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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592 #ifdef ARCH_VAX |
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593 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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594 #endif |
3146
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
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changeset
|
595 } |
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
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596 #endif /* !ARCH_X86 */ |