Mercurial > mplayer.hg
annotate vidix/drivers/mach64_vid.c @ 7838:1a6da24ad34c
save colorkey stuff patch by (Colin Leroy <colin at colino dot net>)
author | michael |
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date | Tue, 22 Oct 2002 13:20:53 +0000 |
parents | 6bfe33dc531e |
children | 9ec1e707f736 |
rev | line source |
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4691 | 1 /* |
2 mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips | |
3 Copyrights 2002 Nick Kurshev. This file is based on sources from | |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
4866 | 6 WARNING: THIS DRIVER IS IN BETTA STAGE |
4691 | 7 */ |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
13 #include <inttypes.h> | |
14 #include <fcntl.h> | |
15 | |
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16 #include "../../config.h" |
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17 #include "../../bswap.h" |
4691 | 18 #include "../vidix.h" |
19 #include "../fourcc.h" | |
20 #include "../../libdha/libdha.h" | |
21 #include "../../libdha/pci_ids.h" | |
22 #include "../../libdha/pci_names.h" | |
23 | |
24 #include "mach64.h" | |
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25 #include "../../version.h" |
4691 | 26 |
27 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ | |
28 | |
29 static void *mach64_mmio_base = 0; | |
30 static void *mach64_mem_base = 0; | |
4721 | 31 static int32_t mach64_overlay_offset = 0; |
4691 | 32 static uint32_t mach64_ram_size = 0; |
4866 | 33 static uint32_t mach64_buffer_base[10][3]; |
34 static int num_mach64_buffers=-1; | |
4876 | 35 static int supports_planar=0; |
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36 static int supports_lcd_v_stretch=0; |
4691 | 37 |
38 pciinfo_t pci_info; | |
39 static int probed = 0; | |
40 static int __verbose = 0; | |
4721 | 41 |
4758 | 42 #define VERBOSE_LEVEL 1 |
43 | |
4721 | 44 typedef struct bes_registers_s |
45 { | |
46 /* base address of yuv framebuffer */ | |
47 uint32_t yuv_base; | |
48 uint32_t fourcc; | |
49 /* YUV BES registers */ | |
50 uint32_t reg_load_cntl; | |
51 uint32_t scale_inc; | |
52 uint32_t y_x_start; | |
53 uint32_t y_x_end; | |
54 uint32_t vid_buf_pitch; | |
55 uint32_t height_width; | |
56 | |
57 uint32_t scale_cntl; | |
58 uint32_t exclusive_horz; | |
59 uint32_t auto_flip_cntl; | |
60 uint32_t filter_cntl; | |
61 uint32_t key_cntl; | |
62 uint32_t test; | |
63 /* Configurable stuff */ | |
64 | |
65 int brightness; | |
66 int saturation; | |
67 | |
68 int ckey_on; | |
69 uint32_t graphics_key_clr; | |
70 uint32_t graphics_key_msk; | |
71 | |
72 int deinterlace_on; | |
73 uint32_t deinterlace_pattern; | |
74 | |
75 } bes_registers_t; | |
76 | |
77 static bes_registers_t besr; | |
78 | |
79 typedef struct video_registers_s | |
80 { | |
81 const char * sname; | |
82 uint32_t name; | |
83 uint32_t value; | |
84 }video_registers_t; | |
85 | |
86 static bes_registers_t besr; | |
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87 |
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88 /* Graphic keys */ |
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89 static vidix_grkey_t mach64_grkey; |
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90 |
4721 | 91 #define DECLARE_VREG(name) { #name, name, 0 } |
92 static video_registers_t vregs[] = | |
93 { | |
94 DECLARE_VREG(OVERLAY_SCALE_INC), | |
95 DECLARE_VREG(OVERLAY_Y_X_START), | |
96 DECLARE_VREG(OVERLAY_Y_X_END), | |
97 DECLARE_VREG(OVERLAY_SCALE_CNTL), | |
98 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), | |
99 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), | |
100 DECLARE_VREG(OVERLAY_TEST), | |
101 DECLARE_VREG(SCALER_BUF_PITCH), | |
102 DECLARE_VREG(SCALER_HEIGHT_WIDTH), | |
103 DECLARE_VREG(SCALER_BUF0_OFFSET), | |
104 DECLARE_VREG(SCALER_BUF0_OFFSET_U), | |
105 DECLARE_VREG(SCALER_BUF0_OFFSET_V), | |
106 DECLARE_VREG(SCALER_BUF1_OFFSET), | |
107 DECLARE_VREG(SCALER_BUF1_OFFSET_U), | |
108 DECLARE_VREG(SCALER_BUF1_OFFSET_V), | |
109 DECLARE_VREG(SCALER_H_COEFF0), | |
110 DECLARE_VREG(SCALER_H_COEFF1), | |
111 DECLARE_VREG(SCALER_H_COEFF2), | |
112 DECLARE_VREG(SCALER_H_COEFF3), | |
113 DECLARE_VREG(SCALER_H_COEFF4), | |
114 DECLARE_VREG(SCALER_COLOUR_CNTL), | |
115 DECLARE_VREG(SCALER_THRESHOLD), | |
116 DECLARE_VREG(VIDEO_FORMAT), | |
117 DECLARE_VREG(VIDEO_CONFIG), | |
118 DECLARE_VREG(VIDEO_SYNC_TEST), | |
119 DECLARE_VREG(VIDEO_SYNC_TEST_B) | |
120 }; | |
121 | |
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122 /* have to restore it on exit */ |
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123 static uint32_t SAVED_OVERLAY_GRAPHICS_KEY_CLR; |
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124 |
4691 | 125 /* VIDIX exports */ |
126 | |
127 /* MMIO space*/ | |
128 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
129 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
130 | |
4721 | 131 #define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) |
132 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) | |
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133 #define INREG(addr) le2me_32(GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2)) |
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134 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val)) |
4691 | 135 |
136 #define OUTREGP(addr,val,mask) \ | |
137 do { \ | |
138 unsigned int _tmp = INREG(addr); \ | |
139 _tmp &= (mask); \ | |
140 _tmp |= (val); \ | |
141 OUTREG(addr, _tmp); \ | |
142 } while (0) | |
143 | |
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144 static __inline__ int ATIGetMach64LCDReg(int _Index) |
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145 { |
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146 OUTREG8(LCD_INDEX, _Index); |
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147 return INREG(LCD_DATA); |
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148 } |
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149 |
4691 | 150 static __inline__ uint32_t INPLL(uint32_t addr) |
151 { | |
4721 | 152 uint32_t res; |
5731 | 153 uint32_t in; |
154 | |
5792 | 155 in= INREG(CLOCK_CNTL); |
156 in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff | |
157 OUTREG(CLOCK_CNTL, in | (addr<<10)); | |
5731 | 158 |
4721 | 159 /* read the register value */ |
5792 | 160 res = (INREG(CLOCK_CNTL)>>16)&0xFF; |
4721 | 161 return res; |
4691 | 162 } |
163 | |
4721 | 164 static __inline__ void OUTPLL(uint32_t addr,uint32_t val) |
165 { | |
5792 | 166 //FIXME buggy but its not used |
4721 | 167 /* write addr byte */ |
168 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); | |
169 /* write the register value */ | |
170 OUTREG(CLOCK_CNTL + 2, val); | |
171 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); | |
172 } | |
173 | |
4691 | 174 #define OUTPLLP(addr,val,mask) \ |
175 do { \ | |
176 unsigned int _tmp = INPLL(addr); \ | |
177 _tmp &= (mask); \ | |
178 _tmp |= (val); \ | |
179 OUTPLL(addr, _tmp); \ | |
180 } while (0) | |
181 | |
4721 | 182 static void mach64_fifo_wait(unsigned n) |
183 { | |
184 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); | |
185 } | |
186 | |
187 static void mach64_wait_for_idle( void ) | |
188 { | |
189 mach64_fifo_wait(16); | |
190 while ((INREG(GUI_STAT) & 1)!= 0); | |
191 } | |
192 | |
4876 | 193 static void mach64_wait_vsync( void ) |
194 { | |
195 int i; | |
196 | |
197 for(i=0; i<2000000; i++) | |
198 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; | |
199 for(i=0; i<2000000; i++) | |
200 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; | |
201 | |
202 } | |
203 | |
4691 | 204 static vidix_capability_t mach64_cap = |
205 { | |
206 "BES driver for Mach64/3DRage cards", | |
4872 | 207 "Nick Kurshev and Michael Niedermayer", |
4691 | 208 TYPE_OUTPUT, |
209 { 0, 0, 0, 0 }, | |
210 2048, | |
211 2048, | |
212 4, | |
213 4, | |
214 -1, | |
215 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
216 VENDOR_ATI, | |
217 -1, | |
218 { 0, 0, 0, 0 } | |
219 }; | |
220 | |
4721 | 221 static uint32_t mach64_vid_get_dbpp( void ) |
222 { | |
223 uint32_t dbpp,retval; | |
224 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; | |
225 switch(dbpp) | |
226 { | |
227 case 1: retval = 4; break; | |
228 case 2: retval = 8; break; | |
229 case 3: retval = 15; break; | |
230 case 4: retval = 16; break; | |
231 case 5: retval = 24; break; | |
232 default: retval=32; break; | |
233 } | |
234 return retval; | |
235 } | |
236 | |
237 static int mach64_is_dbl_scan( void ) | |
238 { | |
239 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; | |
240 } | |
241 | |
242 static int mach64_is_interlace( void ) | |
243 { | |
244 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; | |
245 } | |
246 | |
247 static uint32_t mach64_get_xres( void ) | |
248 { | |
249 /* FIXME: currently we extract that from CRTC!!!*/ | |
250 uint32_t xres,h_total; | |
251 h_total = INREG(CRTC_H_TOTAL_DISP); | |
252 xres = (h_total >> 16) & 0xffff; | |
253 return (xres + 1)*8; | |
254 } | |
255 | |
256 static uint32_t mach64_get_yres( void ) | |
257 { | |
258 /* FIXME: currently we extract that from CRTC!!!*/ | |
259 uint32_t yres,v_total; | |
260 v_total = INREG(CRTC_V_TOTAL_DISP); | |
261 yres = (v_total >> 16) & 0xffff; | |
262 return yres + 1; | |
263 } | |
264 | |
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265 // returns the verical stretch factor in 16.16 |
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266 static int mach64_get_vert_stretch(void) |
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267 { |
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268 int lcd_index; |
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269 int vert_stretching; |
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270 int ext_vert_stretch; |
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271 int ret; |
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272 int yres= mach64_get_yres(); |
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273 |
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274 if(!supports_lcd_v_stretch){ |
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275 if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); |
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276 return 1<<16; |
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277 } |
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278 |
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279 lcd_index= INREG(LCD_INDEX); |
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280 |
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281 vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); |
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282 if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; |
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283 else |
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284 { |
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285 int panel_size; |
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286 |
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287 ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); |
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288 panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; |
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289 panel_size++; |
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290 |
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291 ret= ((yres<<16) + (panel_size>>1))/panel_size; |
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292 } |
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293 |
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294 // lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); |
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295 |
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296 OUTREG(LCD_INDEX, lcd_index); |
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297 |
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298 if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); |
4872 | 299 |
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300 return ret; |
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301 } |
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302 |
4721 | 303 static void mach64_vid_make_default() |
304 { | |
4872 | 305 mach64_fifo_wait(5); |
4761 | 306 OUTREG(SCALER_COLOUR_CNTL,0x00101000); |
4872 | 307 |
308 besr.ckey_on=0; | |
309 besr.graphics_key_msk=0; | |
310 besr.graphics_key_clr=0; | |
311 | |
312 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
313 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
314 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
315 | |
4721 | 316 } |
317 | |
318 static void mach64_vid_dump_regs( void ) | |
319 { | |
320 size_t i; | |
321 printf("[mach64] *** Begin of DRIVER variables dump ***\n"); | |
322 printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); | |
323 printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); | |
324 printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); | |
325 printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); | |
326 printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); | |
327 printf("[mach64] *** Begin of OV0 registers dump ***\n"); | |
328 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
329 { | |
330 mach64_wait_for_idle(); | |
331 printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
332 } | |
333 printf("[mach64] *** End of OV0 registers dump ***\n"); | |
334 } | |
335 | |
336 | |
4691 | 337 unsigned int vixGetVersion(void) |
338 { | |
339 return(VIDIX_VERSION); | |
340 } | |
341 | |
342 static unsigned short ati_card_ids[] = | |
343 { | |
344 DEVICE_ATI_215CT_MACH64_CT, | |
345 DEVICE_ATI_210888CX_MACH64_CX, | |
346 DEVICE_ATI_210888ET_MACH64_ET, | |
347 DEVICE_ATI_MACH64_VT, | |
348 DEVICE_ATI_210888GX_MACH64_GX, | |
349 DEVICE_ATI_264LT_MACH64_LT, | |
350 DEVICE_ATI_264VT_MACH64_VT, | |
351 DEVICE_ATI_264VT3_MACH64_VT3, | |
352 DEVICE_ATI_264VT4_MACH64_VT4, | |
353 /**/ | |
354 DEVICE_ATI_3D_RAGE_PRO, | |
355 DEVICE_ATI_3D_RAGE_PRO2, | |
356 DEVICE_ATI_3D_RAGE_PRO3, | |
357 DEVICE_ATI_3D_RAGE_PRO4, | |
358 DEVICE_ATI_RAGE_XC, | |
359 DEVICE_ATI_RAGE_XL_AGP, | |
360 DEVICE_ATI_RAGE_XC_AGP, | |
361 DEVICE_ATI_RAGE_XL, | |
362 DEVICE_ATI_3D_RAGE_PRO5, | |
363 DEVICE_ATI_3D_RAGE_PRO6, | |
364 DEVICE_ATI_RAGE_XL2, | |
365 DEVICE_ATI_RAGE_XC2, | |
366 DEVICE_ATI_3D_RAGE_I_II, | |
367 DEVICE_ATI_3D_RAGE_II, | |
368 DEVICE_ATI_3D_RAGE_IIC, | |
369 DEVICE_ATI_3D_RAGE_IIC2, | |
370 DEVICE_ATI_3D_RAGE_IIC3, | |
371 DEVICE_ATI_3D_RAGE_IIC4, | |
372 DEVICE_ATI_3D_RAGE_LT, | |
373 DEVICE_ATI_3D_RAGE_LT2, | |
374 DEVICE_ATI_3D_RAGE_LT_G, | |
375 DEVICE_ATI_3D_RAGE_LT3, | |
376 DEVICE_ATI_RAGE_MOBILITY_P_M, | |
377 DEVICE_ATI_RAGE_MOBILITY_L, | |
378 DEVICE_ATI_3D_RAGE_LT4, | |
379 DEVICE_ATI_3D_RAGE_LT5, | |
380 DEVICE_ATI_RAGE_MOBILITY_P_M2, | |
381 DEVICE_ATI_RAGE_MOBILITY_L2 | |
382 }; | |
383 | |
384 static int find_chip(unsigned chip_id) | |
385 { | |
386 unsigned i; | |
387 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) | |
388 { | |
389 if(chip_id == ati_card_ids[i]) return i; | |
390 } | |
391 return -1; | |
392 } | |
393 | |
394 int vixProbe(int verbose,int force) | |
395 { | |
396 pciinfo_t lst[MAX_PCI_DEVICES]; | |
397 unsigned i,num_pci; | |
398 int err; | |
399 __verbose = verbose; | |
400 err = pci_scan(lst,&num_pci); | |
401 if(err) | |
402 { | |
403 printf("[mach64] Error occured during pci scan: %s\n",strerror(err)); | |
404 return err; | |
405 } | |
406 else | |
407 { | |
408 err = ENXIO; | |
409 for(i=0;i<num_pci;i++) | |
410 { | |
411 if(lst[i].vendor == VENDOR_ATI) | |
412 { | |
413 int idx; | |
414 const char *dname; | |
415 idx = find_chip(lst[i].device); | |
416 if(idx == -1 && force == PROBE_NORMAL) continue; | |
417 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
418 dname = dname ? dname : "Unknown chip"; | |
419 printf("[mach64] Found chip: %s\n",dname); | |
420 if(force > PROBE_NORMAL) | |
421 { | |
422 printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
423 if(idx == -1) | |
424 printf("[mach64] Assuming it as Mach64\n"); | |
425 } | |
426 mach64_cap.device_id = lst[i].device; | |
427 err = 0; | |
428 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
429 probed=1; | |
430 break; | |
431 } | |
432 } | |
433 } | |
434 if(err && verbose) printf("[mach64] Can't find chip\n"); | |
435 return err; | |
436 } | |
437 | |
4721 | 438 static void reset_regs( void ) |
439 { | |
440 size_t i; | |
441 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
442 { | |
443 mach64_fifo_wait(2); | |
4758 | 444 OUTREG(vregs[i].name,0); |
4721 | 445 } |
446 } | |
447 | |
448 | |
4691 | 449 int vixInit(void) |
450 { | |
451 int err; | |
452 if(!probed) | |
453 { | |
454 printf("[mach64] Driver was not probed but is being initializing\n"); | |
455 return EINTR; | |
456 } | |
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457 if(__verbose>0) printf("[mach64] version %s\n", VERSION); |
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458 |
4721 | 459 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; |
460 mach64_wait_for_idle(); | |
4691 | 461 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; |
462 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; | |
463 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; | |
464 else mach64_ram_size = (mach64_ram_size - 7) * 2048; | |
465 mach64_ram_size *= 0x400; /* KB -> bytes */ | |
466 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; | |
4758 | 467 memset(&besr,0,sizeof(bes_registers_t)); |
4691 | 468 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); |
469 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); | |
470 if(!err) printf("[mach64] Set write-combining type of video memory\n"); | |
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471 |
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472 /* save this */ |
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473 mach64_wait_for_idle(); |
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474 SAVED_OVERLAY_GRAPHICS_KEY_CLR = INREG(OVERLAY_GRAPHICS_KEY_CLR); |
4876 | 475 |
476 /* check if planar formats are supported */ | |
477 supports_planar=0; | |
478 mach64_wait_for_idle(); | |
479 mach64_fifo_wait(2); | |
480 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
481 else | |
482 { | |
483 OUTREG(SCALER_BUF0_OFFSET_U, -1); | |
484 | |
485 mach64_wait_vsync(); | |
486 mach64_wait_for_idle(); | |
487 mach64_fifo_wait(2); | |
488 | |
489 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
490 } | |
491 if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); | |
492 else printf("[mach64] Planar YUV formats are not supported :(\n"); | |
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493 |
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494 if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M |
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495 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 |
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496 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L |
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497 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) |
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498 supports_lcd_v_stretch=1; |
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499 else |
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500 supports_lcd_v_stretch=0; |
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501 |
4721 | 502 reset_regs(); |
4761 | 503 mach64_vid_make_default(); |
4876 | 504 |
4758 | 505 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4691 | 506 return 0; |
507 } | |
508 | |
509 void vixDestroy(void) | |
510 { | |
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511 /*restore this*/ |
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512 mach64_wait_for_idle(); |
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513 OUTREG(OVERLAY_GRAPHICS_KEY_CLR,SAVED_OVERLAY_GRAPHICS_KEY_CLR); |
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514 |
4691 | 515 unmap_phys_mem(mach64_mem_base,mach64_ram_size); |
4721 | 516 unmap_phys_mem(mach64_mmio_base,0x4000); |
4691 | 517 } |
518 | |
519 int vixGetCapability(vidix_capability_t *to) | |
520 { | |
521 memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); | |
522 return 0; | |
523 } | |
524 | |
4721 | 525 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
526 { | |
527 unsigned pitch,spy,spv,spu; | |
528 spy = spv = spu = 0; | |
529 switch(spitch->y) | |
530 { | |
531 case 16: | |
532 case 32: | |
533 case 64: | |
534 case 128: | |
535 case 256: spy = spitch->y; break; | |
536 default: break; | |
537 } | |
538 switch(spitch->u) | |
539 { | |
540 case 16: | |
541 case 32: | |
542 case 64: | |
543 case 128: | |
544 case 256: spu = spitch->u; break; | |
545 default: break; | |
546 } | |
547 switch(spitch->v) | |
548 { | |
549 case 16: | |
550 case 32: | |
551 case 64: | |
552 case 128: | |
553 case 256: spv = spitch->v; break; | |
554 default: break; | |
555 } | |
556 switch(fourcc) | |
557 { | |
558 /* 4:2:0 */ | |
559 case IMGFMT_IYUV: | |
560 case IMGFMT_YV12: | |
561 case IMGFMT_I420: | |
562 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
563 else pitch = 32; | |
564 break; | |
4872 | 565 case IMGFMT_YVU9: |
566 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; | |
567 else pitch = 64; | |
568 break; | |
4721 | 569 default: |
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570 if(spy >= 16) pitch = spy; |
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571 else pitch = 16; |
4721 | 572 break; |
573 } | |
574 return pitch; | |
575 } | |
576 | |
577 static void mach64_compute_framesize(vidix_playback_t *info) | |
578 { | |
579 unsigned pitch,awidth; | |
580 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); | |
581 switch(info->fourcc) | |
582 { | |
583 case IMGFMT_I420: | |
584 case IMGFMT_YV12: | |
585 case IMGFMT_IYUV: | |
586 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
587 info->frame_size = awidth*(info->src.h+info->src.h/2); | |
588 break; | |
4872 | 589 case IMGFMT_YVU9: |
590 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
591 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
592 break; | |
593 // case IMGFMT_RGB32: | |
4721 | 594 case IMGFMT_BGR32: |
595 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); | |
596 info->frame_size = (awidth*info->src.h); | |
597 break; | |
598 /* YUY2 YVYU, RGB15, RGB16 */ | |
599 default: | |
600 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
601 info->frame_size = (awidth*info->src.h); | |
602 break; | |
603 } | |
4872 | 604 info->frame_size+=256; // so we have some space for alignment & such |
605 info->frame_size&=~16; | |
4721 | 606 } |
607 | |
608 static void mach64_vid_stop_video( void ) | |
609 { | |
610 mach64_fifo_wait(14); | |
611 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); | |
612 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); | |
613 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); | |
614 OUTREG(SCALER_H_COEFF0, 0x00002000); | |
615 OUTREG(SCALER_H_COEFF1, 0x0D06200D); | |
616 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); | |
617 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); | |
618 OUTREG(SCALER_H_COEFF4, 0x0C14140C); | |
619 OUTREG(VIDEO_FORMAT, 0xB000B); | |
620 OUTREG(OVERLAY_TEST, 0x0); | |
621 } | |
622 | |
623 static void mach64_vid_display_video( void ) | |
624 { | |
625 uint32_t vf; | |
626 mach64_fifo_wait(14); | |
627 | |
628 OUTREG(OVERLAY_Y_X_START, besr.y_x_start); | |
629 OUTREG(OVERLAY_Y_X_END, besr.y_x_end); | |
630 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); | |
631 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); | |
632 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); | |
4866 | 633 OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); |
634 OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); | |
635 OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); | |
636 OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); | |
637 OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); | |
638 OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); | |
4876 | 639 mach64_wait_vsync(); |
640 | |
641 mach64_fifo_wait(4); | |
4758 | 642 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); |
4760 | 643 // OVERLAY_SCALE_CNTL bits & what they seem to affect |
644 // bit 0 no effect | |
645 // bit 1 yuv2rgb coeff related | |
646 // bit 2 horizontal interpolation if 0 | |
647 // bit 3 vertical interpolation if 0 | |
4847 | 648 // bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) |
4760 | 649 // bit 5-6 gamma correction |
650 // bit 7 nothing visible if set | |
651 // bit 8-27 no effect | |
652 // bit 28-31 nothing interresting just crashed my system when i played with them :( | |
4847 | 653 |
4721 | 654 mach64_wait_for_idle(); |
655 vf = INREG(VIDEO_FORMAT); | |
4751 | 656 |
657 // Bits 16-19 seem to select the format | |
4769 | 658 // 0x0 dunno behaves strange |
659 // 0x1 dunno behaves strange | |
660 // 0x2 dunno behaves strange | |
661 // 0x3 BGR15 | |
662 // 0x4 BGR16 | |
663 // 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) | |
664 // 0x6 BGR32 | |
665 // 0x7 BGR32 with somehow mixed even / odd pixels ? | |
666 // 0x8 YYYYUVUV | |
667 // 0x9 YVU9 | |
668 // 0xA YV12 | |
669 // 0xB YUY2 | |
670 // 0xC UYVY | |
4847 | 671 // 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) |
4769 | 672 // 0xE dunno behaves strange |
673 // 0xF dunno behaves strange | |
674 // Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) | |
4751 | 675 // the remaining bits seem to have no effect |
676 | |
4769 | 677 |
4721 | 678 switch(besr.fourcc) |
679 { | |
4769 | 680 /* BGR formats */ |
681 case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; | |
682 case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; | |
683 case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; | |
4721 | 684 /* 4:2:0 */ |
685 case IMGFMT_IYUV: | |
686 case IMGFMT_I420: | |
4769 | 687 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; |
4872 | 688 |
689 case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; | |
4721 | 690 /* 4:2:2 */ |
691 case IMGFMT_YVYU: | |
4769 | 692 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; |
4721 | 693 case IMGFMT_YUY2: |
4769 | 694 default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; |
4721 | 695 } |
4758 | 696 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 697 } |
698 | |
699 static int mach64_vid_init_video( vidix_playback_t *config ) | |
700 { | |
4758 | 701 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; |
4721 | 702 int is_420,best_pitch,mpitch; |
4866 | 703 int src_offset_y, src_offset_u, src_offset_v; |
704 unsigned int i; | |
4872 | 705 |
4721 | 706 mach64_vid_stop_video(); |
4866 | 707 /* warning, if left or top are != 0 this will fail, as the framesize is too small then */ |
708 left = config->src.x; | |
709 top = config->src.y; | |
4721 | 710 src_h = config->src.h; |
711 src_w = config->src.w; | |
712 is_420 = 0; | |
713 if(config->fourcc == IMGFMT_YV12 || | |
714 config->fourcc == IMGFMT_I420 || | |
715 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
716 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); | |
717 mpitch = best_pitch-1; | |
718 switch(config->fourcc) | |
719 { | |
4872 | 720 case IMGFMT_YVU9: |
4721 | 721 /* 4:2:0 */ |
722 case IMGFMT_IYUV: | |
723 case IMGFMT_YV12: | |
724 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; | |
725 config->dest.pitch.y = | |
726 config->dest.pitch.u = | |
727 config->dest.pitch.v = best_pitch; | |
4769 | 728 besr.vid_buf_pitch= pitch; |
4721 | 729 break; |
730 /* RGB 4:4:4:4 */ | |
731 case IMGFMT_RGB32: | |
732 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
733 config->dest.pitch.y = | |
734 config->dest.pitch.u = | |
735 config->dest.pitch.v = best_pitch; | |
4769 | 736 besr.vid_buf_pitch= pitch>>2; |
4721 | 737 break; |
738 /* 4:2:2 */ | |
739 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ | |
740 pitch = ((src_w*2) + mpitch) & ~mpitch; | |
741 config->dest.pitch.y = | |
742 config->dest.pitch.u = | |
743 config->dest.pitch.v = best_pitch; | |
4769 | 744 besr.vid_buf_pitch= pitch>>1; |
4721 | 745 break; |
746 } | |
747 dest_w = config->dest.w; | |
748 dest_h = config->dest.h; | |
749 besr.fourcc = config->fourcc; | |
750 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; | |
5792 | 751 #if 0 |
752 { | |
753 int i; | |
754 for(i=0; i<32; i++){ | |
755 printf("%X ", INPLL(i)); | |
756 } | |
757 } | |
758 #endif | |
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759 if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); |
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760 v_inc = src_h * mach64_get_vert_stretch(); |
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761 |
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762 if(mach64_is_interlace()) v_inc<<=1; |
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763 if(mach64_is_dbl_scan() ) v_inc>>=1; |
601e8a796c38
colorkey support fixed (thanks to nick for the mga_vid tip ... i should RTFS more)
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parents:
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diff
changeset
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764 v_inc>>=4; // convert 16.16 -> 20.12 |
601e8a796c38
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changeset
|
765 v_inc/= dest_h; |
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changeset
|
766 |
5731 | 767 h_inc = (src_w << (12+ecp)) / dest_w; |
4721 | 768 /* keep everything in 16.16 */ |
769 config->offsets[0] = 0; | |
4866 | 770 for(i=1; i<config->num_frames; i++) |
771 config->offsets[i] = config->offsets[i-1] + config->frame_size; | |
772 | |
4872 | 773 /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) |
774 1. the framesize isnt known as the outer src rectangle dimensions arent known | |
775 2. the mach64 needs aligned addresses so it cant work anyway | |
776 -> so we could shift the outer buffer to compensate that but that would mean | |
777 alignment problems for the code which writes into it | |
778 */ | |
779 | |
4721 | 780 if(is_420) |
781 { | |
4866 | 782 config->offset.y= 0; |
4872 | 783 config->offset.u= (pitch*src_h + 15)&~15; |
784 config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; | |
785 | |
4866 | 786 src_offset_y= config->offset.y + top*pitch + left; |
787 src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); | |
788 src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); | |
4872 | 789 |
4721 | 790 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
791 { | |
792 uint32_t tmp; | |
793 tmp = config->offset.u; | |
794 config->offset.u = config->offset.v; | |
795 config->offset.v = tmp; | |
796 } | |
797 } | |
4872 | 798 else if(besr.fourcc == IMGFMT_YVU9) |
799 { | |
800 config->offset.y= 0; | |
801 config->offset.u= (pitch*src_h + 15)&~15; | |
802 config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; | |
803 | |
804 src_offset_y= config->offset.y + top*pitch + left; | |
805 src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); | |
806 src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); | |
807 } | |
4866 | 808 else if(besr.fourcc == IMGFMT_BGR32) |
809 { | |
810 config->offset.y = config->offset.u = config->offset.v = 0; | |
4872 | 811 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); |
4866 | 812 } |
4721 | 813 else |
814 { | |
4866 | 815 config->offset.y = config->offset.u = config->offset.v = 0; |
4872 | 816 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); |
4866 | 817 } |
818 | |
819 num_mach64_buffers= config->num_frames; | |
820 for(i=0; i<config->num_frames; i++) | |
821 { | |
822 mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; | |
823 mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; | |
824 mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; | |
4721 | 825 } |
826 | |
827 leftUV = (left >> 17) & 15; | |
828 left = (left >> 16) & 15; | |
829 besr.scale_inc = ( h_inc << 16 ) | v_inc; | |
4758 | 830 y_pos = config->dest.y; |
831 if(mach64_is_dbl_scan()) y_pos*=2; | |
832 else | |
833 if(mach64_is_interlace()) y_pos/=2; | |
834 besr.y_x_start = y_pos | (config->dest.x << 16); | |
835 y_pos =config->dest.y + dest_h; | |
836 if(mach64_is_dbl_scan()) y_pos*=2; | |
837 else | |
838 if(mach64_is_interlace()) y_pos/=2; | |
839 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); | |
4721 | 840 besr.height_width = ((src_w - left)<<16) | (src_h - top); |
4769 | 841 |
4721 | 842 return 0; |
843 } | |
844 | |
4876 | 845 static int is_supported_fourcc(uint32_t fourcc) |
4721 | 846 { |
4876 | 847 switch(fourcc) |
848 { | |
849 case IMGFMT_YV12: | |
850 case IMGFMT_I420: | |
851 case IMGFMT_YVU9: | |
852 case IMGFMT_IYUV: | |
853 return supports_planar; | |
854 case IMGFMT_YUY2: | |
855 case IMGFMT_UYVY: | |
856 case IMGFMT_BGR15: | |
857 case IMGFMT_BGR16: | |
858 case IMGFMT_BGR32: | |
859 return 1; | |
860 default: | |
861 return 0; | |
862 } | |
4721 | 863 } |
864 | |
4691 | 865 int vixQueryFourcc(vidix_fourcc_t *to) |
866 { | |
4721 | 867 if(is_supported_fourcc(to->fourcc)) |
868 { | |
869 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
870 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
871 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
872 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
873 VID_DEPTH_32BPP; | |
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874 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
4721 | 875 return 0; |
876 } | |
877 else to->depth = to->flags = 0; | |
4691 | 878 return ENOSYS; |
879 } | |
880 | |
881 int vixConfigPlayback(vidix_playback_t *info) | |
882 { | |
4721 | 883 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
4866 | 884 |
4721 | 885 mach64_compute_framesize(info); |
4894
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886 |
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887 if(info->num_frames>4) info->num_frames=4; |
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888 for(;info->num_frames>0; info->num_frames--) |
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889 { |
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890 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; |
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891 mach64_overlay_offset &= 0xffff0000; |
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892 if(mach64_overlay_offset>0) break; |
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893 } |
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894 if(info->num_frames <= 0) return EINVAL; |
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895 |
4721 | 896 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; |
897 mach64_vid_init_video(info); | |
898 return 0; | |
4691 | 899 } |
900 | |
901 int vixPlaybackOn(void) | |
902 { | |
4721 | 903 mach64_vid_display_video(); |
904 return 0; | |
4691 | 905 } |
906 | |
907 int vixPlaybackOff(void) | |
908 { | |
4721 | 909 mach64_vid_stop_video(); |
910 return 0; | |
911 } | |
912 | |
4691 | 913 int vixPlaybackFrameSelect(unsigned int frame) |
914 { | |
4721 | 915 uint32_t off[6]; |
4866 | 916 int i; |
917 int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; | |
918 //printf("Selecting frame %d\n", frame); | |
4721 | 919 /* |
920 buf3-5 always should point onto second buffer for better | |
921 deinterlacing and TV-in | |
922 */ | |
4866 | 923 if(num_mach64_buffers==1) return 0; |
924 | |
925 for(i=0; i<3; i++) | |
4721 | 926 { |
4866 | 927 off[i] = mach64_buffer_base[frame][i]; |
928 off[i+3]= mach64_buffer_base[last_frame][i]; | |
929 } | |
4769 | 930 |
4847 | 931 #if 0 // delay routine so the individual frames can be ssen better |
932 { | |
933 volatile int i=0; | |
934 for(i=0; i<10000000; i++); | |
935 } | |
936 #endif | |
4721 | 937 |
938 mach64_wait_for_idle(); | |
939 mach64_fifo_wait(7); | |
4847 | 940 |
4721 | 941 OUTREG(SCALER_BUF0_OFFSET, off[0]); |
942 OUTREG(SCALER_BUF0_OFFSET_U, off[1]); | |
943 OUTREG(SCALER_BUF0_OFFSET_V, off[2]); | |
944 OUTREG(SCALER_BUF1_OFFSET, off[3]); | |
945 OUTREG(SCALER_BUF1_OFFSET_U, off[4]); | |
946 OUTREG(SCALER_BUF1_OFFSET_V, off[5]); | |
4866 | 947 if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering |
948 | |
4758 | 949 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 950 return 0; |
4691 | 951 } |
4721 | 952 |
953 vidix_video_eq_t equal = | |
954 { | |
955 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | |
956 , | |
957 0, 0, 0, 0, 0, 0, 0, 0 }; | |
958 | |
959 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
960 { | |
961 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
962 return 0; | |
963 } | |
964 | |
965 int vixPlaybackSetEq( const vidix_video_eq_t * eq) | |
966 { | |
967 int br,sat; | |
968 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; | |
969 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; | |
970 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; | |
971 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; | |
972 if(eq->cap & VEQ_CAP_RGB_INTENSITY) | |
973 { | |
974 equal.red_intensity = eq->red_intensity; | |
975 equal.green_intensity = eq->green_intensity; | |
976 equal.blue_intensity = eq->blue_intensity; | |
977 } | |
978 equal.flags = eq->flags; | |
979 br = equal.brightness * 64 / 1000; | |
980 if(br < -64) br = -64; if(br > 63) br = 63; | |
981 sat = (equal.saturation + 1000) * 16 / 1000; | |
982 if(sat < 0) sat = 0; if(sat > 31) sat = 31; | |
983 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
984 return 0; | |
985 } | |
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986 |
601e8a796c38
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987 int vixGetGrKeys(vidix_grkey_t *grkey) |
601e8a796c38
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parents:
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988 { |
601e8a796c38
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michael
parents:
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989 memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); |
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990 return(0); |
601e8a796c38
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991 } |
601e8a796c38
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992 |
601e8a796c38
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993 int vixSetGrKeys(const vidix_grkey_t *grkey) |
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diff
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994 { |
601e8a796c38
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995 memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); |
4872 | 996 |
997 if(mach64_grkey.ckey.op == CKEY_TRUE) | |
998 { | |
999 besr.ckey_on=1; | |
1000 | |
1001 switch(mach64_vid_get_dbpp()) | |
1002 { | |
1003 case 15: | |
1004 besr.graphics_key_msk=0x7FFF; | |
1005 besr.graphics_key_clr= | |
1006 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
1007 | ((mach64_grkey.ckey.green&0xF8)<<2) | |
1008 | ((mach64_grkey.ckey.red &0xF8)<<7); | |
1009 break; | |
1010 case 16: | |
1011 besr.graphics_key_msk=0xFFFF; | |
1012 besr.graphics_key_clr= | |
1013 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
1014 | ((mach64_grkey.ckey.green&0xFC)<<3) | |
1015 | ((mach64_grkey.ckey.red &0xF8)<<8); | |
7836
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diff
changeset
|
1016 besr.graphics_key_clr=le2me_32(besr.graphics_key_clr); |
4872 | 1017 break; |
1018 case 24: | |
1019 besr.graphics_key_msk=0xFFFFFF; | |
1020 besr.graphics_key_clr= | |
1021 ((mach64_grkey.ckey.blue &0xFF)) | |
1022 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
1023 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1024 break; | |
1025 case 32: | |
1026 besr.graphics_key_msk=0xFFFFFF; | |
1027 besr.graphics_key_clr= | |
1028 ((mach64_grkey.ckey.blue &0xFF)) | |
1029 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
1030 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1031 break; | |
1032 default: | |
1033 besr.ckey_on=0; | |
1034 besr.graphics_key_msk=0; | |
1035 besr.graphics_key_clr=0; | |
1036 } | |
1037 } | |
1038 else | |
1039 { | |
1040 besr.ckey_on=0; | |
1041 besr.graphics_key_msk=0; | |
1042 besr.graphics_key_clr=0; | |
1043 } | |
1044 | |
1045 mach64_fifo_wait(4); | |
1046 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
1047 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1048 // OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); | |
1049 // OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); | |
1050 if(besr.ckey_on) | |
1051 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
1052 else | |
1053 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); | |
1054 | |
4861
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1055 return(0); |
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1056 } |