Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3253:48899ffdc4de
Minor improvements
author | nick |
---|---|
date | Sat, 01 Dec 2001 20:23:47 +0000 |
parents | e714f1e4ab27 |
children | 4ee5fc519e08 |
rev | line source |
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2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
2870 | 15 */ |
16 | |
3250 | 17 #define RADEON_VID_VERSION "1.0.1" |
2951 | 18 |
2870 | 19 /* |
20 It's entirely possible this major conflicts with something else | |
21 mknod /dev/radeon_vid c 178 0 | |
3164 | 22 or |
23 mknod /dev/rage128_vid c 178 0 | |
24 for Rage128/Rage128Pro chips (althrough it doesn't matter) | |
25 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
26 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
27 ----------------------------------------------------------- | |
2870 | 28 TODO: |
3164 | 29 Highest priority: fbvid.h compatibility |
30 High priority: RGB/BGR 2-32, YVU9, IF09 support | |
3122 | 31 Middle priority: |
32 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? | |
33 OV0_AUTO_FLIP_CNTL | |
34 OV0_FILTER_CNTL | |
35 OV0_VIDEO_KEY_CLR | |
36 OV0_KEY_CNTL | |
3164 | 37 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV |
3122 | 38 YUNV, YVYU, Y41P, Y211, Y41T, Y42T, V422, V655, CLJR |
39 ^^^^ | |
40 YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
2870 | 41 */ |
42 | |
43 #include <linux/config.h> | |
44 #include <linux/version.h> | |
45 #include <linux/module.h> | |
46 #include <linux/types.h> | |
47 #include <linux/kernel.h> | |
48 #include <linux/sched.h> | |
49 #include <linux/mm.h> | |
50 #include <linux/string.h> | |
51 #include <linux/errno.h> | |
52 #include <linux/slab.h> | |
53 #include <linux/pci.h> | |
54 #include <linux/ioport.h> | |
55 #include <linux/init.h> | |
56 | |
57 #include "radeon_vid.h" | |
58 #include "radeon.h" | |
59 | |
60 #ifdef CONFIG_MTRR | |
61 #include <asm/mtrr.h> | |
62 #endif | |
63 | |
64 #include <asm/uaccess.h> | |
65 #include <asm/system.h> | |
66 #include <asm/io.h> | |
67 | |
68 #define TRUE 1 | |
69 #define FALSE 0 | |
70 | |
71 #define RADEON_VID_MAJOR 178 | |
72 | |
73 | |
74 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
3198 | 75 #ifdef RAGE128 |
76 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
77 #else | |
78 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
79 #endif | |
2965 | 80 #ifdef MODULE_LICENSE |
2870 | 81 MODULE_LICENSE("GPL"); |
2965 | 82 #endif |
2870 | 83 |
3164 | 84 #ifdef RAGE128 |
85 #define RVID_MSG "rage128_vid: " | |
86 #define X_ADJUST 0 | |
87 #else | |
88 #define RVID_MSG "radeon_vid: " | |
89 #define X_ADJUST 8 | |
3198 | 90 #ifndef RADEON |
91 #define RADEON | |
92 #endif | |
3164 | 93 #endif |
94 | |
2870 | 95 typedef struct bes_registers_s |
96 { | |
97 /* base address of yuv framebuffer */ | |
98 uint32_t yuv_base; | |
99 uint32_t fourcc; | |
100 /* YUV BES registers */ | |
101 uint32_t reg_load_cntl; | |
102 uint32_t h_inc; | |
103 uint32_t step_by; | |
104 uint32_t y_x_start; | |
105 uint32_t y_x_end; | |
106 uint32_t v_inc; | |
107 uint32_t p1_blank_lines_at_top; | |
3019 | 108 uint32_t p23_blank_lines_at_top; |
2870 | 109 uint32_t vid_buf_pitch0_value; |
2944 | 110 uint32_t vid_buf_pitch1_value; |
2870 | 111 uint32_t p1_x_start_end; |
112 uint32_t p2_x_start_end; | |
113 uint32_t p3_x_start_end; | |
3122 | 114 uint32_t base_addr; |
2870 | 115 uint32_t vid_buf0_base_adrs; |
116 /* These ones are for auto flip: maybe in the future */ | |
117 uint32_t vid_buf1_base_adrs; | |
118 uint32_t vid_buf2_base_adrs; | |
119 uint32_t vid_buf3_base_adrs; | |
120 uint32_t vid_buf4_base_adrs; | |
121 uint32_t vid_buf5_base_adrs; | |
122 | |
123 uint32_t p1_v_accum_init; | |
124 uint32_t p1_h_accum_init; | |
3019 | 125 uint32_t p23_v_accum_init; |
2870 | 126 uint32_t p23_h_accum_init; |
127 uint32_t scale_cntl; | |
128 uint32_t exclusive_horz; | |
129 uint32_t auto_flip_cntl; | |
130 uint32_t filter_cntl; | |
3250 | 131 uint32_t graphics_key_msk; |
132 uint32_t key_cntl; | |
133 uint32_t test; | |
134 /* Configurable stuff */ | |
135 int double_buff; | |
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136 int brightness; |
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137 int saturation; |
2870 | 138 uint32_t graphics_key_clr; |
3250 | 139 int deinterlace_on; |
140 uint32_t deinterlace_pattern; | |
2870 | 141 } bes_registers_t; |
142 | |
143 typedef struct video_registers_s | |
144 { | |
145 uint32_t name; | |
146 uint32_t value; | |
147 }video_registers_t; | |
148 | |
149 static bes_registers_t besr; | |
150 static video_registers_t vregs[] = | |
151 { | |
152 { OV0_REG_LOAD_CNTL, 0 }, | |
153 { OV0_H_INC, 0 }, | |
154 { OV0_STEP_BY, 0 }, | |
155 { OV0_Y_X_START, 0 }, | |
156 { OV0_Y_X_END, 0 }, | |
157 { OV0_V_INC, 0 }, | |
158 { OV0_P1_BLANK_LINES_AT_TOP, 0 }, | |
3019 | 159 { OV0_P23_BLANK_LINES_AT_TOP, 0 }, |
2870 | 160 { OV0_VID_BUF_PITCH0_VALUE, 0 }, |
2944 | 161 { OV0_VID_BUF_PITCH1_VALUE, 0 }, |
2870 | 162 { OV0_P1_X_START_END, 0 }, |
163 { OV0_P2_X_START_END, 0 }, | |
164 { OV0_P3_X_START_END, 0 }, | |
3122 | 165 { OV0_BASE_ADDR, 0 }, |
2870 | 166 { OV0_VID_BUF0_BASE_ADRS, 0 }, |
167 { OV0_VID_BUF1_BASE_ADRS, 0 }, | |
168 { OV0_VID_BUF2_BASE_ADRS, 0 }, | |
169 { OV0_VID_BUF3_BASE_ADRS, 0 }, | |
170 { OV0_VID_BUF4_BASE_ADRS, 0 }, | |
171 { OV0_VID_BUF5_BASE_ADRS, 0 }, | |
172 { OV0_P1_V_ACCUM_INIT, 0 }, | |
173 { OV0_P1_H_ACCUM_INIT, 0 }, | |
3019 | 174 { OV0_P23_V_ACCUM_INIT, 0 }, |
2870 | 175 { OV0_P23_H_ACCUM_INIT, 0 }, |
176 { OV0_SCALE_CNTL, 0 }, | |
177 { OV0_EXCLUSIVE_HORZ, 0 }, | |
178 { OV0_AUTO_FLIP_CNTL, 0 }, | |
179 { OV0_FILTER_CNTL, 0 }, | |
180 { OV0_COLOUR_CNTL, 0 }, | |
181 { OV0_GRAPHICS_KEY_MSK, 0 }, | |
182 { OV0_GRAPHICS_KEY_CLR, 0 }, | |
183 { OV0_KEY_CNTL, 0 }, | |
184 { OV0_TEST, 0 } | |
185 }; | |
186 | |
187 static uint32_t radeon_vid_in_use = 0; | |
188 | |
189 static uint8_t *radeon_mmio_base = 0; | |
190 static uint32_t radeon_mem_base = 0; | |
3019 | 191 static int32_t radeon_overlay_off = 0; |
2870 | 192 static uint32_t radeon_ram_size = 0; |
193 | |
194 static mga_vid_config_t radeon_config; | |
195 | |
2951 | 196 #undef DEBUG |
2870 | 197 #if DEBUG |
198 #define RTRACE printk | |
199 #else | |
200 #define RTRACE(...) ((void)0) | |
201 #endif | |
202 | |
3122 | 203 static char *fourcc_format_name(int format) |
204 { | |
205 switch(format) | |
206 { | |
207 case IMGFMT_RGB8: return("RGB 8-bit"); | |
208 case IMGFMT_RGB15: return("RGB 15-bit"); | |
209 case IMGFMT_RGB16: return("RGB 16-bit"); | |
210 case IMGFMT_RGB24: return("RGB 24-bit"); | |
211 case IMGFMT_RGB32: return("RGB 32-bit"); | |
212 case IMGFMT_BGR8: return("BGR 8-bit"); | |
213 case IMGFMT_BGR15: return("BGR 15-bit"); | |
214 case IMGFMT_BGR16: return("BGR 16-bit"); | |
215 case IMGFMT_BGR24: return("BGR 24-bit"); | |
216 case IMGFMT_BGR32: return("BGR 32-bit"); | |
217 case IMGFMT_YVU9: return("Planar YVU9"); | |
218 case IMGFMT_IF09: return("Planar IF09"); | |
219 case IMGFMT_YV12: return("Planar YV12"); | |
220 case IMGFMT_I420: return("Planar I420"); | |
221 case IMGFMT_IYUV: return("Planar IYUV"); | |
222 case IMGFMT_CLPL: return("Planar CLPL"); | |
3198 | 223 case IMGFMT_Y800: return("Planar Y800"); |
224 case IMGFMT_Y8: return("Planar Y8"); | |
225 case IMGFMT_IUYV: return("Packed IUYV"); | |
226 case IMGFMT_IY41: return("Packed IY41"); | |
3122 | 227 case IMGFMT_IYU1: return("Packed IYU1"); |
228 case IMGFMT_IYU2: return("Packed IYU2"); | |
229 case IMGFMT_UYVY: return("Packed UYVY"); | |
230 case IMGFMT_UYNV: return("Packed UYNV"); | |
231 case IMGFMT_cyuv: return("Packed CYUV"); | |
3198 | 232 case IMGFMT_Y422: return("Packed Y422"); |
3122 | 233 case IMGFMT_YUY2: return("Packed YUY2"); |
234 case IMGFMT_YUNV: return("Packed YUNV"); | |
235 case IMGFMT_YVYU: return("Packed YVYU"); | |
236 case IMGFMT_Y41P: return("Packed Y41P"); | |
237 case IMGFMT_Y211: return("Packed Y211"); | |
238 case IMGFMT_Y41T: return("Packed Y41T"); | |
239 case IMGFMT_Y42T: return("Packed Y42T"); | |
240 case IMGFMT_V422: return("Packed V422"); | |
241 case IMGFMT_V655: return("Packed V655"); | |
242 case IMGFMT_CLJR: return("Packed CLJR"); | |
243 case IMGFMT_YUVP: return("Packed YUVP"); | |
244 case IMGFMT_UYVP: return("Packed UYVP"); | |
3198 | 245 case IMGFMT_MPEGPES: return("Mpeg PES"); |
3122 | 246 } |
247 return("Unknown"); | |
248 } | |
249 | |
2870 | 250 |
251 /* | |
252 * IO macros | |
253 */ | |
254 | |
255 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
256 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
257 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
258 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
259 | |
260 static void radeon_vid_save_state( void ) | |
261 { | |
262 size_t i; | |
263 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
264 vregs[i].value = INREG(vregs[i].name); | |
265 } | |
266 | |
267 static void radeon_vid_restore_state( void ) | |
268 { | |
269 size_t i; | |
270 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
271 OUTREG(vregs[i].name,vregs[i].value); | |
272 } | |
273 | |
274 static void radeon_vid_stop_video( void ) | |
275 { | |
276 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
277 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
278 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
279 OUTREG(OV0_FILTER_CNTL, 0x0000000f); | |
280 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
281 OUTREG(OV0_TEST, 0); | |
282 } | |
283 | |
284 static void radeon_vid_display_video( void ) | |
285 { | |
286 int bes_flags; | |
3164 | 287 RTRACE(RVID_MSG"OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
288 RTRACE(RVID_MSG"OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs); | |
289 RTRACE(RVID_MSG"OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 290 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
3164 | 291 RTRACE(RVID_MSG"OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n" |
2951 | 292 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end); |
3164 | 293 RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n" |
2951 | 294 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init); |
2870 | 295 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
296 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
2965 | 297 |
2870 | 298 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
299 | |
3250 | 300 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
2870 | 301 |
302 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
303 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2965 | 304 |
2870 | 305 OUTREG(OV0_H_INC, besr.h_inc); |
306 OUTREG(OV0_STEP_BY, besr.step_by); | |
307 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
308 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
309 OUTREG(OV0_V_INC, besr.v_inc); | |
310 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
3164 | 311 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
2870 | 312 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
2944 | 313 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 314 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
315 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
316 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
3198 | 317 #if 0 |
3122 | 318 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
319 #endif | |
2870 | 320 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
321 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
322 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
323 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
324 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
325 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
326 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
327 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
328 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
3164 | 329 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
2870 | 330 |
331 bes_flags = SCALER_ENABLE | | |
332 SCALER_SMART_SWITCH | | |
333 SCALER_HORZ_PICK_NEAREST; | |
3250 | 334 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; |
335 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
3198 | 336 #ifdef RAGE128 |
337 bes_flags |= SCALER_BURST_PER_PLANE; | |
338 #endif | |
2870 | 339 switch(besr.fourcc) |
340 { | |
341 case IMGFMT_RGB15: | |
342 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
343 case IMGFMT_RGB16: | |
344 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
345 case IMGFMT_RGB24: | |
346 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
347 case IMGFMT_RGB32: | |
348 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
3164 | 349 /* 4:1:0*/ |
350 case IMGFMT_IF09: | |
2870 | 351 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
3164 | 352 /* 4:2:0 */ |
3122 | 353 case IMGFMT_IYUV: |
2870 | 354 case IMGFMT_I420: |
3164 | 355 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
356 /* 4:2:2 */ | |
357 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
2870 | 358 case IMGFMT_YUY2: |
359 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
360 } | |
3164 | 361 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags); |
2870 | 362 OUTREG(OV0_SCALE_CNTL, bes_flags); |
363 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
364 } | |
365 | |
2951 | 366 #define XXX_SRC_X 0 |
367 #define XXX_SRC_Y 0 | |
2870 | 368 |
2944 | 369 #define XXX_WIDTH config->src_width |
370 #define XXX_HEIGHT config->src_height | |
2870 | 371 |
2951 | 372 #define XXX_DRW_W config->dest_width |
373 #define XXX_DRW_H config->dest_height | |
2925 | 374 |
2870 | 375 static int radeon_vid_init_video( mga_vid_config_t *config ) |
376 { | |
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377 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 378 int is_420; |
3164 | 379 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 380 ,(uint32_t)config->version |
2951 | 381 ,(uint32_t)config->format |
2870 | 382 ,(uint32_t)config->card_type |
383 ,(uint32_t)config->ram_size | |
384 ,(uint32_t)config->src_width | |
385 ,(uint32_t)config->src_height | |
386 ,(uint32_t)config->x_org | |
387 ,(uint32_t)config->y_org | |
388 ,(uint32_t)config->dest_width | |
389 ,(uint32_t)config->dest_height | |
390 ,(uint32_t)config->frame_size | |
391 ,(uint32_t)config->num_frames); | |
2917 | 392 radeon_vid_stop_video(); |
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393 left = XXX_SRC_X << 16; |
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394 top = XXX_SRC_Y << 16; |
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395 src_h = config->src_height; |
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396 src_w = config->src_width; |
2870 | 397 switch(config->format) |
398 { | |
399 case IMGFMT_RGB15: | |
400 case IMGFMT_BGR15: | |
401 case IMGFMT_RGB16: | |
402 case IMGFMT_BGR16: | |
403 case IMGFMT_RGB24: | |
404 case IMGFMT_BGR24: | |
405 case IMGFMT_RGB32: | |
406 case IMGFMT_BGR32: | |
3164 | 407 /* 4:1:0 */ |
408 case IMGFMT_IF09: | |
2870 | 409 case IMGFMT_YVU9: |
3164 | 410 /* 4:2:0 */ |
2870 | 411 case IMGFMT_IYUV: |
412 case IMGFMT_YV12: | |
413 case IMGFMT_I420: | |
3164 | 414 /* 4:2:2 */ |
415 case IMGFMT_UYVY: | |
2870 | 416 case IMGFMT_YUY2: |
417 break; | |
418 default: | |
3164 | 419 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
2870 | 420 return -1; |
421 } | |
3019 | 422 is_420 = 0; |
3122 | 423 if(config->format == IMGFMT_YV12 || |
424 config->format == IMGFMT_I420 || | |
425 config->format == IMGFMT_IYUV) is_420 = 1; | |
2951 | 426 switch(config->format) |
427 { | |
3164 | 428 /* 4:1:0 */ |
2951 | 429 case IMGFMT_YVU9: |
3164 | 430 case IMGFMT_IF09: |
431 /* 4:2:0 */ | |
2951 | 432 case IMGFMT_IYUV: |
3164 | 433 case IMGFMT_YV12: |
434 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
435 /* 4:2:2 */ | |
436 default: | |
2951 | 437 case IMGFMT_UYVY: |
438 case IMGFMT_YUY2: | |
439 case IMGFMT_RGB15: | |
440 case IMGFMT_BGR15: | |
441 case IMGFMT_RGB16: | |
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442 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 443 case IMGFMT_RGB24: |
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444 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 445 case IMGFMT_RGB32: |
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446 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 447 } |
448 | |
2870 | 449 besr.fourcc = config->format; |
450 | |
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451 besr.v_inc = (src_h << 20) / XXX_DRW_H; |
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452 h_inc = (src_w << 12) / XXX_DRW_W; |
2944 | 453 step_by = 1; |
2870 | 454 |
2944 | 455 while(h_inc >= (2 << 12)) { |
456 step_by++; | |
457 h_inc >>= 1; | |
2870 | 458 } |
459 | |
460 /* keep everything in 16.16 */ | |
3164 | 461 besr.base_addr = radeon_mem_base; |
3019 | 462 if(is_420) |
463 { | |
3164 | 464 uint32_t d1line,d2line,d3line; |
465 d1line = top*pitch; | |
466 d2line = src_h*pitch+(d1line>>1); | |
467 d3line = d2line+((src_h*pitch)>>2); | |
468 d1line += (left >> 16) & ~15; | |
469 d2line += (left >> 17) & ~15; | |
470 d3line += (left >> 17) & ~15; | |
471 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
472 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
473 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
474 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
475 { | |
476 uint32_t tmp; | |
477 tmp = besr.vid_buf1_base_adrs; | |
478 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
479 besr.vid_buf2_base_adrs = tmp; | |
480 } | |
3019 | 481 } |
482 else | |
483 { | |
484 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
3198 | 485 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; |
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486 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 487 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
488 } | |
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489 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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490 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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491 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 492 |
2951 | 493 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 494 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 495 ((tmp << 12) & 0xf0000000); |
2870 | 496 |
2951 | 497 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 498 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 499 ((tmp << 12) & 0x70000000); |
500 tmp = (top & 0x0000ffff) + 0x00018000; | |
3122 | 501 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
502 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
3019 | 503 |
504 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
3122 | 505 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
506 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
3019 | 507 |
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508 leftUV = (left >> 17) & 15; |
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509 left = (left >> 16) & 15; |
2944 | 510 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
511 besr.step_by = step_by | (step_by << 8); | |
3164 | 512 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
513 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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514 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
3122 | 515 if(is_420) |
516 { | |
517 src_h = (src_h + 1) >> 1; | |
518 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
519 } | |
520 else besr.p23_blank_lines_at_top = 0; | |
2870 | 521 besr.vid_buf_pitch0_value = pitch; |
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522 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
3164 | 523 RTRACE(RVID_MSG"BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
524 RTRACE(RVID_MSG"BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); | |
525 RTRACE(RVID_MSG"BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 526 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
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527 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
3164 | 528 src_w>>=1; |
529 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
530 besr.p3_x_start_end = besr.p2_x_start_end; | |
2870 | 531 return 0; |
532 } | |
533 | |
534 static void radeon_vid_frame_sel(int frame) | |
535 { | |
3066 | 536 uint32_t off0,off1,off2; |
3250 | 537 if(!besr.double_buff) return; |
3066 | 538 if(frame%2) |
539 { | |
540 off0 = besr.vid_buf3_base_adrs; | |
541 off1 = besr.vid_buf4_base_adrs; | |
542 off2 = besr.vid_buf5_base_adrs; | |
543 } | |
544 else | |
545 { | |
546 off0 = besr.vid_buf0_base_adrs; | |
547 off1 = besr.vid_buf1_base_adrs; | |
548 off2 = besr.vid_buf2_base_adrs; | |
549 } | |
2917 | 550 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
551 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 552 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
553 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
554 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 555 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 556 } |
557 | |
3250 | 558 static void radeon_vid_make_default(void) |
559 { | |
560 besr.deinterlace_pattern = 0x900AAAAA; | |
561 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
562 besr.deinterlace_on=1; | |
563 besr.double_buff=1; | |
564 } | |
565 | |
566 | |
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567 static void radeon_vid_preset(void) |
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568 { |
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569 unsigned tmp; |
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570 tmp = INREG(OV0_COLOUR_CNTL); |
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571 besr.saturation = (tmp>>8)&0x1f; |
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572 besr.brightness = tmp & 0x7f; |
3250 | 573 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); |
574 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); | |
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575 } |
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576 |
2951 | 577 static int video_on = 0; |
578 | |
2870 | 579 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
580 { | |
581 int frame; | |
582 | |
583 switch(cmd) | |
584 { | |
585 case MGA_VID_CONFIG: | |
586 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base); | |
587 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base); | |
3164 | 588 RTRACE(RVID_MSG"Received configuration\n"); |
2870 | 589 |
590 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
591 { | |
3164 | 592 printk(RVID_MSG"failed copy from userspace\n"); |
3019 | 593 return -EFAULT; |
2870 | 594 } |
595 if(radeon_config.version != MGA_VID_VERSION){ | |
3164 | 596 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
3019 | 597 return -EFAULT; |
2870 | 598 } |
599 | |
600 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
3164 | 601 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
3019 | 602 return -EFAULT; |
2870 | 603 } |
604 | |
605 if(radeon_config.num_frames<1 || radeon_config.num_frames>4){ | |
3164 | 606 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
3019 | 607 return -EFAULT; |
2870 | 608 } |
609 | |
610 radeon_config.card_type = 0; | |
611 radeon_config.ram_size = radeon_ram_size; | |
3019 | 612 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
613 radeon_overlay_off &= 0xffff0000; | |
614 if(radeon_overlay_off < 0){ | |
3164 | 615 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
3019 | 616 return -EFAULT; |
617 } | |
3164 | 618 RTRACE(RVID_MSG"using video overlay at offset %p\n",radeon_overlay_off); |
2870 | 619 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
620 { | |
3164 | 621 printk(RVID_MSG"failed copy to userspace\n"); |
3019 | 622 return -EFAULT; |
2870 | 623 } |
3164 | 624 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
2870 | 625 return radeon_vid_init_video(&radeon_config); |
626 break; | |
627 | |
628 case MGA_VID_ON: | |
3164 | 629 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
630 radeon_vid_display_video(); | |
2951 | 631 video_on = 1; |
2870 | 632 break; |
633 | |
634 case MGA_VID_OFF: | |
3164 | 635 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
2951 | 636 if(video_on) radeon_vid_stop_video(); |
637 video_on = 0; | |
2870 | 638 break; |
639 | |
640 case MGA_VID_FSEL: | |
641 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
642 { | |
3164 | 643 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
2870 | 644 return(-EFAULT); |
645 } | |
646 radeon_vid_frame_sel(frame); | |
647 break; | |
648 | |
649 default: | |
3164 | 650 printk(RVID_MSG"Invalid ioctl\n"); |
2870 | 651 return (-EINVAL); |
652 } | |
653 | |
654 return 0; | |
655 } | |
656 | |
657 struct ati_card_id_s | |
658 { | |
3164 | 659 const int id; |
660 const char name[17]; | |
661 }; | |
662 | |
663 const struct ati_card_id_s ati_card_ids[]= | |
2870 | 664 { |
3164 | 665 #ifdef RAGE128 |
666 /* | |
667 This driver should be compatible with Rage128 (pro) chips. | |
668 (include adaptive deinterlacing!!!). | |
669 Moreover: the same logic can be used with Mach64 chips. | |
670 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
671 but they are incompatible by i/o ports. So if enthusiasts will want | |
672 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
673 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
674 fourccs (422 and 420 formats only). | |
675 */ | |
676 /* Rage128 Pro GL */ | |
677 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
678 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
679 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
680 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
681 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
682 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
683 /* Rage128 Pro VR */ | |
684 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
685 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
686 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
687 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
688 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
689 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
690 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
691 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
692 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
693 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
694 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
695 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
696 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
697 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
698 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
699 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
700 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
701 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
702 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
703 /* Rage128 GL */ | |
704 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
705 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
706 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
707 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
708 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
709 /* Rage128 VR */ | |
710 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
711 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
712 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
713 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
714 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
715 /* Rage128 M3 */ | |
3198 | 716 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, |
717 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
3164 | 718 /* Rage128 Pro Ultra */ |
3198 | 719 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, |
720 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
721 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
3164 | 722 #else |
723 /* Radeons (indeed: Rage 256 Pro ;) */ | |
2870 | 724 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
725 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
726 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
727 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
728 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
729 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
730 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
731 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
732 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
733 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
734 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
3164 | 735 #endif |
2870 | 736 }; |
737 | |
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738 static int detected_chip; |
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739 |
2870 | 740 static int radeon_vid_config_card(void) |
741 { | |
742 struct pci_dev *dev = NULL; | |
743 size_t i; | |
744 | |
745 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
746 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
747 break; | |
3122 | 748 if(!dev) |
2870 | 749 { |
3164 | 750 printk(RVID_MSG"No supported cards found\n"); |
2870 | 751 return FALSE; |
752 } | |
753 | |
754 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
755 radeon_mem_base = dev->resource[0].start; | |
756 | |
3164 | 757 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
758 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
2870 | 759 |
3122 | 760 /* video memory size */ |
761 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
762 | |
3164 | 763 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
3122 | 764 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
765 radeon_ram_size /= 0x100000; | |
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766 detected_chip = i; |
3164 | 767 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
2870 | 768 |
769 return TRUE; | |
770 } | |
771 | |
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772 #define PARAM_BRIGHTNESS "brightness=" |
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773 #define PARAM_SATURATION "saturation=" |
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774 #define PARAM_DOUBLE_BUFF "double_buff=" |
3250 | 775 #define PARAM_COLOUR_KEY "colour_key=" |
776 #define PARAM_DEINTERLACE "deinterlace=" | |
777 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" | |
2870 | 778 |
779 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
780 { | |
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781 unsigned len,saturation; |
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782 long brightness; |
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783 brightness = besr.brightness; |
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784 saturation = besr.saturation; |
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785 len = 0; |
3252 | 786 len += sprintf(&buf[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); |
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787 len += sprintf(&buf[len],"Chip: %s\n",ati_card_ids[detected_chip].name); |
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788 len += sprintf(&buf[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000); |
3252 | 789 len += sprintf(&buf[len],"MMIO: %p\n",radeon_mmio_base); |
790 len += sprintf(&buf[len],"Overlay offset: %p\n",radeon_overlay_off); | |
791 len += sprintf(&buf[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); | |
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792 len += sprintf(&buf[len],"Configurable stuff:\n"); |
3250 | 793 len += sprintf(&buf[len],"~~~~~~~~~~~~~~~~~~~\n"); |
794 len += sprintf(&buf[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); | |
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795 len += sprintf(&buf[len],PARAM_BRIGHTNESS"%i\n",brightness); |
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796 len += sprintf(&buf[len],PARAM_SATURATION"%u\n",saturation); |
3250 | 797 len += sprintf(&buf[len],PARAM_COLOUR_KEY"%X\n",besr.graphics_key_clr); |
798 len += sprintf(&buf[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); | |
799 len += sprintf(&buf[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); | |
3253 | 800 ppos += len; |
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801 return len; |
2870 | 802 } |
803 | |
804 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
805 { | |
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806 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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807 { |
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808 long brightness; |
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809 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
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810 if(brightness >= -64 && brightness <= 63) |
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811 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | |
3250 | 812 (besr.saturation << 8) | |
813 (besr.saturation << 16)); | |
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814 } |
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815 else |
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816 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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817 { |
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818 long saturation; |
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819 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); |
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820 if(saturation >= 0 && saturation <= 31) |
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821 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
3250 | 822 (saturation << 8) | |
823 (saturation << 16)); | |
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824 } |
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825 else |
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826 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) |
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827 { |
3250 | 828 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; |
829 else besr.double_buff = 0; | |
830 } | |
831 else | |
832 if(memcmp(buf,PARAM_COLOUR_KEY,min(count,strlen(PARAM_COLOUR_KEY))) == 0) | |
833 { | |
834 long ckey; | |
835 ckey=simple_strtol(&buf[strlen(PARAM_COLOUR_KEY)],NULL,16); | |
836 OUTREG(OV0_GRAPHICS_KEY_CLR, ckey); | |
837 } | |
838 else | |
839 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) | |
840 { | |
841 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; | |
842 else besr.deinterlace_on = 0; | |
843 } | |
844 else | |
845 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) | |
846 { | |
847 long dpat; | |
848 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); | |
849 OUTREG(OV0_DEINTERLACE_PATTERN, dpat); | |
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850 } |
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851 radeon_vid_preset(); |
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852 return count; |
2870 | 853 } |
854 | |
855 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
856 { | |
857 | |
3164 | 858 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
3019 | 859 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 860 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
861 { | |
3164 | 862 printk(RVID_MSG"error mapping video memory\n"); |
2870 | 863 return(-EAGAIN); |
864 } | |
865 | |
866 return(0); | |
867 } | |
868 | |
869 static int radeon_vid_release(struct inode *inode, struct file *file) | |
870 { | |
871 radeon_vid_in_use = 0; | |
872 radeon_vid_stop_video(); | |
873 | |
874 MOD_DEC_USE_COUNT; | |
875 return 0; | |
876 } | |
877 | |
878 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
879 { | |
880 return -ESPIPE; | |
881 } | |
882 | |
883 static int radeon_vid_open(struct inode *inode, struct file *file) | |
884 { | |
885 int minor = MINOR(inode->i_rdev); | |
886 | |
887 if(minor != 0) | |
888 return(-ENXIO); | |
889 | |
890 if(radeon_vid_in_use == 1) | |
891 return(-EBUSY); | |
892 | |
893 radeon_vid_in_use = 1; | |
894 MOD_INC_USE_COUNT; | |
895 return(0); | |
896 } | |
897 | |
898 #if LINUX_VERSION_CODE >= 0x020400 | |
899 static struct file_operations radeon_vid_fops = | |
900 { | |
901 llseek: radeon_vid_lseek, | |
902 read: radeon_vid_read, | |
903 write: radeon_vid_write, | |
904 ioctl: radeon_vid_ioctl, | |
905 mmap: radeon_vid_mmap, | |
906 open: radeon_vid_open, | |
907 release: radeon_vid_release | |
908 }; | |
909 #else | |
910 static struct file_operations radeon_vid_fops = | |
911 { | |
912 radeon_vid_lseek, | |
913 radeon_vid_read, | |
914 radeon_vid_write, | |
915 NULL, | |
916 NULL, | |
917 radeon_vid_ioctl, | |
918 radeon_vid_mmap, | |
919 radeon_vid_open, | |
920 NULL, | |
921 radeon_vid_release | |
922 }; | |
923 #endif | |
924 | |
925 /* | |
926 * Main Initialization Function | |
927 */ | |
928 | |
929 | |
930 static int radeon_vid_initialize(void) | |
931 { | |
932 radeon_vid_in_use = 0; | |
3164 | 933 #ifdef RAGE128 |
934 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
935 #else | |
936 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
937 #endif | |
2870 | 938 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
939 { | |
3164 | 940 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
2870 | 941 return -EIO; |
942 } | |
943 | |
944 if (!radeon_vid_config_card()) | |
945 { | |
3164 | 946 printk(RVID_MSG"can't configure this card\n"); |
2870 | 947 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
948 return -EINVAL; | |
949 } | |
950 radeon_vid_save_state(); | |
3250 | 951 radeon_vid_make_default(); |
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952 radeon_vid_preset(); |
2870 | 953 return(0); |
954 } | |
955 | |
956 int init_module(void) | |
957 { | |
958 return radeon_vid_initialize(); | |
959 } | |
960 | |
961 void cleanup_module(void) | |
962 { | |
963 radeon_vid_restore_state(); | |
964 if(radeon_mmio_base) | |
965 iounmap(radeon_mmio_base); | |
966 | |
3164 | 967 RTRACE(RVID_MSG"Cleaning up module\n"); |
2870 | 968 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
969 } | |
970 |