Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 8859:fd13e4c4f323
Set is_shift_required according to RadeonFamily
rather than device_id (thanks to Marcus Blomenkamp for this idea)
Also give RV200 a seperate family from R200 as they aren't really the same.
patch by James Stembridge <jstembridge@gmx.net>
author | arpi |
---|---|
date | Thu, 09 Jan 2003 18:28:56 +0000 |
parents | a6fc826a2b98 |
children | 026ed72206ba |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
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6 PPC support by Alex Beregszaszi |
3996 | 7 */ |
8 | |
9 #include <errno.h> | |
10 #include <stdio.h> | |
11 #include <stdlib.h> | |
12 #include <string.h> | |
13 #include <math.h> | |
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14 #include <inttypes.h> |
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15 |
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16 #include "../../config.h" |
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17 #include "../../bswap.h" |
4201 | 18 #include "../../libdha/pci_ids.h" |
19 #include "../../libdha/pci_names.h" | |
3996 | 20 #include "../vidix.h" |
21 #include "../fourcc.h" | |
22 #include "../../libdha/libdha.h" | |
23 #include "radeon.h" | |
24 | |
25 #ifdef RAGE128 | |
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26 #define RADEON_MSG "[rage128]" |
3996 | 27 #define X_ADJUST 0 |
28 #else | |
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29 #define RADEON_MSG "[radeon]" |
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30 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 31 #ifndef RADEON |
32 #define RADEON | |
33 #endif | |
34 #endif | |
35 | |
4030 | 36 static int __verbose = 0; |
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37 #ifdef RADEON |
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38 static int rage_ckey_model=0; |
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39 static int is_shift_required = 0; |
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40 #endif |
4015 | 41 |
3996 | 42 typedef struct bes_registers_s |
43 { | |
44 /* base address of yuv framebuffer */ | |
45 uint32_t yuv_base; | |
46 uint32_t fourcc; | |
47 uint32_t dest_bpp; | |
48 /* YUV BES registers */ | |
49 uint32_t reg_load_cntl; | |
50 uint32_t h_inc; | |
51 uint32_t step_by; | |
52 uint32_t y_x_start; | |
53 uint32_t y_x_end; | |
54 uint32_t v_inc; | |
55 uint32_t p1_blank_lines_at_top; | |
56 uint32_t p23_blank_lines_at_top; | |
57 uint32_t vid_buf_pitch0_value; | |
58 uint32_t vid_buf_pitch1_value; | |
59 uint32_t p1_x_start_end; | |
60 uint32_t p2_x_start_end; | |
61 uint32_t p3_x_start_end; | |
62 uint32_t base_addr; | |
4930 | 63 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
64 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
65 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
66 uint32_t vid_nbufs; | |
3996 | 67 |
68 uint32_t p1_v_accum_init; | |
69 uint32_t p1_h_accum_init; | |
70 uint32_t p23_v_accum_init; | |
71 uint32_t p23_h_accum_init; | |
72 uint32_t scale_cntl; | |
73 uint32_t exclusive_horz; | |
74 uint32_t auto_flip_cntl; | |
75 uint32_t filter_cntl; | |
76 uint32_t key_cntl; | |
77 uint32_t test; | |
78 /* Configurable stuff */ | |
79 int double_buff; | |
80 | |
81 int brightness; | |
82 int saturation; | |
83 | |
84 int ckey_on; | |
85 uint32_t graphics_key_clr; | |
86 uint32_t graphics_key_msk; | |
4869 | 87 uint32_t ckey_cntl; |
3996 | 88 |
89 int deinterlace_on; | |
90 uint32_t deinterlace_pattern; | |
91 | |
92 } bes_registers_t; | |
93 | |
94 typedef struct video_registers_s | |
95 { | |
96 const char * sname; | |
97 uint32_t name; | |
98 uint32_t value; | |
99 }video_registers_t; | |
100 | |
101 static bes_registers_t besr; | |
102 #ifndef RAGE128 | |
8855 | 103 static int RadeonFamily=100; |
3996 | 104 #endif |
105 #define DECLARE_VREG(name) { #name, name, 0 } | |
106 static video_registers_t vregs[] = | |
107 { | |
108 DECLARE_VREG(VIDEOMUX_CNTL), | |
109 DECLARE_VREG(VIPPAD_MASK), | |
110 DECLARE_VREG(VIPPAD1_A), | |
111 DECLARE_VREG(VIPPAD1_EN), | |
112 DECLARE_VREG(VIPPAD1_Y), | |
113 DECLARE_VREG(OV0_Y_X_START), | |
114 DECLARE_VREG(OV0_Y_X_END), | |
115 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
116 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
117 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
118 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
119 DECLARE_VREG(OV0_SCALE_CNTL), | |
120 DECLARE_VREG(OV0_V_INC), | |
121 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
122 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
123 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
124 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
125 #ifdef RADEON | |
126 DECLARE_VREG(OV0_BASE_ADDR), | |
127 #endif | |
128 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
129 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
130 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
131 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
132 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
133 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
134 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
135 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
136 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
137 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
138 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
139 DECLARE_VREG(OV0_H_INC), | |
140 DECLARE_VREG(OV0_STEP_BY), | |
141 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
142 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
143 DECLARE_VREG(OV0_P1_X_START_END), | |
144 DECLARE_VREG(OV0_P2_X_START_END), | |
145 DECLARE_VREG(OV0_P3_X_START_END), | |
146 DECLARE_VREG(OV0_FILTER_CNTL), | |
147 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
148 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
149 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
150 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
151 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
152 DECLARE_VREG(OV0_FLAG_CNTL), | |
153 #ifdef RAGE128 | |
154 DECLARE_VREG(OV0_COLOUR_CNTL), | |
155 #else | |
156 DECLARE_VREG(OV0_SLICE_CNTL), | |
157 #endif | |
158 DECLARE_VREG(OV0_VID_KEY_CLR), | |
159 DECLARE_VREG(OV0_VID_KEY_MSK), | |
160 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
161 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
162 DECLARE_VREG(OV0_KEY_CNTL), | |
163 DECLARE_VREG(OV0_TEST), | |
164 DECLARE_VREG(OV0_LIN_TRANS_A), | |
165 DECLARE_VREG(OV0_LIN_TRANS_B), | |
166 DECLARE_VREG(OV0_LIN_TRANS_C), | |
167 DECLARE_VREG(OV0_LIN_TRANS_D), | |
168 DECLARE_VREG(OV0_LIN_TRANS_E), | |
169 DECLARE_VREG(OV0_LIN_TRANS_F), | |
170 DECLARE_VREG(OV0_GAMMA_0_F), | |
171 DECLARE_VREG(OV0_GAMMA_10_1F), | |
172 DECLARE_VREG(OV0_GAMMA_20_3F), | |
173 DECLARE_VREG(OV0_GAMMA_40_7F), | |
174 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
175 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
176 DECLARE_VREG(SUBPIC_CNTL), | |
177 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
178 DECLARE_VREG(SUBPIC_Y_X_START), | |
179 DECLARE_VREG(SUBPIC_Y_X_END), | |
180 DECLARE_VREG(SUBPIC_V_INC), | |
181 DECLARE_VREG(SUBPIC_H_INC), | |
182 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
183 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
184 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
185 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
186 DECLARE_VREG(SUBPIC_PITCH), | |
187 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
188 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
189 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
190 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
191 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
192 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
193 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
194 DECLARE_VREG(IDCT_RUNS), | |
195 DECLARE_VREG(IDCT_LEVELS), | |
196 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
197 DECLARE_VREG(IDCT_AUTH), | |
198 DECLARE_VREG(IDCT_CONTROL) | |
199 }; | |
4030 | 200 |
3996 | 201 static void * radeon_mmio_base = 0; |
202 static void * radeon_mem_base = 0; | |
203 static int32_t radeon_overlay_off = 0; | |
204 static uint32_t radeon_ram_size = 0; | |
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205 /* Restore on exit */ |
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206 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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207 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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208 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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209 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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210 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
3996 | 211 |
4012 | 212 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
213 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
214 | |
215 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
216 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
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217 |
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218 static inline uint32_t INREG (uint32_t addr) { |
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219 uint32_t tmp = GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr); |
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220 return le2me_32(tmp); |
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221 } |
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222 //#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) |
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223 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,le2me_32(val)) |
3996 | 224 #define OUTREGP(addr,val,mask) \ |
225 do { \ | |
226 unsigned int _tmp = INREG(addr); \ | |
227 _tmp &= (mask); \ | |
228 _tmp |= (val); \ | |
229 OUTREG(addr, _tmp); \ | |
230 } while (0) | |
231 | |
4666 | 232 static __inline__ uint32_t INPLL(uint32_t addr) |
233 { | |
234 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
235 return (INREG(CLOCK_CNTL_DATA)); | |
236 } | |
237 | |
238 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
239 OUTREG(CLOCK_CNTL_DATA, val) | |
240 #define OUTPLLP(addr,val,mask) \ | |
241 do { \ | |
242 unsigned int _tmp = INPLL(addr); \ | |
243 _tmp &= (mask); \ | |
244 _tmp |= (val); \ | |
245 OUTPLL(addr, _tmp); \ | |
246 } while (0) | |
247 | |
3996 | 248 static uint32_t radeon_vid_get_dbpp( void ) |
249 { | |
250 uint32_t dbpp,retval; | |
251 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
252 switch(dbpp) | |
253 { | |
254 case DST_8BPP: retval = 8; break; | |
255 case DST_15BPP: retval = 15; break; | |
256 case DST_16BPP: retval = 16; break; | |
257 case DST_24BPP: retval = 24; break; | |
258 default: retval=32; break; | |
259 } | |
260 return retval; | |
261 } | |
262 | |
263 static int radeon_is_dbl_scan( void ) | |
264 { | |
265 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
266 } | |
267 | |
268 static int radeon_is_interlace( void ) | |
269 { | |
270 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
271 } | |
272 | |
4666 | 273 static uint32_t radeon_get_xres( void ) |
274 { | |
275 /* FIXME: currently we extract that from CRTC!!!*/ | |
276 uint32_t xres,h_total; | |
277 h_total = INREG(CRTC_H_TOTAL_DISP); | |
278 xres = (h_total >> 16) & 0xffff; | |
279 return (xres + 1)*8; | |
280 } | |
281 | |
282 static uint32_t radeon_get_yres( void ) | |
283 { | |
284 /* FIXME: currently we extract that from CRTC!!!*/ | |
285 uint32_t yres,v_total; | |
286 v_total = INREG(CRTC_V_TOTAL_DISP); | |
287 yres = (v_total >> 16) & 0xffff; | |
288 return yres + 1; | |
289 } | |
290 | |
4689 | 291 static void radeon_wait_vsync(void) |
292 { | |
293 int i; | |
294 | |
295 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
296 for (i = 0; i < 2000000; i++) | |
297 { | |
298 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
299 } | |
300 } | |
301 | |
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302 #ifdef RAGE128 |
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303 static void _radeon_engine_idle(void); |
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304 static void _radeon_fifo_wait(unsigned); |
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305 #define radeon_engine_idle() _radeon_engine_idle() |
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306 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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307 /* Flush all dirty data in the Pixel Cache to memory. */ |
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308 static __inline__ void radeon_engine_flush ( void ) |
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309 { |
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310 unsigned i; |
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311 |
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312 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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313 for (i = 0; i < 2000000; i++) { |
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314 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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315 } |
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316 } |
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317 |
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318 /* Reset graphics card to known state. */ |
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319 static void radeon_engine_reset( void ) |
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320 { |
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321 uint32_t clock_cntl_index; |
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322 uint32_t mclk_cntl; |
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323 uint32_t gen_reset_cntl; |
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324 |
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325 radeon_engine_flush(); |
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326 |
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327 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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328 mclk_cntl = INPLL(MCLK_CNTL); |
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329 |
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330 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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331 |
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332 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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333 |
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334 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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335 INREG(GEN_RESET_CNTL); |
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336 OUTREG(GEN_RESET_CNTL, |
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337 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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338 INREG(GEN_RESET_CNTL); |
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339 |
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340 OUTPLL(MCLK_CNTL, mclk_cntl); |
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341 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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342 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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343 } |
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344 #else |
4689 | 345 |
3996 | 346 static __inline__ void radeon_engine_flush ( void ) |
347 { | |
348 int i; | |
349 | |
350 /* initiate flush */ | |
351 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
352 ~RB2D_DC_FLUSH_ALL); | |
353 | |
354 for (i=0; i < 2000000; i++) { | |
355 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
356 break; | |
357 } | |
358 } | |
359 | |
4666 | 360 static void _radeon_engine_idle(void); |
361 static void _radeon_fifo_wait(unsigned); | |
362 #define radeon_engine_idle() _radeon_engine_idle() | |
363 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 364 |
4666 | 365 static void radeon_engine_reset( void ) |
3996 | 366 { |
4666 | 367 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
368 | |
369 radeon_engine_flush (); | |
370 | |
371 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
372 mclk_cntl = INPLL(MCLK_CNTL); | |
373 | |
374 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
375 FORCEON_MCLKA | | |
376 FORCEON_MCLKB | | |
377 FORCEON_YCLKA | | |
378 FORCEON_YCLKB | | |
379 FORCEON_MC | | |
380 FORCEON_AIC)); | |
381 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 382 |
4666 | 383 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
384 SOFT_RESET_CP | | |
385 SOFT_RESET_HI | | |
386 SOFT_RESET_SE | | |
387 SOFT_RESET_RE | | |
388 SOFT_RESET_PP | | |
389 SOFT_RESET_E2 | | |
390 SOFT_RESET_RB | | |
391 SOFT_RESET_HDP); | |
392 INREG(RBBM_SOFT_RESET); | |
393 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
394 ~(SOFT_RESET_CP | | |
395 SOFT_RESET_HI | | |
396 SOFT_RESET_SE | | |
397 SOFT_RESET_RE | | |
398 SOFT_RESET_PP | | |
399 SOFT_RESET_E2 | | |
400 SOFT_RESET_RB | | |
401 SOFT_RESET_HDP)); | |
402 INREG(RBBM_SOFT_RESET); | |
403 | |
404 OUTPLL(MCLK_CNTL, mclk_cntl); | |
405 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
406 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
407 | |
408 return; | |
3996 | 409 } |
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410 #endif |
4666 | 411 static void radeon_engine_restore( void ) |
3996 | 412 { |
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413 #ifndef RAGE128 |
4666 | 414 int pitch64; |
415 uint32_t xres,yres,bpp; | |
416 radeon_fifo_wait(1); | |
417 xres = radeon_get_xres(); | |
418 yres = radeon_get_yres(); | |
419 bpp = radeon_vid_get_dbpp(); | |
420 /* turn of all automatic flushing - we'll do it all */ | |
421 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
422 | |
423 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
424 | |
425 radeon_fifo_wait(1); | |
426 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
427 (pitch64 << 22)); | |
428 | |
429 radeon_fifo_wait(1); | |
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430 //#if defined(__BIG_ENDIAN) |
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431 #if defined(WORDS_BIGENDIAN) |
4666 | 432 OUTREGP(DP_DATATYPE, |
433 HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
434 #else | |
435 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
436 #endif | |
437 | |
438 radeon_fifo_wait(1); | |
439 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
440 | DEFAULT_SC_BOTTOM_MAX)); | |
441 radeon_fifo_wait(1); | |
442 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
443 | GMC_BRUSH_SOLID_COLOR | |
444 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 445 |
4666 | 446 radeon_fifo_wait(7); |
447 OUTREG(DST_LINE_START, 0); | |
448 OUTREG(DST_LINE_END, 0); | |
449 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
450 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
451 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
452 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
453 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
454 | |
455 radeon_engine_idle(); | |
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456 #endif |
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457 } |
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458 #ifdef RAGE128 |
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459 static void _radeon_fifo_wait (unsigned entries) |
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460 { |
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461 unsigned i; |
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462 |
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463 for(;;) |
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464 { |
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465 for (i=0; i<2000000; i++) |
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466 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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467 return; |
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468 radeon_engine_reset(); |
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469 radeon_engine_restore(); |
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470 } |
4666 | 471 } |
472 | |
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473 static void _radeon_engine_idle ( void ) |
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474 { |
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475 unsigned i; |
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476 |
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477 /* ensure FIFO is empty before waiting for idle */ |
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478 radeon_fifo_wait (64); |
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479 for(;;) |
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480 { |
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481 for (i=0; i<2000000; i++) { |
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482 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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483 radeon_engine_flush (); |
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484 return; |
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485 } |
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486 } |
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487 radeon_engine_reset(); |
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488 radeon_engine_restore(); |
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489 } |
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490 } |
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491 #else |
4666 | 492 static void _radeon_fifo_wait (unsigned entries) |
493 { | |
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494 unsigned i; |
3996 | 495 |
4666 | 496 for(;;) |
497 { | |
498 for (i=0; i<2000000; i++) | |
499 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
500 return; | |
501 radeon_engine_reset(); | |
502 radeon_engine_restore(); | |
503 } | |
504 } | |
505 static void _radeon_engine_idle ( void ) | |
506 { | |
507 int i; | |
508 | |
509 /* ensure FIFO is empty before waiting for idle */ | |
510 radeon_fifo_wait (64); | |
511 for(;;) | |
512 { | |
3996 | 513 for (i=0; i<2000000; i++) { |
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514 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 515 radeon_engine_flush (); |
516 return; | |
517 } | |
518 } | |
4666 | 519 radeon_engine_reset(); |
520 radeon_engine_restore(); | |
521 } | |
3996 | 522 } |
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523 #endif |
3996 | 524 |
525 #ifndef RAGE128 | |
526 /* Reference color space transform data */ | |
527 typedef struct tagREF_TRANSFORM | |
528 { | |
529 float RefLuma; | |
530 float RefRCb; | |
531 float RefRCr; | |
532 float RefGCb; | |
533 float RefGCr; | |
534 float RefBCb; | |
535 float RefBCr; | |
536 } REF_TRANSFORM; | |
537 | |
538 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
539 REF_TRANSFORM trans[2] = | |
540 { | |
541 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
542 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
543 }; | |
544 /**************************************************************************** | |
545 * SetTransform * | |
546 * Function: Calculates and sets color space transform from supplied * | |
547 * reference transform, gamma, brightness, contrast, hue and * | |
548 * saturation. * | |
549 * Inputs: bright - brightness * | |
550 * cont - contrast * | |
551 * sat - saturation * | |
552 * hue - hue * | |
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553 * red_intensity - intense of red component * |
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554 * green_intensity - intense of green component * |
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555 * blue_intensity - intense of blue component * |
3996 | 556 * ref - index to the table of refernce transforms * |
557 * Outputs: NONE * | |
558 ****************************************************************************/ | |
559 | |
560 static void radeon_set_transform(float bright, float cont, float sat, | |
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561 float hue, float red_intensity, |
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562 float green_intensity,float blue_intensity, |
4284 | 563 unsigned ref) |
3996 | 564 { |
565 float OvHueSin, OvHueCos; | |
566 float CAdjLuma, CAdjOff; | |
4284 | 567 float RedAdj,GreenAdj,BlueAdj; |
3996 | 568 float CAdjRCb, CAdjRCr; |
569 float CAdjGCb, CAdjGCr; | |
570 float CAdjBCb, CAdjBCr; | |
571 float OvLuma, OvROff, OvGOff, OvBOff; | |
572 float OvRCb, OvRCr; | |
573 float OvGCb, OvGCr; | |
574 float OvBCb, OvBCr; | |
575 float Loff = 64.0; | |
576 float Coff = 512.0f; | |
577 | |
578 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
579 uint32_t dwOvRCb, dwOvRCr; | |
580 uint32_t dwOvGCb, dwOvGCr; | |
581 uint32_t dwOvBCb, dwOvBCr; | |
582 | |
583 if (ref >= 2) return; | |
584 | |
585 OvHueSin = sin((double)hue); | |
586 OvHueCos = cos((double)hue); | |
587 | |
588 CAdjLuma = cont * trans[ref].RefLuma; | |
589 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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590 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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591 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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592 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 593 |
594 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
595 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
596 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
597 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
598 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
599 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
600 | |
601 #if 0 /* default constants */ | |
602 CAdjLuma = 1.16455078125; | |
603 | |
604 CAdjRCb = 0.0; | |
605 CAdjRCr = 1.59619140625; | |
606 CAdjGCb = -0.39111328125; | |
607 CAdjGCr = -0.8125; | |
608 CAdjBCb = 2.01708984375; | |
609 CAdjBCr = 0; | |
610 #endif | |
611 OvLuma = CAdjLuma; | |
612 OvRCb = CAdjRCb; | |
613 OvRCr = CAdjRCr; | |
614 OvGCb = CAdjGCb; | |
615 OvGCr = CAdjGCr; | |
616 OvBCb = CAdjBCb; | |
617 OvBCr = CAdjBCr; | |
4284 | 618 OvROff = RedAdj + CAdjOff - |
3996 | 619 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 620 OvGOff = GreenAdj + CAdjOff - |
3996 | 621 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 622 OvBOff = BlueAdj + CAdjOff - |
3996 | 623 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
624 #if 0 /* default constants */ | |
625 OvROff = -888.5; | |
626 OvGOff = 545; | |
627 OvBOff = -1104; | |
628 #endif | |
629 | |
630 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
631 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
632 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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633 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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634 as in Radeon is a lie */ |
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635 #if 0 |
8855 | 636 if(RadeonFamily == 100) |
3996 | 637 { |
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638 #endif |
3996 | 639 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
640 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
641 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
642 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
643 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
644 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
645 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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646 #if 0 |
3996 | 647 } |
648 else | |
649 { | |
650 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
651 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
652 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
653 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
654 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
655 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
656 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
657 } | |
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658 #endif |
3996 | 659 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
660 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
661 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
662 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
663 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
664 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
665 } | |
666 | |
667 /* Gamma curve definition */ | |
668 typedef struct | |
669 { | |
670 unsigned int gammaReg; | |
671 unsigned int gammaSlope; | |
672 unsigned int gammaOffset; | |
673 }GAMMA_SETTINGS; | |
674 | |
675 /* Recommended gamma curve parameters */ | |
676 GAMMA_SETTINGS r200_def_gamma[18] = | |
677 { | |
678 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
679 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
680 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
681 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
682 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
683 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
684 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
685 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
686 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
687 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
688 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
689 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
690 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
691 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
692 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
693 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
694 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
695 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
696 }; | |
697 | |
698 GAMMA_SETTINGS r100_def_gamma[6] = | |
699 { | |
700 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
701 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
702 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
703 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
704 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
705 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
706 }; | |
707 | |
708 static void make_default_gamma_correction( void ) | |
709 { | |
710 size_t i; | |
8855 | 711 if(RadeonFamily == 100) { |
3996 | 712 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
713 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
714 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
715 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
716 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
717 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
718 for(i=0; i<6; i++){ | |
719 OUTREG(r100_def_gamma[i].gammaReg, | |
720 (r100_def_gamma[i].gammaSlope<<16) | | |
721 r100_def_gamma[i].gammaOffset); | |
722 } | |
723 } | |
724 else{ | |
725 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
726 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
727 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
728 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
729 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
730 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
731 | |
732 /* Default Gamma, | |
733 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
734 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
735 for(i=0; i<18; i++){ | |
736 OUTREG(r200_def_gamma[i].gammaReg, | |
737 (r200_def_gamma[i].gammaSlope<<16) | | |
738 r200_def_gamma[i].gammaOffset); | |
739 } | |
740 } | |
741 } | |
742 #endif | |
743 | |
744 static void radeon_vid_make_default(void) | |
745 { | |
746 #ifdef RAGE128 | |
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747 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 748 #else |
749 make_default_gamma_correction(); | |
750 #endif | |
751 besr.deinterlace_pattern = 0x900AAAAA; | |
752 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
753 besr.deinterlace_on=1; | |
754 besr.double_buff=1; | |
4869 | 755 besr.ckey_on=0; |
756 besr.graphics_key_msk=0; | |
757 besr.graphics_key_clr=0; | |
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758 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 759 } |
760 | |
761 | |
762 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
763 | |
4107 | 764 static unsigned short ati_card_ids[] = |
3996 | 765 { |
766 #ifdef RAGE128 | |
767 /* | |
768 This driver should be compatible with Rage128 (pro) chips. | |
769 (include adaptive deinterlacing!!!). | |
770 Moreover: the same logic can be used with Mach64 chips. | |
771 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
772 but they are incompatible by i/o ports. So if enthusiasts will want | |
773 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
774 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
775 fourccs (422 and 420 formats only). | |
776 */ | |
777 /* Rage128 Pro GL */ | |
4107 | 778 DEVICE_ATI_RAGE_128_PA_PRO, |
779 DEVICE_ATI_RAGE_128_PB_PRO, | |
780 DEVICE_ATI_RAGE_128_PC_PRO, | |
781 DEVICE_ATI_RAGE_128_PD_PRO, | |
782 DEVICE_ATI_RAGE_128_PE_PRO, | |
783 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 784 /* Rage128 Pro VR */ |
4107 | 785 DEVICE_ATI_RAGE_128_PG_PRO, |
786 DEVICE_ATI_RAGE_128_PH_PRO, | |
787 DEVICE_ATI_RAGE_128_PI_PRO, | |
788 DEVICE_ATI_RAGE_128_PJ_PRO, | |
789 DEVICE_ATI_RAGE_128_PK_PRO, | |
790 DEVICE_ATI_RAGE_128_PL_PRO, | |
791 DEVICE_ATI_RAGE_128_PM_PRO, | |
792 DEVICE_ATI_RAGE_128_PN_PRO, | |
793 DEVICE_ATI_RAGE_128_PO_PRO, | |
794 DEVICE_ATI_RAGE_128_PP_PRO, | |
795 DEVICE_ATI_RAGE_128_PQ_PRO, | |
796 DEVICE_ATI_RAGE_128_PR_PRO, | |
797 DEVICE_ATI_RAGE_128_PS_PRO, | |
798 DEVICE_ATI_RAGE_128_PT_PRO, | |
799 DEVICE_ATI_RAGE_128_PU_PRO, | |
800 DEVICE_ATI_RAGE_128_PV_PRO, | |
801 DEVICE_ATI_RAGE_128_PW_PRO, | |
802 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 803 /* Rage128 GL */ |
4107 | 804 DEVICE_ATI_RAGE_128_RE_SG, |
805 DEVICE_ATI_RAGE_128_RF_SG, | |
806 DEVICE_ATI_RAGE_128_RG, | |
807 DEVICE_ATI_RAGE_128_RK_VR, | |
808 DEVICE_ATI_RAGE_128_RL_VR, | |
809 DEVICE_ATI_RAGE_128_SE_4X, | |
810 DEVICE_ATI_RAGE_128_SF_4X, | |
811 DEVICE_ATI_RAGE_128_SG_4X, | |
8854 | 812 DEVICE_ATI_RAGE_128_SH, |
4107 | 813 DEVICE_ATI_RAGE_128_SK_4X, |
814 DEVICE_ATI_RAGE_128_SL_4X, | |
815 DEVICE_ATI_RAGE_128_SM_4X, | |
8854 | 816 DEVICE_ATI_RAGE_128_4X, |
4107 | 817 DEVICE_ATI_RAGE_128_PRO, |
818 DEVICE_ATI_RAGE_128_PRO2, | |
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819 DEVICE_ATI_RAGE_128_PRO3, |
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820 /* these seem to be based on rage 128 instead of mach64 */ |
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821 DEVICE_ATI_RAGE_MOBILITY_M3, |
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822 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 823 #else |
824 /* Radeons (indeed: Rage 256 Pro ;) */ | |
8855 | 825 DEVICE_ATI_RADEON_R100_QD, |
826 DEVICE_ATI_RADEON_R100_QE, | |
827 DEVICE_ATI_RADEON_R100_QF, | |
828 DEVICE_ATI_RADEON_R100_QG, | |
829 DEVICE_ATI_RADEON_VE_QY, | |
830 DEVICE_ATI_RADEON_VE_QZ, | |
8854 | 831 DEVICE_ATI_RADEON_MOBILITY_M7, |
832 DEVICE_ATI_RADEON_MOBILITY_M72, | |
4107 | 833 DEVICE_ATI_RADEON_MOBILITY_M6, |
834 DEVICE_ATI_RADEON_MOBILITY_M62, | |
8855 | 835 DEVICE_ATI_RADEON_R200_BB, |
836 DEVICE_ATI_RADEON_R200_QH, | |
837 DEVICE_ATI_RADEON_R200_QI, | |
838 DEVICE_ATI_RADEON_R200_QJ, | |
839 DEVICE_ATI_RADEON_R200_QK, | |
8854 | 840 DEVICE_ATI_RADEON_R200_QL, |
8855 | 841 DEVICE_ATI_RADEON_R200_QH2, |
842 DEVICE_ATI_RADEON_R200_QI2, | |
843 DEVICE_ATI_RADEON_R200_QJ2, | |
844 DEVICE_ATI_RADEON_R200_QK2, | |
8854 | 845 DEVICE_ATI_RADEON_RV200_QW, |
8855 | 846 DEVICE_ATI_RADEON_RV200_QX, |
847 DEVICE_ATI_RADEON_R250_ID, | |
848 DEVICE_ATI_RADEON_R250_IE, | |
849 DEVICE_ATI_RADEON_R250_IF, | |
850 DEVICE_ATI_RADEON_R250_IG, | |
851 DEVICE_ATI_RADEON_R250_LD, | |
852 DEVICE_ATI_RADEON_R250_LE, | |
853 DEVICE_ATI_RADEON_R250_LF, | |
854 DEVICE_ATI_RADEON_R250_LG, | |
855 DEVICE_ATI_RADEON_R300_ND, | |
856 DEVICE_ATI_RADEON_R300_NE, | |
857 DEVICE_ATI_RADEON_R300_NF, | |
858 DEVICE_ATI_RADEON_R300_NG | |
3996 | 859 #endif |
860 }; | |
861 | |
862 static int find_chip(unsigned chip_id) | |
863 { | |
864 unsigned i; | |
4107 | 865 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 866 { |
4107 | 867 if(chip_id == ati_card_ids[i]) return i; |
3996 | 868 } |
869 return -1; | |
870 } | |
871 | |
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872 static pciinfo_t pci_info; |
3996 | 873 static int probed=0; |
874 | |
875 vidix_capability_t def_cap = | |
876 { | |
877 #ifdef RAGE128 | |
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878 "BES driver for Rage128 cards", |
3996 | 879 #else |
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880 "BES driver for Radeon cards", |
3996 | 881 #endif |
4327 | 882 "Nick Kurshev", |
3996 | 883 TYPE_OUTPUT | TYPE_FX, |
4191 | 884 { 0, 0, 0, 0 }, |
4282 | 885 2048, |
886 2048, | |
3996 | 887 4, |
888 4, | |
889 -1, | |
4264 | 890 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 891 VENDOR_ATI, |
3996 | 892 0, |
893 { 0, 0, 0, 0} | |
894 }; | |
895 | |
896 | |
4191 | 897 int vixProbe( int verbose,int force ) |
3996 | 898 { |
899 pciinfo_t lst[MAX_PCI_DEVICES]; | |
900 unsigned i,num_pci; | |
901 int err; | |
4030 | 902 __verbose = verbose; |
3996 | 903 err = pci_scan(lst,&num_pci); |
904 if(err) | |
905 { | |
906 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
907 return err; | |
908 } | |
909 else | |
910 { | |
911 err = ENXIO; | |
912 for(i=0;i<num_pci;i++) | |
913 { | |
4107 | 914 if(lst[i].vendor == VENDOR_ATI) |
3996 | 915 { |
916 int idx; | |
4191 | 917 const char *dname; |
3996 | 918 idx = find_chip(lst[i].device); |
4191 | 919 if(idx == -1 && force == PROBE_NORMAL) continue; |
920 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
921 dname = dname ? dname : "Unknown chip"; | |
922 printf(RADEON_MSG" Found chip: %s\n",dname); | |
3996 | 923 #ifndef RAGE128 |
4191 | 924 if(idx != -1) |
8855 | 925 { |
926 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_R100_QD || | |
927 ati_card_ids[idx] == DEVICE_ATI_RADEON_R100_QE || | |
928 ati_card_ids[idx] == DEVICE_ATI_RADEON_R100_QF || | |
929 ati_card_ids[idx] == DEVICE_ATI_RADEON_R100_QG || | |
930 ati_card_ids[idx] == DEVICE_ATI_RADEON_VE_QY || | |
931 ati_card_ids[idx] == DEVICE_ATI_RADEON_VE_QZ || | |
932 ati_card_ids[idx] == DEVICE_ATI_RADEON_MOBILITY_M7|| | |
933 ati_card_ids[idx] == DEVICE_ATI_RADEON_MOBILITY_M72|| | |
934 ati_card_ids[idx] == DEVICE_ATI_RADEON_MOBILITY_M6|| | |
935 ati_card_ids[idx] == DEVICE_ATI_RADEON_MOBILITY_M62) RadeonFamily = 100; | |
8859 | 936 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_RV200_QW || |
937 ati_card_ids[idx] == DEVICE_ATI_RADEON_RV200_QX) RadeonFamily = 150; | |
8855 | 938 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_BB || |
939 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QH || | |
940 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QI || | |
941 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QJ || | |
942 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QK || | |
943 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QL || | |
944 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QH2 || | |
945 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QI2 || | |
946 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QJ2 || | |
8859 | 947 ati_card_ids[idx] == DEVICE_ATI_RADEON_R200_QK2) RadeonFamily = 200; |
8855 | 948 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_ID || |
949 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_IE || | |
950 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_IF || | |
951 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_IG || | |
952 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_LD || | |
953 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_LE || | |
954 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_LF || | |
955 ati_card_ids[idx] == DEVICE_ATI_RADEON_R250_LG) RadeonFamily = 250; | |
956 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_R300_ND || | |
957 ati_card_ids[idx] == DEVICE_ATI_RADEON_R300_NE || | |
958 ati_card_ids[idx] == DEVICE_ATI_RADEON_R300_NF || | |
959 ati_card_ids[idx] == DEVICE_ATI_RADEON_R300_NG) RadeonFamily = 300; | |
960 } | |
3996 | 961 #endif |
4193 | 962 if(force > PROBE_NORMAL) |
963 { | |
964 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
965 if(idx == -1) | |
966 #ifdef RAGE128 | |
4373 | 967 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 968 #else |
4373 | 969 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 970 #endif |
971 } | |
4191 | 972 def_cap.device_id = lst[i].device; |
3996 | 973 err = 0; |
974 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
975 probed=1; | |
976 break; | |
977 } | |
978 } | |
979 } | |
980 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
981 return err; | |
982 } | |
983 | |
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984 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
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985 |
3996 | 986 int vixInit( void ) |
987 { | |
4477 | 988 int err; |
4012 | 989 if(!probed) |
990 { | |
991 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
992 return EINTR; | |
993 } | |
994 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 995 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
996 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
997 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
998 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
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999 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 1000 radeon_vid_make_default(); |
1001 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 1002 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
1003 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
8521
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1004 |
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1005 radeon_fifo_wait(3); |
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1006 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
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1007 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
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1008 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
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1009 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
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1010 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
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1011 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
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1012 |
8521
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1013 #ifdef RADEON |
8859 | 1014 switch(RadeonFamily) |
1015 { | |
1016 case 100: | |
1017 case 150: | |
1018 case 250: | |
1019 is_shift_required=1; | |
1020 break; | |
1021 default: | |
1022 break; | |
1023 } | |
1024 | |
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1025 switch(def_cap.device_id) |
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1026 { |
8854 | 1027 case DEVICE_ATI_RADEON_MOBILITY_M7: |
1028 case DEVICE_ATI_RADEON_MOBILITY_M72: | |
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1029 case DEVICE_ATI_RADEON_MOBILITY_M62: |
8858 | 1030 rage_ckey_model=1; |
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1031 default: |
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1032 // printf(RADEON_MSG" Warning! Probably colorkeying isn't working correct!\n"); |
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1033 break; |
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1034 } |
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1035 #endif |
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1036 |
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1037 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1038 return 0; |
1039 } | |
1040 | |
1041 void vixDestroy( void ) | |
1042 { | |
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1043 /* remove colorkeying */ |
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1044 radeon_fifo_wait(3); |
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1045 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
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1046 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
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1047 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
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1048 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
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1049 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
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1050 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
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1051 |
3996 | 1052 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 1053 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 1054 } |
1055 | |
1056 int vixGetCapability(vidix_capability_t *to) | |
1057 { | |
1058 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1059 return 0; | |
1060 } | |
1061 | |
6483 | 1062 /* |
1063 Full list of fourcc which are supported by Win2K redeon driver: | |
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1064 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1065 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1066 */ | |
3996 | 1067 uint32_t supported_fourcc[] = |
1068 { | |
6483 | 1069 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1070 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1071 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1072 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1073 IMGFMT_RGB16, IMGFMT_BGR16, |
1074 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1075 }; |
1076 | |
6483 | 1077 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1078 { |
6483 | 1079 unsigned int i; |
3996 | 1080 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1081 { | |
1082 if(fourcc==supported_fourcc[i]) return 1; | |
1083 } | |
1084 return 0; | |
1085 } | |
1086 | |
1087 int vixQueryFourcc(vidix_fourcc_t *to) | |
1088 { | |
1089 if(is_supported_fourcc(to->fourcc)) | |
1090 { | |
1091 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1092 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1093 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1094 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1095 VID_DEPTH_32BPP; | |
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1096 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1097 return 0; |
1098 } | |
4015 | 1099 else to->depth = to->flags = 0; |
3996 | 1100 return ENOSYS; |
1101 } | |
1102 | |
1103 static void radeon_vid_dump_regs( void ) | |
1104 { | |
1105 size_t i; | |
4015 | 1106 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1107 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1108 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1109 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1110 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1111 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1112 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1113 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1114 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1115 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1116 } |
1117 | |
1118 static void radeon_vid_stop_video( void ) | |
1119 { | |
1120 radeon_engine_idle(); | |
1121 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1122 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1123 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1124 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
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1125 #ifdef RADEON |
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1126 OUTREG(OV0_KEY_CNTL, rage_ckey_model ? GRAPHIC_KEY_FN_NE : GRAPHIC_KEY_FN_EQ); |
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1127 #else |
3996 | 1128 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
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1129 #endif |
3996 | 1130 OUTREG(OV0_TEST, 0); |
1131 } | |
1132 | |
1133 static void radeon_vid_display_video( void ) | |
1134 { | |
1135 int bes_flags; | |
1136 radeon_fifo_wait(2); | |
1137 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1138 radeon_engine_idle(); | |
1139 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1140 radeon_fifo_wait(15); | |
4666 | 1141 |
1142 /* Shutdown capturing */ | |
1143 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1144 OUTREG(CAP0_TRIG_CNTL, 0); | |
1145 | |
4689 | 1146 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1147 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1148 |
3996 | 1149 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1150 | |
4611 | 1151 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1152 #ifdef RAGE128 |
7493 | 1153 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1154 (((besr.saturation*31+31000)/2000) << 8) | | |
1155 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1156 #endif |
1157 radeon_fifo_wait(2); | |
4869 | 1158 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1159 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1160 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1161 |
1162 OUTREG(OV0_H_INC, besr.h_inc); | |
1163 OUTREG(OV0_STEP_BY, besr.step_by); | |
1164 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1165 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1166 OUTREG(OV0_V_INC, besr.v_inc); | |
1167 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1168 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1169 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1170 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1171 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1172 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1173 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1174 #ifdef RADEON | |
1175 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1176 #endif | |
4930 | 1177 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1178 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1179 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1180 radeon_fifo_wait(9); |
4930 | 1181 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1182 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1183 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1184 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1185 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1186 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1187 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1188 | |
6678 | 1189 #ifdef RADEON |
1190 bes_flags = SCALER_ENABLE | | |
1191 SCALER_SMART_SWITCH; | |
1192 // SCALER_HORZ_PICK_NEAREST | | |
1193 // SCALER_VERT_PICK_NEAREST | | |
1194 #endif | |
3996 | 1195 bes_flags = SCALER_ENABLE | |
1196 SCALER_SMART_SWITCH | | |
1197 SCALER_Y2R_TEMP | | |
1198 SCALER_PIX_EXPAND; | |
1199 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1200 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1201 #ifdef RAGE128 | |
1202 bes_flags |= SCALER_BURST_PER_PLANE; | |
1203 #endif | |
1204 switch(besr.fourcc) | |
1205 { | |
1206 case IMGFMT_RGB15: | |
1207 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1208 case IMGFMT_RGB16: |
3996 | 1209 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1210 /* |
3996 | 1211 case IMGFMT_RGB24: |
1212 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1213 */ |
3996 | 1214 case IMGFMT_RGB32: |
1215 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1216 /* 4:1:0 */ |
3996 | 1217 case IMGFMT_IF09: |
1218 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1219 /* 4:0:0 */ |
1220 case IMGFMT_Y800: | |
1221 case IMGFMT_Y8: | |
3996 | 1222 /* 4:2:0 */ |
1223 case IMGFMT_IYUV: | |
1224 case IMGFMT_I420: | |
6483 | 1225 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1226 /* 4:2:2 */ |
4455 | 1227 case IMGFMT_YVYU: |
3996 | 1228 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1229 case IMGFMT_YUY2: | |
1230 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1231 } | |
1232 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1233 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1234 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1235 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1236 } |
1237 | |
4456 | 1238 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1239 { |
4456 | 1240 unsigned pitch,spy,spv,spu; |
1241 spy = spv = spu = 0; | |
1242 switch(spitch->y) | |
1243 { | |
1244 case 16: | |
1245 case 32: | |
1246 case 64: | |
1247 case 128: | |
1248 case 256: spy = spitch->y; break; | |
1249 default: break; | |
1250 } | |
1251 switch(spitch->u) | |
1252 { | |
1253 case 16: | |
1254 case 32: | |
1255 case 64: | |
1256 case 128: | |
1257 case 256: spu = spitch->u; break; | |
1258 default: break; | |
1259 } | |
1260 switch(spitch->v) | |
1261 { | |
1262 case 16: | |
1263 case 32: | |
1264 case 64: | |
1265 case 128: | |
1266 case 256: spv = spitch->v; break; | |
1267 default: break; | |
1268 } | |
4009 | 1269 switch(fourcc) |
1270 { | |
1271 /* 4:2:0 */ | |
1272 case IMGFMT_IYUV: | |
1273 case IMGFMT_YV12: | |
4456 | 1274 case IMGFMT_I420: |
1275 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1276 else pitch = 32; | |
1277 break; | |
6483 | 1278 /* 4:1:0 */ |
1279 case IMGFMT_IF09: | |
6254
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1280 case IMGFMT_YVU9: |
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1281 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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1282 else pitch = 64; |
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|
1283 break; |
4456 | 1284 default: |
1285 if(spy >= 16) pitch = spy; | |
1286 else pitch = 16; | |
1287 break; | |
4009 | 1288 } |
1289 return pitch; | |
1290 } | |
1291 | |
3996 | 1292 static int radeon_vid_init_video( vidix_playback_t *config ) |
1293 { | |
4930 | 1294 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1295 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1296 radeon_vid_stop_video(); |
1297 left = config->src.x << 16; | |
1298 top = config->src.y << 16; | |
1299 src_h = config->src.h; | |
1300 src_w = config->src.w; | |
6483 | 1301 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1302 if(config->fourcc == IMGFMT_YV12 || |
1303 config->fourcc == IMGFMT_I420 || | |
1304 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1305 if(config->fourcc == IMGFMT_YVU9 || |
1306 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1307 if(config->fourcc == IMGFMT_Y800 || | |
1308 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1309 if(config->fourcc == IMGFMT_RGB32 || |
1310 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1311 if(config->fourcc == IMGFMT_RGB32 || |
1312 config->fourcc == IMGFMT_BGR32 || | |
1313 config->fourcc == IMGFMT_RGB24 || | |
1314 config->fourcc == IMGFMT_BGR24 || | |
1315 config->fourcc == IMGFMT_RGB16 || | |
1316 config->fourcc == IMGFMT_BGR16 || | |
1317 config->fourcc == IMGFMT_RGB15 || | |
1318 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1319 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1320 mpitch = best_pitch-1; |
3996 | 1321 switch(config->fourcc) |
1322 { | |
6483 | 1323 /* 4:0:0 */ |
1324 case IMGFMT_Y800: | |
1325 case IMGFMT_Y8: | |
1326 /* 4:1:0 */ | |
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1327 case IMGFMT_YVU9: |
6483 | 1328 case IMGFMT_IF09: |
3996 | 1329 /* 4:2:0 */ |
1330 case IMGFMT_IYUV: | |
1331 case IMGFMT_YV12: | |
4415 | 1332 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1333 config->dest.pitch.y = |
1334 config->dest.pitch.u = | |
4415 | 1335 config->dest.pitch.v = best_pitch; |
3996 | 1336 break; |
4416 | 1337 /* RGB 4:4:4:4 */ |
1338 case IMGFMT_RGB32: | |
1339 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1340 config->dest.pitch.y = | |
1341 config->dest.pitch.u = | |
1342 config->dest.pitch.v = best_pitch; | |
1343 break; | |
3996 | 1344 /* 4:2:2 */ |
4455 | 1345 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1346 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1347 config->dest.pitch.y = |
1348 config->dest.pitch.u = | |
4415 | 1349 config->dest.pitch.v = best_pitch; |
3996 | 1350 break; |
1351 } | |
1352 dest_w = config->dest.w; | |
1353 dest_h = config->dest.h; | |
1354 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1355 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1356 besr.fourcc = config->fourcc; | |
1357 besr.v_inc = (src_h << 20) / dest_h; | |
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1358 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1359 h_inc = (src_w << 12) / dest_w; |
1360 step_by = 1; | |
1361 while(h_inc >= (2 << 12)) { | |
1362 step_by++; | |
1363 h_inc >>= 1; | |
1364 } | |
1365 | |
1366 /* keep everything in 16.16 */ | |
4015 | 1367 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1368 config->offsets[0] = 0; |
4930 | 1369 for(i=1;i<besr.vid_nbufs;i++) |
1370 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1371 if(is_420 || is_410 || is_400) |
3996 | 1372 { |
1373 uint32_t d1line,d2line,d3line; | |
1374 d1line = top*pitch; | |
6483 | 1375 if(is_420) |
1376 { | |
1377 d2line = src_h*pitch+(d1line>>2); | |
1378 d3line = d2line+((src_h*pitch)>>2); | |
1379 } | |
1380 else | |
1381 if(is_410) | |
1382 { | |
1383 d2line = src_h*pitch+(d1line>>4); | |
1384 d3line = d2line+((src_h*pitch)>>4); | |
1385 } | |
1386 else | |
1387 { | |
1388 d2line = 0; | |
1389 d3line = 0; | |
1390 } | |
3996 | 1391 d1line += (left >> 16) & ~15; |
6483 | 1392 if(is_420) |
1393 { | |
1394 d2line += (left >> 17) & ~15; | |
1395 d3line += (left >> 17) & ~15; | |
1396 } | |
1397 else | |
1398 if(is_410) | |
1399 { | |
1400 d2line += (left >> 18) & ~15; | |
1401 d3line += (left >> 18) & ~15; | |
1402 } | |
3996 | 1403 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1404 if(is_400) |
1405 { | |
1406 config->offset.v = 0; | |
1407 config->offset.u = 0; | |
1408 } | |
1409 else | |
1410 { | |
1411 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1412 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1413 } | |
4930 | 1414 for(i=0;i<besr.vid_nbufs;i++) |
1415 { | |
1416 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1417 if(is_400) |
1418 { | |
1419 besr.vid_buf_base_adrs_v[i]=0; | |
1420 besr.vid_buf_base_adrs_u[i]=0; | |
1421 } | |
1422 else | |
1423 { | |
1424 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1425 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1426 } | |
4930 | 1427 } |
1428 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1429 if(is_400) |
1430 { | |
1431 config->offset.v = 0; | |
1432 config->offset.u = 0; | |
1433 } | |
1434 else | |
1435 { | |
1436 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1437 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1438 } | |
3996 | 1439 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1440 { | |
1441 uint32_t tmp; | |
1442 tmp = config->offset.u; | |
1443 config->offset.u = config->offset.v; | |
1444 config->offset.v = tmp; | |
1445 } | |
1446 } | |
1447 else | |
1448 { | |
1449 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1450 for(i=0;i<besr.vid_nbufs;i++) |
1451 { | |
1452 besr.vid_buf_base_adrs_y[i] = | |
1453 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1454 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1455 } |
3996 | 1456 } |
1457 | |
1458 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1459 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1460 ((tmp << 12) & 0xf0000000); | |
1461 | |
1462 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1463 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1464 ((tmp << 12) & 0x70000000); | |
1465 tmp = (top & 0x0000ffff) + 0x00018000; | |
1466 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1467 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1468 | |
1469 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1470 besr.p23_v_accum_init = (is_420||is_410) ? |
1471 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1472 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1473 | |
6483 | 1474 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1475 left = (left >> 16) & 15; |
4571 | 1476 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1477 if(is_rgb32) |
4571 | 1478 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1479 else |
6483 | 1480 if(is_410) |
1481 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1482 else | |
4416 | 1483 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1484 besr.step_by = step_by | (step_by << 8); |
1485 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1486 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1487 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1488 if(is_420 || is_410) |
3996 | 1489 { |
6483 | 1490 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1491 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1492 } | |
1493 else besr.p23_blank_lines_at_top = 0; | |
1494 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1495 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1496 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1497 if (is_410||is_420) src_w>>=is_410?2:1; |
1498 if(is_400) | |
1499 { | |
1500 besr.p2_x_start_end = 0; | |
1501 besr.p3_x_start_end = 0; | |
1502 } | |
1503 else | |
1504 { | |
1505 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1506 besr.p3_x_start_end = besr.p2_x_start_end; | |
1507 } | |
4869 | 1508 |
3996 | 1509 return 0; |
1510 } | |
1511 | |
4009 | 1512 static void radeon_compute_framesize(vidix_playback_t *info) |
1513 { | |
4666 | 1514 unsigned pitch,awidth,dbpp; |
4456 | 1515 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1516 dbpp = radeon_vid_get_dbpp(); |
4033 | 1517 switch(info->fourcc) |
1518 { | |
1519 case IMGFMT_I420: | |
1520 case IMGFMT_YV12: | |
1521 case IMGFMT_IYUV: | |
4666 | 1522 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1523 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1524 break; |
6483 | 1525 case IMGFMT_Y800: |
1526 case IMGFMT_Y8: | |
1527 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1528 info->frame_size = awidth*info->src.h; | |
1529 break; | |
1530 case IMGFMT_IF09: | |
1531 case IMGFMT_YVU9: | |
1532 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1533 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1534 break; | |
4429 | 1535 case IMGFMT_RGB32: |
1536 case IMGFMT_BGR32: | |
4666 | 1537 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1538 info->frame_size = awidth*info->src.h; |
4429 | 1539 break; |
1540 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1541 default: |
1542 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1543 info->frame_size = awidth*info->src.h; |
4033 | 1544 break; |
1545 } | |
4009 | 1546 } |
1547 | |
3996 | 1548 int vixConfigPlayback(vidix_playback_t *info) |
1549 { | |
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1550 unsigned rgb_size,nfr; |
3996 | 1551 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1552 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1553 if(info->num_frames==1) besr.double_buff=0; |
1554 else besr.double_buff=1; | |
4009 | 1555 radeon_compute_framesize(info); |
4930 | 1556 |
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1557 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1558 nfr = info->num_frames; |
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1559 for(;nfr>0; nfr--) |
4930 | 1560 { |
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1561 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1562 radeon_overlay_off &= 0xffff0000; |
1563 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1564 } | |
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1565 if(nfr <= 3) |
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1566 { |
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1567 nfr = info->num_frames; |
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1568 for(;nfr>0; nfr--) |
4930 | 1569 { |
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1570 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1571 radeon_overlay_off &= 0xffff0000; |
1572 if(radeon_overlay_off > 0) break; | |
1573 } | |
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1574 } |
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1575 if(nfr <= 0) return EINVAL; |
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1576 info->num_frames = nfr; |
4930 | 1577 besr.vid_nbufs = info->num_frames; |
1578 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1579 radeon_vid_init_video(info); |
1580 return 0; | |
1581 } | |
1582 | |
1583 int vixPlaybackOn( void ) | |
1584 { | |
1585 radeon_vid_display_video(); | |
1586 return 0; | |
1587 } | |
1588 | |
1589 int vixPlaybackOff( void ) | |
1590 { | |
1591 radeon_vid_stop_video(); | |
1592 return 0; | |
1593 } | |
1594 | |
4033 | 1595 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1596 { |
4412 | 1597 uint32_t off[6]; |
4930 | 1598 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1599 /* |
1600 buf3-5 always should point onto second buffer for better | |
1601 deinterlacing and TV-in | |
1602 */ | |
4666 | 1603 if(!besr.double_buff) return 0; |
4930 | 1604 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1605 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1606 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1607 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1608 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1609 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1610 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1611 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1612 radeon_fifo_wait(8); |
3996 | 1613 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1614 radeon_engine_idle(); |
3996 | 1615 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1616 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1617 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1618 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1619 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1620 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1621 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1622 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1623 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1624 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1625 return 0; |
1626 } | |
1627 | |
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1628 vidix_video_eq_t equal = |
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1629 { |
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1630 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1631 #ifndef RAGE128 |
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1632 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1633 #endif |
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1634 , |
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1635 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1636 |
1637 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1638 { | |
1639 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1640 return 0; | |
1641 } | |
1642 | |
4229 | 1643 #ifndef RAGE128 |
1644 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1645 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1646 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1647 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1648 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1649 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1650 #endif | |
1651 | |
3996 | 1652 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1653 { | |
1654 #ifdef RAGE128 | |
1655 int br,sat; | |
4229 | 1656 #else |
1657 int itu_space; | |
3996 | 1658 #endif |
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1659 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1660 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1661 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1662 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1663 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1664 { |
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1665 equal.red_intensity = eq->red_intensity; |
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1666 equal.green_intensity = eq->green_intensity; |
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1667 equal.blue_intensity = eq->blue_intensity; |
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1668 } |
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1669 equal.flags = eq->flags; |
3996 | 1670 #ifdef RAGE128 |
1671 br = equal.brightness * 64 / 1000; | |
4229 | 1672 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1673 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1674 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1675 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1676 #else | |
4229 | 1677 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1678 RTFCheckParam(equal.brightness); | |
1679 RTFCheckParam(equal.saturation); | |
1680 RTFCheckParam(equal.contrast); | |
1681 RTFCheckParam(equal.hue); | |
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1682 RTFCheckParam(equal.red_intensity); |
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1683 RTFCheckParam(equal.green_intensity); |
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1684 RTFCheckParam(equal.blue_intensity); |
4229 | 1685 radeon_set_transform(RTFBrightness(equal.brightness), |
1686 RTFContrast(equal.contrast), | |
1687 RTFSaturation(equal.saturation), | |
1688 RTFHue(equal.hue), | |
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1689 RTFIntensity(equal.red_intensity), |
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1690 RTFIntensity(equal.green_intensity), |
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1691 RTFIntensity(equal.blue_intensity), |
4229 | 1692 itu_space); |
3996 | 1693 #endif |
1694 return 0; | |
1695 } | |
1696 | |
4611 | 1697 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1698 { | |
1699 unsigned sflg; | |
1700 switch(info->flags) | |
1701 { | |
1702 default: | |
1703 case CFG_NON_INTERLACED: | |
1704 besr.deinterlace_on = 0; | |
1705 break; | |
1706 case CFG_EVEN_ODD_INTERLACING: | |
1707 case CFG_INTERLACED: | |
1708 besr.deinterlace_on = 1; | |
1709 besr.deinterlace_pattern = 0x900AAAAA; | |
1710 break; | |
1711 case CFG_ODD_EVEN_INTERLACING: | |
1712 besr.deinterlace_on = 1; | |
1713 besr.deinterlace_pattern = 0x00055555; | |
1714 break; | |
1715 case CFG_UNIQUE_INTERLACING: | |
1716 besr.deinterlace_on = 1; | |
1717 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1718 break; | |
1719 } | |
1720 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1721 radeon_engine_idle(); | |
1722 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1723 radeon_fifo_wait(15); | |
1724 sflg = INREG(OV0_SCALE_CNTL); | |
1725 if(besr.deinterlace_on) | |
1726 { | |
1727 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1728 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1729 } | |
1730 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1731 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1732 return 0; | |
1733 } | |
1734 | |
1735 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1736 { | |
1737 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1738 else | |
1739 { | |
1740 info->flags = CFG_UNIQUE_INTERLACING; | |
1741 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1742 } | |
1743 return 0; | |
1744 } | |
4869 | 1745 |
1746 | |
1747 /* Graphic keys */ | |
1748 static vidix_grkey_t radeon_grkey; | |
1749 | |
1750 static void set_gr_key( void ) | |
1751 { | |
1752 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1753 { | |
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1754 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1755 besr.ckey_on=1; |
1756 | |
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1757 switch(dbpp) |
4869 | 1758 { |
1759 case 15: | |
8856 | 1760 #ifdef RADEON |
8858 | 1761 if(RadeonFamily > 100) |
8856 | 1762 besr.graphics_key_clr= |
1763 ((radeon_grkey.ckey.blue &0xF8)) | |
1764 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
1765 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1766 else | |
1767 #endif | |
4869 | 1768 besr.graphics_key_clr= |
1769 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1770 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
1771 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
1772 break; | |
1773 case 16: | |
8856 | 1774 #ifdef RADEON |
1775 /* This test may be too general/specific */ | |
8858 | 1776 if(RadeonFamily > 100) |
8856 | 1777 besr.graphics_key_clr= |
1778 ((radeon_grkey.ckey.blue &0xF8)) | |
1779 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
1780 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1781 else | |
1782 #endif | |
4869 | 1783 besr.graphics_key_clr= |
1784 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1785 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
1786 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
1787 break; | |
1788 case 24: | |
1789 besr.graphics_key_clr= | |
1790 ((radeon_grkey.ckey.blue &0xFF)) | |
1791 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1792 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1793 break; | |
1794 case 32: | |
1795 besr.graphics_key_clr= | |
1796 ((radeon_grkey.ckey.blue &0xFF)) | |
1797 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1798 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1799 break; | |
1800 default: | |
1801 besr.ckey_on=0; | |
1802 besr.graphics_key_msk=0; | |
1803 besr.graphics_key_clr=0; | |
1804 } | |
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1805 #ifdef RAGE128 |
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1806 besr.graphics_key_msk=(1<<dbpp)-1; |
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1807 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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1808 #else |
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1809 besr.graphics_key_msk=besr.graphics_key_clr; |
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1810 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND; |
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1811 if(rage_ckey_model) |
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1812 besr.ckey_cntl |= GRAPHIC_KEY_FN_NE; |
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1813 else |
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1814 besr.ckey_cntl |= GRAPHIC_KEY_FN_EQ; |
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1815 #endif |
4869 | 1816 } |
1817 else | |
1818 { | |
1819 besr.ckey_on=0; | |
1820 besr.graphics_key_msk=0; | |
1821 besr.graphics_key_clr=0; | |
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1822 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 1823 } |
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1824 radeon_fifo_wait(3); |
4869 | 1825 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1826 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1827 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1828 } | |
1829 | |
1830 int vixGetGrKeys(vidix_grkey_t *grkey) | |
1831 { | |
1832 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
1833 return(0); | |
1834 } | |
1835 | |
1836 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
1837 { | |
1838 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
1839 set_gr_key(); | |
1840 return(0); | |
1841 } |