Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 11169:9a100ec9135f
gamma weight patch by (Alexander Stege <mplayer at legale-software dot com>)
author | michael |
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date | Sat, 18 Oct 2003 23:02:30 +0000 |
parents | dd748f428d05 |
children | 9cd1546f26ea |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
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6 PPC support by Alex Beregszaszi |
3996 | 7 */ |
8 | |
9 #include <errno.h> | |
10 #include <stdio.h> | |
11 #include <stdlib.h> | |
12 #include <string.h> | |
13 #include <math.h> | |
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14 #include <inttypes.h> |
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15 |
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16 #include "../../config.h" |
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17 #include "../../bswap.h" |
4201 | 18 #include "../../libdha/pci_ids.h" |
19 #include "../../libdha/pci_names.h" | |
3996 | 20 #include "../vidix.h" |
21 #include "../fourcc.h" | |
22 #include "../../libdha/libdha.h" | |
23 #include "radeon.h" | |
24 | |
25 #ifdef RAGE128 | |
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26 #define RADEON_MSG "[rage128]" |
3996 | 27 #define X_ADJUST 0 |
28 #else | |
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29 #define RADEON_MSG "[radeon]" |
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30 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 31 #ifndef RADEON |
32 #define RADEON | |
33 #endif | |
34 #endif | |
35 | |
4030 | 36 static int __verbose = 0; |
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37 #ifdef RADEON |
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38 static int is_shift_required = 0; |
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39 #endif |
4015 | 40 |
3996 | 41 typedef struct bes_registers_s |
42 { | |
43 /* base address of yuv framebuffer */ | |
44 uint32_t yuv_base; | |
45 uint32_t fourcc; | |
46 uint32_t dest_bpp; | |
47 /* YUV BES registers */ | |
48 uint32_t reg_load_cntl; | |
49 uint32_t h_inc; | |
50 uint32_t step_by; | |
51 uint32_t y_x_start; | |
52 uint32_t y_x_end; | |
53 uint32_t v_inc; | |
54 uint32_t p1_blank_lines_at_top; | |
55 uint32_t p23_blank_lines_at_top; | |
56 uint32_t vid_buf_pitch0_value; | |
57 uint32_t vid_buf_pitch1_value; | |
58 uint32_t p1_x_start_end; | |
59 uint32_t p2_x_start_end; | |
60 uint32_t p3_x_start_end; | |
61 uint32_t base_addr; | |
4930 | 62 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
63 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
64 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
65 uint32_t vid_nbufs; | |
3996 | 66 |
67 uint32_t p1_v_accum_init; | |
68 uint32_t p1_h_accum_init; | |
69 uint32_t p23_v_accum_init; | |
70 uint32_t p23_h_accum_init; | |
71 uint32_t scale_cntl; | |
72 uint32_t exclusive_horz; | |
73 uint32_t auto_flip_cntl; | |
74 uint32_t filter_cntl; | |
75 uint32_t key_cntl; | |
76 uint32_t test; | |
77 /* Configurable stuff */ | |
78 int double_buff; | |
79 | |
80 int brightness; | |
81 int saturation; | |
82 | |
83 int ckey_on; | |
84 uint32_t graphics_key_clr; | |
85 uint32_t graphics_key_msk; | |
4869 | 86 uint32_t ckey_cntl; |
3996 | 87 |
88 int deinterlace_on; | |
89 uint32_t deinterlace_pattern; | |
90 | |
91 } bes_registers_t; | |
92 | |
93 typedef struct video_registers_s | |
94 { | |
95 const char * sname; | |
96 uint32_t name; | |
97 uint32_t value; | |
98 }video_registers_t; | |
99 | |
100 static bes_registers_t besr; | |
101 #ifndef RAGE128 | |
8855 | 102 static int RadeonFamily=100; |
3996 | 103 #endif |
104 #define DECLARE_VREG(name) { #name, name, 0 } | |
105 static video_registers_t vregs[] = | |
106 { | |
107 DECLARE_VREG(VIDEOMUX_CNTL), | |
108 DECLARE_VREG(VIPPAD_MASK), | |
109 DECLARE_VREG(VIPPAD1_A), | |
110 DECLARE_VREG(VIPPAD1_EN), | |
111 DECLARE_VREG(VIPPAD1_Y), | |
112 DECLARE_VREG(OV0_Y_X_START), | |
113 DECLARE_VREG(OV0_Y_X_END), | |
114 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
115 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
116 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
117 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
118 DECLARE_VREG(OV0_SCALE_CNTL), | |
119 DECLARE_VREG(OV0_V_INC), | |
120 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
121 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
122 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
123 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
124 #ifdef RADEON | |
125 DECLARE_VREG(OV0_BASE_ADDR), | |
126 #endif | |
127 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
128 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
129 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
130 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
131 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
132 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
133 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
134 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
135 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
136 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
137 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
138 DECLARE_VREG(OV0_H_INC), | |
139 DECLARE_VREG(OV0_STEP_BY), | |
140 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
141 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
142 DECLARE_VREG(OV0_P1_X_START_END), | |
143 DECLARE_VREG(OV0_P2_X_START_END), | |
144 DECLARE_VREG(OV0_P3_X_START_END), | |
145 DECLARE_VREG(OV0_FILTER_CNTL), | |
146 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
147 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
148 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
149 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
150 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
151 DECLARE_VREG(OV0_FLAG_CNTL), | |
152 #ifdef RAGE128 | |
153 DECLARE_VREG(OV0_COLOUR_CNTL), | |
154 #else | |
155 DECLARE_VREG(OV0_SLICE_CNTL), | |
156 #endif | |
157 DECLARE_VREG(OV0_VID_KEY_CLR), | |
158 DECLARE_VREG(OV0_VID_KEY_MSK), | |
159 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
160 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
161 DECLARE_VREG(OV0_KEY_CNTL), | |
162 DECLARE_VREG(OV0_TEST), | |
163 DECLARE_VREG(OV0_LIN_TRANS_A), | |
164 DECLARE_VREG(OV0_LIN_TRANS_B), | |
165 DECLARE_VREG(OV0_LIN_TRANS_C), | |
166 DECLARE_VREG(OV0_LIN_TRANS_D), | |
167 DECLARE_VREG(OV0_LIN_TRANS_E), | |
168 DECLARE_VREG(OV0_LIN_TRANS_F), | |
169 DECLARE_VREG(OV0_GAMMA_0_F), | |
170 DECLARE_VREG(OV0_GAMMA_10_1F), | |
171 DECLARE_VREG(OV0_GAMMA_20_3F), | |
172 DECLARE_VREG(OV0_GAMMA_40_7F), | |
173 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
174 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
175 DECLARE_VREG(SUBPIC_CNTL), | |
176 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
177 DECLARE_VREG(SUBPIC_Y_X_START), | |
178 DECLARE_VREG(SUBPIC_Y_X_END), | |
179 DECLARE_VREG(SUBPIC_V_INC), | |
180 DECLARE_VREG(SUBPIC_H_INC), | |
181 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
182 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
183 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
184 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
185 DECLARE_VREG(SUBPIC_PITCH), | |
186 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
187 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
188 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
189 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
190 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
191 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
192 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
193 DECLARE_VREG(IDCT_RUNS), | |
194 DECLARE_VREG(IDCT_LEVELS), | |
195 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
196 DECLARE_VREG(IDCT_AUTH), | |
9044 | 197 DECLARE_VREG(IDCT_CONTROL), |
198 DECLARE_VREG(CONFIG_CNTL) | |
3996 | 199 }; |
4030 | 200 |
3996 | 201 static void * radeon_mmio_base = 0; |
202 static void * radeon_mem_base = 0; | |
203 static int32_t radeon_overlay_off = 0; | |
204 static uint32_t radeon_ram_size = 0; | |
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205 /* Restore on exit */ |
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206 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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207 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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208 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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209 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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210 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
9044 | 211 #if defined(RAGE128) && (WORDS_BIGENDIAN) |
212 static uint32_t SAVED_CONFIG_CNTL = 0; | |
213 #define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) | |
214 #define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) | |
215 #endif | |
3996 | 216 |
4012 | 217 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
218 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
219 | |
220 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
221 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
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222 |
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223 static inline uint32_t INREG (uint32_t addr) { |
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224 uint32_t tmp = GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr); |
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225 return le2me_32(tmp); |
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226 } |
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227 //#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) |
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228 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,le2me_32(val)) |
3996 | 229 #define OUTREGP(addr,val,mask) \ |
230 do { \ | |
231 unsigned int _tmp = INREG(addr); \ | |
232 _tmp &= (mask); \ | |
233 _tmp |= (val); \ | |
234 OUTREG(addr, _tmp); \ | |
235 } while (0) | |
236 | |
4666 | 237 static __inline__ uint32_t INPLL(uint32_t addr) |
238 { | |
239 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
240 return (INREG(CLOCK_CNTL_DATA)); | |
241 } | |
242 | |
243 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
244 OUTREG(CLOCK_CNTL_DATA, val) | |
245 #define OUTPLLP(addr,val,mask) \ | |
246 do { \ | |
247 unsigned int _tmp = INPLL(addr); \ | |
248 _tmp &= (mask); \ | |
249 _tmp |= (val); \ | |
250 OUTPLL(addr, _tmp); \ | |
251 } while (0) | |
252 | |
3996 | 253 static uint32_t radeon_vid_get_dbpp( void ) |
254 { | |
255 uint32_t dbpp,retval; | |
256 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
257 switch(dbpp) | |
258 { | |
259 case DST_8BPP: retval = 8; break; | |
260 case DST_15BPP: retval = 15; break; | |
261 case DST_16BPP: retval = 16; break; | |
262 case DST_24BPP: retval = 24; break; | |
263 default: retval=32; break; | |
264 } | |
265 return retval; | |
266 } | |
267 | |
268 static int radeon_is_dbl_scan( void ) | |
269 { | |
270 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
271 } | |
272 | |
273 static int radeon_is_interlace( void ) | |
274 { | |
275 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
276 } | |
277 | |
4666 | 278 static uint32_t radeon_get_xres( void ) |
279 { | |
280 /* FIXME: currently we extract that from CRTC!!!*/ | |
281 uint32_t xres,h_total; | |
282 h_total = INREG(CRTC_H_TOTAL_DISP); | |
283 xres = (h_total >> 16) & 0xffff; | |
284 return (xres + 1)*8; | |
285 } | |
286 | |
287 static uint32_t radeon_get_yres( void ) | |
288 { | |
289 /* FIXME: currently we extract that from CRTC!!!*/ | |
290 uint32_t yres,v_total; | |
291 v_total = INREG(CRTC_V_TOTAL_DISP); | |
292 yres = (v_total >> 16) & 0xffff; | |
293 return yres + 1; | |
294 } | |
295 | |
4689 | 296 static void radeon_wait_vsync(void) |
297 { | |
298 int i; | |
299 | |
300 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
301 for (i = 0; i < 2000000; i++) | |
302 { | |
303 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
304 } | |
305 } | |
306 | |
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307 #ifdef RAGE128 |
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308 static void _radeon_engine_idle(void); |
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309 static void _radeon_fifo_wait(unsigned); |
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310 #define radeon_engine_idle() _radeon_engine_idle() |
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311 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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312 /* Flush all dirty data in the Pixel Cache to memory. */ |
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313 static __inline__ void radeon_engine_flush ( void ) |
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314 { |
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315 unsigned i; |
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316 |
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317 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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318 for (i = 0; i < 2000000; i++) { |
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319 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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320 } |
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321 } |
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322 |
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323 /* Reset graphics card to known state. */ |
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324 static void radeon_engine_reset( void ) |
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325 { |
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326 uint32_t clock_cntl_index; |
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327 uint32_t mclk_cntl; |
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328 uint32_t gen_reset_cntl; |
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329 |
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330 radeon_engine_flush(); |
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331 |
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332 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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333 mclk_cntl = INPLL(MCLK_CNTL); |
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334 |
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335 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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336 |
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337 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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338 |
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339 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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340 INREG(GEN_RESET_CNTL); |
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341 OUTREG(GEN_RESET_CNTL, |
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342 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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343 INREG(GEN_RESET_CNTL); |
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344 |
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345 OUTPLL(MCLK_CNTL, mclk_cntl); |
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346 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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347 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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348 } |
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349 #else |
4689 | 350 |
3996 | 351 static __inline__ void radeon_engine_flush ( void ) |
352 { | |
353 int i; | |
354 | |
355 /* initiate flush */ | |
356 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
357 ~RB2D_DC_FLUSH_ALL); | |
358 | |
359 for (i=0; i < 2000000; i++) { | |
360 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
361 break; | |
362 } | |
363 } | |
364 | |
4666 | 365 static void _radeon_engine_idle(void); |
366 static void _radeon_fifo_wait(unsigned); | |
367 #define radeon_engine_idle() _radeon_engine_idle() | |
368 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 369 |
4666 | 370 static void radeon_engine_reset( void ) |
3996 | 371 { |
4666 | 372 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
373 | |
374 radeon_engine_flush (); | |
375 | |
376 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
377 mclk_cntl = INPLL(MCLK_CNTL); | |
378 | |
379 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
380 FORCEON_MCLKA | | |
381 FORCEON_MCLKB | | |
382 FORCEON_YCLKA | | |
383 FORCEON_YCLKB | | |
384 FORCEON_MC | | |
385 FORCEON_AIC)); | |
386 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 387 |
4666 | 388 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
389 SOFT_RESET_CP | | |
390 SOFT_RESET_HI | | |
391 SOFT_RESET_SE | | |
392 SOFT_RESET_RE | | |
393 SOFT_RESET_PP | | |
394 SOFT_RESET_E2 | | |
395 SOFT_RESET_RB | | |
396 SOFT_RESET_HDP); | |
397 INREG(RBBM_SOFT_RESET); | |
398 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
399 ~(SOFT_RESET_CP | | |
400 SOFT_RESET_HI | | |
401 SOFT_RESET_SE | | |
402 SOFT_RESET_RE | | |
403 SOFT_RESET_PP | | |
404 SOFT_RESET_E2 | | |
405 SOFT_RESET_RB | | |
406 SOFT_RESET_HDP)); | |
407 INREG(RBBM_SOFT_RESET); | |
408 | |
409 OUTPLL(MCLK_CNTL, mclk_cntl); | |
410 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
411 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
412 | |
413 return; | |
3996 | 414 } |
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415 #endif |
4666 | 416 static void radeon_engine_restore( void ) |
3996 | 417 { |
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418 #ifndef RAGE128 |
4666 | 419 int pitch64; |
420 uint32_t xres,yres,bpp; | |
421 radeon_fifo_wait(1); | |
422 xres = radeon_get_xres(); | |
423 yres = radeon_get_yres(); | |
424 bpp = radeon_vid_get_dbpp(); | |
425 /* turn of all automatic flushing - we'll do it all */ | |
426 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
427 | |
428 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
429 | |
430 radeon_fifo_wait(1); | |
431 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
432 (pitch64 << 22)); | |
433 | |
434 radeon_fifo_wait(1); | |
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435 #if defined(WORDS_BIGENDIAN) |
9044 | 436 #ifdef RADEON |
437 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
438 #endif | |
4666 | 439 #else |
440 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
441 #endif | |
442 | |
443 radeon_fifo_wait(1); | |
444 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
445 | DEFAULT_SC_BOTTOM_MAX)); | |
446 radeon_fifo_wait(1); | |
447 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
448 | GMC_BRUSH_SOLID_COLOR | |
449 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 450 |
4666 | 451 radeon_fifo_wait(7); |
452 OUTREG(DST_LINE_START, 0); | |
453 OUTREG(DST_LINE_END, 0); | |
454 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
455 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
456 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
457 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
458 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
459 | |
460 radeon_engine_idle(); | |
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461 #endif |
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462 } |
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463 #ifdef RAGE128 |
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464 static void _radeon_fifo_wait (unsigned entries) |
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465 { |
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466 unsigned i; |
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467 |
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468 for(;;) |
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469 { |
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470 for (i=0; i<2000000; i++) |
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471 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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472 return; |
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473 radeon_engine_reset(); |
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474 radeon_engine_restore(); |
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475 } |
4666 | 476 } |
477 | |
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478 static void _radeon_engine_idle ( void ) |
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479 { |
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480 unsigned i; |
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481 |
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482 /* ensure FIFO is empty before waiting for idle */ |
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483 radeon_fifo_wait (64); |
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484 for(;;) |
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485 { |
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486 for (i=0; i<2000000; i++) { |
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487 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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488 radeon_engine_flush (); |
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489 return; |
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490 } |
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491 } |
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492 radeon_engine_reset(); |
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493 radeon_engine_restore(); |
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494 } |
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495 } |
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496 #else |
4666 | 497 static void _radeon_fifo_wait (unsigned entries) |
498 { | |
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499 unsigned i; |
3996 | 500 |
4666 | 501 for(;;) |
502 { | |
503 for (i=0; i<2000000; i++) | |
504 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
505 return; | |
506 radeon_engine_reset(); | |
507 radeon_engine_restore(); | |
508 } | |
509 } | |
510 static void _radeon_engine_idle ( void ) | |
511 { | |
512 int i; | |
513 | |
514 /* ensure FIFO is empty before waiting for idle */ | |
515 radeon_fifo_wait (64); | |
516 for(;;) | |
517 { | |
3996 | 518 for (i=0; i<2000000; i++) { |
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519 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 520 radeon_engine_flush (); |
521 return; | |
522 } | |
523 } | |
4666 | 524 radeon_engine_reset(); |
525 radeon_engine_restore(); | |
526 } | |
3996 | 527 } |
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528 #endif |
3996 | 529 |
530 #ifndef RAGE128 | |
531 /* Reference color space transform data */ | |
532 typedef struct tagREF_TRANSFORM | |
533 { | |
534 float RefLuma; | |
535 float RefRCb; | |
536 float RefRCr; | |
537 float RefGCb; | |
538 float RefGCr; | |
539 float RefBCb; | |
540 float RefBCr; | |
541 } REF_TRANSFORM; | |
542 | |
543 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
544 REF_TRANSFORM trans[2] = | |
545 { | |
546 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
547 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
548 }; | |
549 /**************************************************************************** | |
550 * SetTransform * | |
551 * Function: Calculates and sets color space transform from supplied * | |
552 * reference transform, gamma, brightness, contrast, hue and * | |
553 * saturation. * | |
554 * Inputs: bright - brightness * | |
555 * cont - contrast * | |
556 * sat - saturation * | |
557 * hue - hue * | |
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558 * red_intensity - intense of red component * |
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559 * green_intensity - intense of green component * |
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560 * blue_intensity - intense of blue component * |
3996 | 561 * ref - index to the table of refernce transforms * |
562 * Outputs: NONE * | |
563 ****************************************************************************/ | |
564 | |
565 static void radeon_set_transform(float bright, float cont, float sat, | |
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566 float hue, float red_intensity, |
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567 float green_intensity,float blue_intensity, |
4284 | 568 unsigned ref) |
3996 | 569 { |
570 float OvHueSin, OvHueCos; | |
571 float CAdjLuma, CAdjOff; | |
4284 | 572 float RedAdj,GreenAdj,BlueAdj; |
3996 | 573 float CAdjRCb, CAdjRCr; |
574 float CAdjGCb, CAdjGCr; | |
575 float CAdjBCb, CAdjBCr; | |
576 float OvLuma, OvROff, OvGOff, OvBOff; | |
577 float OvRCb, OvRCr; | |
578 float OvGCb, OvGCr; | |
579 float OvBCb, OvBCr; | |
580 float Loff = 64.0; | |
581 float Coff = 512.0f; | |
582 | |
583 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
584 uint32_t dwOvRCb, dwOvRCr; | |
585 uint32_t dwOvGCb, dwOvGCr; | |
586 uint32_t dwOvBCb, dwOvBCr; | |
587 | |
588 if (ref >= 2) return; | |
589 | |
590 OvHueSin = sin((double)hue); | |
591 OvHueCos = cos((double)hue); | |
592 | |
593 CAdjLuma = cont * trans[ref].RefLuma; | |
594 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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595 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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596 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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597 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 598 |
599 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
600 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
601 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
602 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
603 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
604 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
605 | |
606 #if 0 /* default constants */ | |
607 CAdjLuma = 1.16455078125; | |
608 | |
609 CAdjRCb = 0.0; | |
610 CAdjRCr = 1.59619140625; | |
611 CAdjGCb = -0.39111328125; | |
612 CAdjGCr = -0.8125; | |
613 CAdjBCb = 2.01708984375; | |
614 CAdjBCr = 0; | |
615 #endif | |
616 OvLuma = CAdjLuma; | |
617 OvRCb = CAdjRCb; | |
618 OvRCr = CAdjRCr; | |
619 OvGCb = CAdjGCb; | |
620 OvGCr = CAdjGCr; | |
621 OvBCb = CAdjBCb; | |
622 OvBCr = CAdjBCr; | |
4284 | 623 OvROff = RedAdj + CAdjOff - |
3996 | 624 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 625 OvGOff = GreenAdj + CAdjOff - |
3996 | 626 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 627 OvBOff = BlueAdj + CAdjOff - |
3996 | 628 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
629 #if 0 /* default constants */ | |
630 OvROff = -888.5; | |
631 OvGOff = 545; | |
632 OvBOff = -1104; | |
633 #endif | |
634 | |
635 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
636 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
637 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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intense->intensity + capability extension + fixing R200 color correction bug
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changeset
|
638 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
2d64382e8dcf
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changeset
|
639 as in Radeon is a lie */ |
2d64382e8dcf
intense->intensity + capability extension + fixing R200 color correction bug
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changeset
|
640 #if 0 |
8855 | 641 if(RadeonFamily == 100) |
3996 | 642 { |
4319
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diff
changeset
|
643 #endif |
3996 | 644 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
645 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
646 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
647 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
648 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
649 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
650 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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changeset
|
651 #if 0 |
3996 | 652 } |
653 else | |
654 { | |
655 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
656 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
657 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
658 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
659 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
660 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
661 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
662 } | |
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663 #endif |
3996 | 664 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
665 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
666 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
667 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
668 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
669 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
670 } | |
671 | |
672 /* Gamma curve definition */ | |
673 typedef struct | |
674 { | |
675 unsigned int gammaReg; | |
676 unsigned int gammaSlope; | |
677 unsigned int gammaOffset; | |
678 }GAMMA_SETTINGS; | |
679 | |
680 /* Recommended gamma curve parameters */ | |
681 GAMMA_SETTINGS r200_def_gamma[18] = | |
682 { | |
683 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
684 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
685 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
686 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
687 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
688 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
689 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
690 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
691 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
692 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
693 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
694 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
695 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
696 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
697 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
698 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
699 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
700 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
701 }; | |
702 | |
703 GAMMA_SETTINGS r100_def_gamma[6] = | |
704 { | |
705 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
706 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
707 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
708 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
709 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
710 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
711 }; | |
712 | |
713 static void make_default_gamma_correction( void ) | |
714 { | |
715 size_t i; | |
8855 | 716 if(RadeonFamily == 100) { |
3996 | 717 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
718 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
719 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
720 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
721 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
722 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
723 for(i=0; i<6; i++){ | |
724 OUTREG(r100_def_gamma[i].gammaReg, | |
725 (r100_def_gamma[i].gammaSlope<<16) | | |
726 r100_def_gamma[i].gammaOffset); | |
727 } | |
728 } | |
729 else{ | |
730 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
731 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
732 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
733 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
734 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
735 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
736 | |
737 /* Default Gamma, | |
738 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
739 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
740 for(i=0; i<18; i++){ | |
741 OUTREG(r200_def_gamma[i].gammaReg, | |
742 (r200_def_gamma[i].gammaSlope<<16) | | |
743 r200_def_gamma[i].gammaOffset); | |
744 } | |
745 } | |
746 } | |
747 #endif | |
748 | |
749 static void radeon_vid_make_default(void) | |
750 { | |
751 #ifdef RAGE128 | |
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changeset
|
752 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 753 #else |
754 make_default_gamma_correction(); | |
755 #endif | |
756 besr.deinterlace_pattern = 0x900AAAAA; | |
757 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
758 besr.deinterlace_on=1; | |
759 besr.double_buff=1; | |
4869 | 760 besr.ckey_on=0; |
761 besr.graphics_key_msk=0; | |
762 besr.graphics_key_clr=0; | |
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Fixed color key definitions. Waiting for new bugreports ;)
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|
763 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 764 } |
765 | |
766 | |
767 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
768 | |
4107 | 769 static unsigned short ati_card_ids[] = |
3996 | 770 { |
771 #ifdef RAGE128 | |
772 /* | |
773 This driver should be compatible with Rage128 (pro) chips. | |
774 (include adaptive deinterlacing!!!). | |
775 Moreover: the same logic can be used with Mach64 chips. | |
776 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
777 but they are incompatible by i/o ports. So if enthusiasts will want | |
778 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
779 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
780 fourccs (422 and 420 formats only). | |
781 */ | |
782 /* Rage128 Pro GL */ | |
4107 | 783 DEVICE_ATI_RAGE_128_PA_PRO, |
784 DEVICE_ATI_RAGE_128_PB_PRO, | |
785 DEVICE_ATI_RAGE_128_PC_PRO, | |
786 DEVICE_ATI_RAGE_128_PD_PRO, | |
787 DEVICE_ATI_RAGE_128_PE_PRO, | |
788 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 789 /* Rage128 Pro VR */ |
4107 | 790 DEVICE_ATI_RAGE_128_PG_PRO, |
791 DEVICE_ATI_RAGE_128_PH_PRO, | |
792 DEVICE_ATI_RAGE_128_PI_PRO, | |
793 DEVICE_ATI_RAGE_128_PJ_PRO, | |
794 DEVICE_ATI_RAGE_128_PK_PRO, | |
795 DEVICE_ATI_RAGE_128_PL_PRO, | |
796 DEVICE_ATI_RAGE_128_PM_PRO, | |
797 DEVICE_ATI_RAGE_128_PN_PRO, | |
798 DEVICE_ATI_RAGE_128_PO_PRO, | |
799 DEVICE_ATI_RAGE_128_PP_PRO, | |
800 DEVICE_ATI_RAGE_128_PQ_PRO, | |
801 DEVICE_ATI_RAGE_128_PR_PRO, | |
802 DEVICE_ATI_RAGE_128_PS_PRO, | |
803 DEVICE_ATI_RAGE_128_PT_PRO, | |
804 DEVICE_ATI_RAGE_128_PU_PRO, | |
805 DEVICE_ATI_RAGE_128_PV_PRO, | |
806 DEVICE_ATI_RAGE_128_PW_PRO, | |
807 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 808 /* Rage128 GL */ |
4107 | 809 DEVICE_ATI_RAGE_128_RE_SG, |
810 DEVICE_ATI_RAGE_128_RF_SG, | |
811 DEVICE_ATI_RAGE_128_RG, | |
812 DEVICE_ATI_RAGE_128_RK_VR, | |
813 DEVICE_ATI_RAGE_128_RL_VR, | |
814 DEVICE_ATI_RAGE_128_SE_4X, | |
815 DEVICE_ATI_RAGE_128_SF_4X, | |
816 DEVICE_ATI_RAGE_128_SG_4X, | |
8854 | 817 DEVICE_ATI_RAGE_128_SH, |
4107 | 818 DEVICE_ATI_RAGE_128_SK_4X, |
819 DEVICE_ATI_RAGE_128_SL_4X, | |
820 DEVICE_ATI_RAGE_128_SM_4X, | |
8854 | 821 DEVICE_ATI_RAGE_128_4X, |
4107 | 822 DEVICE_ATI_RAGE_128_PRO, |
823 DEVICE_ATI_RAGE_128_PRO2, | |
5165
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rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
changeset
|
824 DEVICE_ATI_RAGE_128_PRO3, |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
5044
diff
changeset
|
825 /* these seem to be based on rage 128 instead of mach64 */ |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
5044
diff
changeset
|
826 DEVICE_ATI_RAGE_MOBILITY_M3, |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
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|
827 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 828 #else |
829 /* Radeons (indeed: Rage 256 Pro ;) */ | |
8855 | 830 DEVICE_ATI_RADEON_R100_QD, |
831 DEVICE_ATI_RADEON_R100_QE, | |
832 DEVICE_ATI_RADEON_R100_QF, | |
833 DEVICE_ATI_RADEON_R100_QG, | |
834 DEVICE_ATI_RADEON_VE_QY, | |
835 DEVICE_ATI_RADEON_VE_QZ, | |
8854 | 836 DEVICE_ATI_RADEON_MOBILITY_M7, |
837 DEVICE_ATI_RADEON_MOBILITY_M72, | |
4107 | 838 DEVICE_ATI_RADEON_MOBILITY_M6, |
839 DEVICE_ATI_RADEON_MOBILITY_M62, | |
10332 | 840 DEVICE_ATI_RADEON_MOBILITY_U1, |
8855 | 841 DEVICE_ATI_RADEON_R200_BB, |
842 DEVICE_ATI_RADEON_R200_QH, | |
843 DEVICE_ATI_RADEON_R200_QI, | |
844 DEVICE_ATI_RADEON_R200_QJ, | |
845 DEVICE_ATI_RADEON_R200_QK, | |
8854 | 846 DEVICE_ATI_RADEON_R200_QL, |
8855 | 847 DEVICE_ATI_RADEON_R200_QH2, |
848 DEVICE_ATI_RADEON_R200_QI2, | |
849 DEVICE_ATI_RADEON_R200_QJ2, | |
850 DEVICE_ATI_RADEON_R200_QK2, | |
8854 | 851 DEVICE_ATI_RADEON_RV200_QW, |
8855 | 852 DEVICE_ATI_RADEON_RV200_QX, |
853 DEVICE_ATI_RADEON_R250_ID, | |
854 DEVICE_ATI_RADEON_R250_IE, | |
855 DEVICE_ATI_RADEON_R250_IF, | |
856 DEVICE_ATI_RADEON_R250_IG, | |
857 DEVICE_ATI_RADEON_R250_LD, | |
858 DEVICE_ATI_RADEON_R250_LE, | |
859 DEVICE_ATI_RADEON_R250_LF, | |
860 DEVICE_ATI_RADEON_R250_LG, | |
861 DEVICE_ATI_RADEON_R300_ND, | |
862 DEVICE_ATI_RADEON_R300_NE, | |
863 DEVICE_ATI_RADEON_R300_NF, | |
864 DEVICE_ATI_RADEON_R300_NG | |
3996 | 865 #endif |
866 }; | |
867 | |
868 static int find_chip(unsigned chip_id) | |
869 { | |
870 unsigned i; | |
4107 | 871 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 872 { |
4107 | 873 if(chip_id == ati_card_ids[i]) return i; |
3996 | 874 } |
875 return -1; | |
876 } | |
877 | |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
878 static pciinfo_t pci_info; |
3996 | 879 static int probed=0; |
880 | |
881 vidix_capability_t def_cap = | |
882 { | |
883 #ifdef RAGE128 | |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
884 "BES driver for Rage128 cards", |
3996 | 885 #else |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
886 "BES driver for Radeon cards", |
3996 | 887 #endif |
4327 | 888 "Nick Kurshev", |
3996 | 889 TYPE_OUTPUT | TYPE_FX, |
4191 | 890 { 0, 0, 0, 0 }, |
4282 | 891 2048, |
892 2048, | |
3996 | 893 4, |
894 4, | |
895 -1, | |
4264 | 896 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 897 VENDOR_ATI, |
3996 | 898 0, |
899 { 0, 0, 0, 0} | |
900 }; | |
901 | |
902 | |
4191 | 903 int vixProbe( int verbose,int force ) |
3996 | 904 { |
905 pciinfo_t lst[MAX_PCI_DEVICES]; | |
906 unsigned i,num_pci; | |
907 int err; | |
4030 | 908 __verbose = verbose; |
3996 | 909 err = pci_scan(lst,&num_pci); |
910 if(err) | |
911 { | |
912 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
913 return err; | |
914 } | |
915 else | |
916 { | |
917 err = ENXIO; | |
918 for(i=0;i<num_pci;i++) | |
919 { | |
4107 | 920 if(lst[i].vendor == VENDOR_ATI) |
3996 | 921 { |
922 int idx; | |
4191 | 923 const char *dname; |
3996 | 924 idx = find_chip(lst[i].device); |
4191 | 925 if(idx == -1 && force == PROBE_NORMAL) continue; |
926 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
927 dname = dname ? dname : "Unknown chip"; | |
928 printf(RADEON_MSG" Found chip: %s\n",dname); | |
9767
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
929 if ((lst[i].command & PCI_COMMAND_IO) == 0) |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
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parents:
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diff
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|
930 { |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
931 printf("[radeon] Device is disabled, ignoring\n"); |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
932 continue; |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
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|
933 } |
3996 | 934 #ifndef RAGE128 |
4191 | 935 if(idx != -1) |
8855 | 936 { |
8876
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arpi
parents:
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diff
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|
937 switch(ati_card_ids[idx]) { |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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diff
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|
938 /* Original radeon */ |
026ed72206ba
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arpi
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8859
diff
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|
939 case DEVICE_ATI_RADEON_R100_QD: |
026ed72206ba
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arpi
parents:
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diff
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|
940 case DEVICE_ATI_RADEON_R100_QE: |
026ed72206ba
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arpi
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8859
diff
changeset
|
941 case DEVICE_ATI_RADEON_R100_QF: |
026ed72206ba
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arpi
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8859
diff
changeset
|
942 case DEVICE_ATI_RADEON_R100_QG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
943 RadeonFamily = 100; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
944 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
945 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
946 /* Radeon VE / Radeon Mobility */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
947 case DEVICE_ATI_RADEON_VE_QY: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
948 case DEVICE_ATI_RADEON_VE_QZ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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8859
diff
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|
949 case DEVICE_ATI_RADEON_MOBILITY_M6: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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diff
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|
950 case DEVICE_ATI_RADEON_MOBILITY_M62: |
10332 | 951 case DEVICE_ATI_RADEON_MOBILITY_U1: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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|
952 RadeonFamily = 120; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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diff
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|
953 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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diff
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|
954 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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diff
changeset
|
955 /* Radeon 7500 / Radeon Mobility 7500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
956 case DEVICE_ATI_RADEON_RV200_QW: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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8859
diff
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|
957 case DEVICE_ATI_RADEON_RV200_QX: |
026ed72206ba
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arpi
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diff
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|
958 case DEVICE_ATI_RADEON_MOBILITY_M7: |
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arpi
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diff
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|
959 case DEVICE_ATI_RADEON_MOBILITY_M72: |
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arpi
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|
960 RadeonFamily = 150; |
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patch which removes the rage_ckey_model fix and updates
arpi
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diff
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|
961 break; |
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patch which removes the rage_ckey_model fix and updates
arpi
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diff
changeset
|
962 |
026ed72206ba
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arpi
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diff
changeset
|
963 /* Radeon 8500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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8859
diff
changeset
|
964 case DEVICE_ATI_RADEON_R200_BB: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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|
965 case DEVICE_ATI_RADEON_R200_QH: |
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diff
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|
966 case DEVICE_ATI_RADEON_R200_QI: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
967 case DEVICE_ATI_RADEON_R200_QJ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
968 case DEVICE_ATI_RADEON_R200_QK: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
969 case DEVICE_ATI_RADEON_R200_QL: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
970 case DEVICE_ATI_RADEON_R200_QH2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
971 case DEVICE_ATI_RADEON_R200_QI2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
972 case DEVICE_ATI_RADEON_R200_QJ2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
973 case DEVICE_ATI_RADEON_R200_QK2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
974 RadeonFamily = 200; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
975 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
976 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
977 /* Radeon 9000 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
978 case DEVICE_ATI_RADEON_R250_ID: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
979 case DEVICE_ATI_RADEON_R250_IE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
980 case DEVICE_ATI_RADEON_R250_IF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
981 case DEVICE_ATI_RADEON_R250_IG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
982 case DEVICE_ATI_RADEON_R250_LD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
983 case DEVICE_ATI_RADEON_R250_LE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
984 case DEVICE_ATI_RADEON_R250_LF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
985 case DEVICE_ATI_RADEON_R250_LG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
986 RadeonFamily = 250; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
987 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
988 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
989 /* Radeon 9700 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
990 case DEVICE_ATI_RADEON_R300_ND: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
991 case DEVICE_ATI_RADEON_R300_NE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
992 case DEVICE_ATI_RADEON_R300_NF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
993 case DEVICE_ATI_RADEON_R300_NG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
changeset
|
994 RadeonFamily = 300; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
995 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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8859
diff
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|
996 default: |
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patch which removes the rage_ckey_model fix and updates
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|
997 break; |
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patch which removes the rage_ckey_model fix and updates
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diff
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|
998 } |
8855 | 999 } |
3996 | 1000 #endif |
4193 | 1001 if(force > PROBE_NORMAL) |
1002 { | |
1003 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
1004 if(idx == -1) | |
1005 #ifdef RAGE128 | |
4373 | 1006 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 1007 #else |
4373 | 1008 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 1009 #endif |
1010 } | |
4191 | 1011 def_cap.device_id = lst[i].device; |
3996 | 1012 err = 0; |
1013 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
1014 probed=1; | |
1015 break; | |
1016 } | |
1017 } | |
1018 } | |
1019 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
1020 return err; | |
1021 } | |
1022 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1023 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1024 |
3996 | 1025 int vixInit( void ) |
1026 { | |
4477 | 1027 int err; |
4012 | 1028 if(!probed) |
1029 { | |
1030 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
1031 return EINTR; | |
1032 } | |
1033 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 1034 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
1035 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1036 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
8942 | 1037 #ifdef RADEON |
1038 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ | |
1039 if (radeon_ram_size == 0 && | |
1040 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || | |
1041 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) | |
1042 { | |
1043 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); | |
1044 radeon_ram_size = 8192*1024; | |
1045 } | |
9240
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1046 #else |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1047 /* Rage Mobility (rage128) also has memsize bug */ |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1048 if (radeon_ram_size == 0 && |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1049 (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1050 def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1051 { |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1052 printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1053 radeon_ram_size = 8192*1024; |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1054 } |
8942 | 1055 #endif |
3996 | 1056 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
1057 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 1058 radeon_vid_make_default(); |
1059 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 1060 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
1061 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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diff
changeset
|
1062 |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1063 radeon_fifo_wait(3); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1064 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1065 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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parents:
8521
diff
changeset
|
1066 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1067 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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parents:
8521
diff
changeset
|
1068 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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parents:
8521
diff
changeset
|
1069 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1070 |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1071 #ifdef RADEON |
8859 | 1072 switch(RadeonFamily) |
1073 { | |
1074 case 100: | |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1075 case 120: |
8859 | 1076 case 150: |
1077 case 250: | |
1078 is_shift_required=1; | |
1079 break; | |
1080 default: | |
1081 break; | |
1082 } | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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diff
changeset
|
1083 #endif |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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diff
changeset
|
1084 |
9044 | 1085 /* XXX: hack, but it works for me (tm) */ |
1086 #if defined(RAGE128) && (WORDS_BIGENDIAN) | |
1087 /* code from gatos */ | |
1088 { | |
1089 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); | |
1090 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & | |
1091 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); | |
1092 | |
1093 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, | |
1094 // INREG(CONFIG_CNTL)); | |
1095 } | |
1096 #endif | |
1097 | |
6564
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remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1098 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1099 return 0; |
1100 } | |
1101 | |
1102 void vixDestroy( void ) | |
1103 { | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1104 /* remove colorkeying */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1105 radeon_fifo_wait(3); |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1106 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1107 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1108 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1109 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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diff
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|
1110 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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parents:
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diff
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|
1111 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
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diff
changeset
|
1112 |
9044 | 1113 #if defined(RAGE128) && (WORDS_BIGENDIAN) |
1114 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); | |
1115 // printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, | |
1116 // INREG(CONFIG_CNTL)); | |
1117 #endif | |
1118 | |
3996 | 1119 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 1120 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 1121 } |
1122 | |
1123 int vixGetCapability(vidix_capability_t *to) | |
1124 { | |
1125 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1126 return 0; | |
1127 } | |
1128 | |
6483 | 1129 /* |
1130 Full list of fourcc which are supported by Win2K redeon driver: | |
6564
652ada9f9b66
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alex
parents:
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diff
changeset
|
1131 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1132 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1133 */ | |
3996 | 1134 uint32_t supported_fourcc[] = |
1135 { | |
6483 | 1136 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1137 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1138 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1139 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1140 IMGFMT_RGB16, IMGFMT_BGR16, |
1141 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1142 }; |
1143 | |
6483 | 1144 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1145 { |
6483 | 1146 unsigned int i; |
3996 | 1147 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1148 { | |
1149 if(fourcc==supported_fourcc[i]) return 1; | |
1150 } | |
1151 return 0; | |
1152 } | |
1153 | |
1154 int vixQueryFourcc(vidix_fourcc_t *to) | |
1155 { | |
1156 if(is_supported_fourcc(to->fourcc)) | |
1157 { | |
1158 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1159 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1160 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1161 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1162 VID_DEPTH_32BPP; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
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5041
diff
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|
1163 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1164 return 0; |
1165 } | |
4015 | 1166 else to->depth = to->flags = 0; |
3996 | 1167 return ENOSYS; |
1168 } | |
1169 | |
1170 static void radeon_vid_dump_regs( void ) | |
1171 { | |
1172 size_t i; | |
4015 | 1173 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1174 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1175 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1176 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1177 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1178 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1179 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1180 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1181 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1182 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1183 } |
1184 | |
1185 static void radeon_vid_stop_video( void ) | |
1186 { | |
1187 radeon_engine_idle(); | |
1188 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1189 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1190 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1191 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
8857
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Reduce flickering on window movement (from Christophe Badina)
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diff
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|
1192 #ifdef RADEON |
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diff
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1193 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); |
8857
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Reduce flickering on window movement (from Christophe Badina)
arpi
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1194 #else |
3996 | 1195 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
8857
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Reduce flickering on window movement (from Christophe Badina)
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diff
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1196 #endif |
3996 | 1197 OUTREG(OV0_TEST, 0); |
1198 } | |
1199 | |
1200 static void radeon_vid_display_video( void ) | |
1201 { | |
1202 int bes_flags; | |
1203 radeon_fifo_wait(2); | |
1204 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1205 radeon_engine_idle(); | |
1206 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1207 radeon_fifo_wait(15); | |
4666 | 1208 |
1209 /* Shutdown capturing */ | |
1210 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1211 OUTREG(CAP0_TRIG_CNTL, 0); | |
1212 | |
4689 | 1213 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1214 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1215 |
3996 | 1216 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1217 | |
4611 | 1218 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1219 #ifdef RAGE128 |
7493 | 1220 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1221 (((besr.saturation*31+31000)/2000) << 8) | | |
1222 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1223 #endif |
1224 radeon_fifo_wait(2); | |
4869 | 1225 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1226 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1227 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1228 |
1229 OUTREG(OV0_H_INC, besr.h_inc); | |
1230 OUTREG(OV0_STEP_BY, besr.step_by); | |
1231 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1232 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1233 OUTREG(OV0_V_INC, besr.v_inc); | |
1234 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1235 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1236 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1237 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1238 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1239 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1240 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1241 #ifdef RADEON | |
1242 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1243 #endif | |
4930 | 1244 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1245 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1246 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1247 radeon_fifo_wait(9); |
4930 | 1248 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1249 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1250 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1251 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1252 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1253 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1254 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1255 | |
6678 | 1256 #ifdef RADEON |
1257 bes_flags = SCALER_ENABLE | | |
1258 SCALER_SMART_SWITCH; | |
1259 // SCALER_HORZ_PICK_NEAREST | | |
1260 // SCALER_VERT_PICK_NEAREST | | |
1261 #endif | |
3996 | 1262 bes_flags = SCALER_ENABLE | |
1263 SCALER_SMART_SWITCH | | |
1264 SCALER_Y2R_TEMP | | |
1265 SCALER_PIX_EXPAND; | |
1266 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1267 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1268 #ifdef RAGE128 | |
1269 bes_flags |= SCALER_BURST_PER_PLANE; | |
1270 #endif | |
1271 switch(besr.fourcc) | |
1272 { | |
1273 case IMGFMT_RGB15: | |
1274 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1275 case IMGFMT_RGB16: |
3996 | 1276 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1277 /* |
3996 | 1278 case IMGFMT_RGB24: |
1279 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1280 */ |
3996 | 1281 case IMGFMT_RGB32: |
1282 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1283 /* 4:1:0 */ |
3996 | 1284 case IMGFMT_IF09: |
1285 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1286 /* 4:0:0 */ |
1287 case IMGFMT_Y800: | |
1288 case IMGFMT_Y8: | |
3996 | 1289 /* 4:2:0 */ |
1290 case IMGFMT_IYUV: | |
1291 case IMGFMT_I420: | |
6483 | 1292 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1293 /* 4:2:2 */ |
4455 | 1294 case IMGFMT_YVYU: |
3996 | 1295 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1296 case IMGFMT_YUY2: | |
1297 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1298 } | |
1299 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1300 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1301 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1302 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1303 } |
1304 | |
4456 | 1305 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1306 { |
4456 | 1307 unsigned pitch,spy,spv,spu; |
1308 spy = spv = spu = 0; | |
1309 switch(spitch->y) | |
1310 { | |
1311 case 16: | |
1312 case 32: | |
1313 case 64: | |
1314 case 128: | |
1315 case 256: spy = spitch->y; break; | |
1316 default: break; | |
1317 } | |
1318 switch(spitch->u) | |
1319 { | |
1320 case 16: | |
1321 case 32: | |
1322 case 64: | |
1323 case 128: | |
1324 case 256: spu = spitch->u; break; | |
1325 default: break; | |
1326 } | |
1327 switch(spitch->v) | |
1328 { | |
1329 case 16: | |
1330 case 32: | |
1331 case 64: | |
1332 case 128: | |
1333 case 256: spv = spitch->v; break; | |
1334 default: break; | |
1335 } | |
4009 | 1336 switch(fourcc) |
1337 { | |
1338 /* 4:2:0 */ | |
1339 case IMGFMT_IYUV: | |
1340 case IMGFMT_YV12: | |
4456 | 1341 case IMGFMT_I420: |
1342 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1343 else pitch = 32; | |
1344 break; | |
6483 | 1345 /* 4:1:0 */ |
1346 case IMGFMT_IF09: | |
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1347 case IMGFMT_YVU9: |
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1348 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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1349 else pitch = 64; |
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1350 break; |
4456 | 1351 default: |
1352 if(spy >= 16) pitch = spy; | |
1353 else pitch = 16; | |
1354 break; | |
4009 | 1355 } |
1356 return pitch; | |
1357 } | |
1358 | |
3996 | 1359 static int radeon_vid_init_video( vidix_playback_t *config ) |
1360 { | |
4930 | 1361 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1362 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1363 radeon_vid_stop_video(); |
1364 left = config->src.x << 16; | |
1365 top = config->src.y << 16; | |
1366 src_h = config->src.h; | |
1367 src_w = config->src.w; | |
6483 | 1368 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1369 if(config->fourcc == IMGFMT_YV12 || |
1370 config->fourcc == IMGFMT_I420 || | |
1371 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1372 if(config->fourcc == IMGFMT_YVU9 || |
1373 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1374 if(config->fourcc == IMGFMT_Y800 || | |
1375 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1376 if(config->fourcc == IMGFMT_RGB32 || |
1377 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1378 if(config->fourcc == IMGFMT_RGB32 || |
1379 config->fourcc == IMGFMT_BGR32 || | |
1380 config->fourcc == IMGFMT_RGB24 || | |
1381 config->fourcc == IMGFMT_BGR24 || | |
1382 config->fourcc == IMGFMT_RGB16 || | |
1383 config->fourcc == IMGFMT_BGR16 || | |
1384 config->fourcc == IMGFMT_RGB15 || | |
1385 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1386 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1387 mpitch = best_pitch-1; |
3996 | 1388 switch(config->fourcc) |
1389 { | |
6483 | 1390 /* 4:0:0 */ |
1391 case IMGFMT_Y800: | |
1392 case IMGFMT_Y8: | |
1393 /* 4:1:0 */ | |
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1394 case IMGFMT_YVU9: |
6483 | 1395 case IMGFMT_IF09: |
3996 | 1396 /* 4:2:0 */ |
1397 case IMGFMT_IYUV: | |
1398 case IMGFMT_YV12: | |
4415 | 1399 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1400 config->dest.pitch.y = |
1401 config->dest.pitch.u = | |
4415 | 1402 config->dest.pitch.v = best_pitch; |
3996 | 1403 break; |
4416 | 1404 /* RGB 4:4:4:4 */ |
1405 case IMGFMT_RGB32: | |
1406 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1407 config->dest.pitch.y = | |
1408 config->dest.pitch.u = | |
1409 config->dest.pitch.v = best_pitch; | |
1410 break; | |
3996 | 1411 /* 4:2:2 */ |
4455 | 1412 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1413 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1414 config->dest.pitch.y = |
1415 config->dest.pitch.u = | |
4415 | 1416 config->dest.pitch.v = best_pitch; |
3996 | 1417 break; |
1418 } | |
1419 dest_w = config->dest.w; | |
1420 dest_h = config->dest.h; | |
1421 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1422 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1423 besr.fourcc = config->fourcc; | |
1424 besr.v_inc = (src_h << 20) / dest_h; | |
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1425 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1426 h_inc = (src_w << 12) / dest_w; |
9544
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1427 |
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1428 { |
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1429 unsigned int ecp_div; |
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1430 ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; |
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1431 h_inc <<= ecp_div; |
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1432 } |
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1433 |
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1434 |
3996 | 1435 step_by = 1; |
1436 while(h_inc >= (2 << 12)) { | |
1437 step_by++; | |
1438 h_inc >>= 1; | |
1439 } | |
1440 | |
1441 /* keep everything in 16.16 */ | |
4015 | 1442 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1443 config->offsets[0] = 0; |
4930 | 1444 for(i=1;i<besr.vid_nbufs;i++) |
1445 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1446 if(is_420 || is_410 || is_400) |
3996 | 1447 { |
1448 uint32_t d1line,d2line,d3line; | |
1449 d1line = top*pitch; | |
6483 | 1450 if(is_420) |
1451 { | |
1452 d2line = src_h*pitch+(d1line>>2); | |
1453 d3line = d2line+((src_h*pitch)>>2); | |
1454 } | |
1455 else | |
1456 if(is_410) | |
1457 { | |
1458 d2line = src_h*pitch+(d1line>>4); | |
1459 d3line = d2line+((src_h*pitch)>>4); | |
1460 } | |
1461 else | |
1462 { | |
1463 d2line = 0; | |
1464 d3line = 0; | |
1465 } | |
3996 | 1466 d1line += (left >> 16) & ~15; |
6483 | 1467 if(is_420) |
1468 { | |
1469 d2line += (left >> 17) & ~15; | |
1470 d3line += (left >> 17) & ~15; | |
1471 } | |
1472 else | |
1473 if(is_410) | |
1474 { | |
1475 d2line += (left >> 18) & ~15; | |
1476 d3line += (left >> 18) & ~15; | |
1477 } | |
3996 | 1478 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1479 if(is_400) |
1480 { | |
1481 config->offset.v = 0; | |
1482 config->offset.u = 0; | |
1483 } | |
1484 else | |
1485 { | |
1486 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1487 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1488 } | |
4930 | 1489 for(i=0;i<besr.vid_nbufs;i++) |
1490 { | |
1491 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1492 if(is_400) |
1493 { | |
1494 besr.vid_buf_base_adrs_v[i]=0; | |
1495 besr.vid_buf_base_adrs_u[i]=0; | |
1496 } | |
1497 else | |
1498 { | |
9892 | 1499 if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1500 { | |
1501 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1502 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1503 } | |
1504 else | |
1505 { | |
1506 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1507 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1508 } | |
6483 | 1509 } |
4930 | 1510 } |
1511 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1512 if(is_400) |
1513 { | |
1514 config->offset.v = 0; | |
1515 config->offset.u = 0; | |
1516 } | |
1517 else | |
1518 { | |
1519 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1520 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1521 } | |
3996 | 1522 } |
1523 else | |
1524 { | |
1525 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1526 for(i=0;i<besr.vid_nbufs;i++) |
1527 { | |
1528 besr.vid_buf_base_adrs_y[i] = | |
1529 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1530 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1531 } |
3996 | 1532 } |
1533 | |
1534 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1535 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1536 ((tmp << 12) & 0xf0000000); | |
1537 | |
1538 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1539 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1540 ((tmp << 12) & 0x70000000); | |
1541 tmp = (top & 0x0000ffff) + 0x00018000; | |
1542 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1543 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1544 | |
1545 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1546 besr.p23_v_accum_init = (is_420||is_410) ? |
1547 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1548 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1549 | |
6483 | 1550 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1551 left = (left >> 16) & 15; |
4571 | 1552 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1553 if(is_rgb32) |
4571 | 1554 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1555 else |
6483 | 1556 if(is_410) |
1557 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1558 else | |
4416 | 1559 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1560 besr.step_by = step_by | (step_by << 8); |
1561 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1562 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1563 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1564 if(is_420 || is_410) |
3996 | 1565 { |
6483 | 1566 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1567 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1568 } | |
1569 else besr.p23_blank_lines_at_top = 0; | |
1570 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1571 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1572 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1573 if (is_410||is_420) src_w>>=is_410?2:1; |
1574 if(is_400) | |
1575 { | |
1576 besr.p2_x_start_end = 0; | |
1577 besr.p3_x_start_end = 0; | |
1578 } | |
1579 else | |
1580 { | |
1581 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1582 besr.p3_x_start_end = besr.p2_x_start_end; | |
1583 } | |
4869 | 1584 |
3996 | 1585 return 0; |
1586 } | |
1587 | |
4009 | 1588 static void radeon_compute_framesize(vidix_playback_t *info) |
1589 { | |
4666 | 1590 unsigned pitch,awidth,dbpp; |
4456 | 1591 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1592 dbpp = radeon_vid_get_dbpp(); |
4033 | 1593 switch(info->fourcc) |
1594 { | |
1595 case IMGFMT_I420: | |
1596 case IMGFMT_YV12: | |
1597 case IMGFMT_IYUV: | |
4666 | 1598 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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arpi
parents:
5165
diff
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|
1599 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1600 break; |
6483 | 1601 case IMGFMT_Y800: |
1602 case IMGFMT_Y8: | |
1603 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1604 info->frame_size = awidth*info->src.h; | |
1605 break; | |
1606 case IMGFMT_IF09: | |
1607 case IMGFMT_YVU9: | |
1608 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1609 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1610 break; | |
4429 | 1611 case IMGFMT_RGB32: |
1612 case IMGFMT_BGR32: | |
4666 | 1613 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1614 info->frame_size = awidth*info->src.h; |
4429 | 1615 break; |
1616 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1617 default: |
1618 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1619 info->frame_size = awidth*info->src.h; |
4033 | 1620 break; |
1621 } | |
4009 | 1622 } |
1623 | |
3996 | 1624 int vixConfigPlayback(vidix_playback_t *info) |
1625 { | |
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1626 unsigned rgb_size,nfr; |
3996 | 1627 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1628 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1629 if(info->num_frames==1) besr.double_buff=0; |
1630 else besr.double_buff=1; | |
4009 | 1631 radeon_compute_framesize(info); |
4930 | 1632 |
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1633 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1634 nfr = info->num_frames; |
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1635 for(;nfr>0; nfr--) |
4930 | 1636 { |
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1637 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1638 radeon_overlay_off &= 0xffff0000; |
1639 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1640 } | |
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1641 if(nfr <= 3) |
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1642 { |
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1643 nfr = info->num_frames; |
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1644 for(;nfr>0; nfr--) |
4930 | 1645 { |
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1646 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1647 radeon_overlay_off &= 0xffff0000; |
1648 if(radeon_overlay_off > 0) break; | |
1649 } | |
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1650 } |
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1651 if(nfr <= 0) return EINVAL; |
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1652 info->num_frames = nfr; |
4930 | 1653 besr.vid_nbufs = info->num_frames; |
1654 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1655 radeon_vid_init_video(info); |
1656 return 0; | |
1657 } | |
1658 | |
1659 int vixPlaybackOn( void ) | |
1660 { | |
1661 radeon_vid_display_video(); | |
1662 return 0; | |
1663 } | |
1664 | |
1665 int vixPlaybackOff( void ) | |
1666 { | |
1667 radeon_vid_stop_video(); | |
1668 return 0; | |
1669 } | |
1670 | |
4033 | 1671 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1672 { |
4412 | 1673 uint32_t off[6]; |
4930 | 1674 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1675 /* |
1676 buf3-5 always should point onto second buffer for better | |
1677 deinterlacing and TV-in | |
1678 */ | |
4666 | 1679 if(!besr.double_buff) return 0; |
4930 | 1680 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1681 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1682 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1683 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1684 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1685 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1686 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1687 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1688 radeon_fifo_wait(8); |
3996 | 1689 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1690 radeon_engine_idle(); |
3996 | 1691 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1692 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1693 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1694 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1695 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1696 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1697 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1698 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1699 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1700 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1701 return 0; |
1702 } | |
1703 | |
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1704 vidix_video_eq_t equal = |
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1705 { |
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1706 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1707 #ifndef RAGE128 |
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1708 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1709 #endif |
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1710 , |
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1711 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1712 |
1713 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1714 { | |
1715 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1716 return 0; | |
1717 } | |
1718 | |
4229 | 1719 #ifndef RAGE128 |
1720 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1721 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1722 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1723 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1724 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1725 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1726 #endif | |
1727 | |
3996 | 1728 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1729 { | |
1730 #ifdef RAGE128 | |
1731 int br,sat; | |
4229 | 1732 #else |
1733 int itu_space; | |
3996 | 1734 #endif |
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1735 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1736 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1737 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1738 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1739 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1740 { |
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1741 equal.red_intensity = eq->red_intensity; |
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1742 equal.green_intensity = eq->green_intensity; |
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1743 equal.blue_intensity = eq->blue_intensity; |
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1744 } |
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1745 equal.flags = eq->flags; |
3996 | 1746 #ifdef RAGE128 |
1747 br = equal.brightness * 64 / 1000; | |
4229 | 1748 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1749 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1750 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1751 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1752 #else | |
4229 | 1753 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1754 RTFCheckParam(equal.brightness); | |
1755 RTFCheckParam(equal.saturation); | |
1756 RTFCheckParam(equal.contrast); | |
1757 RTFCheckParam(equal.hue); | |
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1758 RTFCheckParam(equal.red_intensity); |
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1759 RTFCheckParam(equal.green_intensity); |
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1760 RTFCheckParam(equal.blue_intensity); |
4229 | 1761 radeon_set_transform(RTFBrightness(equal.brightness), |
1762 RTFContrast(equal.contrast), | |
1763 RTFSaturation(equal.saturation), | |
1764 RTFHue(equal.hue), | |
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1765 RTFIntensity(equal.red_intensity), |
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1766 RTFIntensity(equal.green_intensity), |
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1767 RTFIntensity(equal.blue_intensity), |
4229 | 1768 itu_space); |
3996 | 1769 #endif |
1770 return 0; | |
1771 } | |
1772 | |
4611 | 1773 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1774 { | |
1775 unsigned sflg; | |
1776 switch(info->flags) | |
1777 { | |
1778 default: | |
1779 case CFG_NON_INTERLACED: | |
1780 besr.deinterlace_on = 0; | |
1781 break; | |
1782 case CFG_EVEN_ODD_INTERLACING: | |
1783 case CFG_INTERLACED: | |
1784 besr.deinterlace_on = 1; | |
1785 besr.deinterlace_pattern = 0x900AAAAA; | |
1786 break; | |
1787 case CFG_ODD_EVEN_INTERLACING: | |
1788 besr.deinterlace_on = 1; | |
1789 besr.deinterlace_pattern = 0x00055555; | |
1790 break; | |
1791 case CFG_UNIQUE_INTERLACING: | |
1792 besr.deinterlace_on = 1; | |
1793 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1794 break; | |
1795 } | |
1796 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1797 radeon_engine_idle(); | |
1798 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1799 radeon_fifo_wait(15); | |
1800 sflg = INREG(OV0_SCALE_CNTL); | |
1801 if(besr.deinterlace_on) | |
1802 { | |
1803 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1804 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1805 } | |
1806 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1807 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1808 return 0; | |
1809 } | |
1810 | |
1811 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1812 { | |
1813 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1814 else | |
1815 { | |
1816 info->flags = CFG_UNIQUE_INTERLACING; | |
1817 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1818 } | |
1819 return 0; | |
1820 } | |
4869 | 1821 |
1822 | |
1823 /* Graphic keys */ | |
1824 static vidix_grkey_t radeon_grkey; | |
1825 | |
1826 static void set_gr_key( void ) | |
1827 { | |
1828 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1829 { | |
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1830 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1831 besr.ckey_on=1; |
1832 | |
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1833 switch(dbpp) |
4869 | 1834 { |
1835 case 15: | |
8856 | 1836 #ifdef RADEON |
8858 | 1837 if(RadeonFamily > 100) |
8856 | 1838 besr.graphics_key_clr= |
1839 ((radeon_grkey.ckey.blue &0xF8)) | |
1840 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
1841 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1842 else | |
1843 #endif | |
4869 | 1844 besr.graphics_key_clr= |
1845 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1846 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
1847 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
1848 break; | |
1849 case 16: | |
8856 | 1850 #ifdef RADEON |
1851 /* This test may be too general/specific */ | |
8858 | 1852 if(RadeonFamily > 100) |
8856 | 1853 besr.graphics_key_clr= |
1854 ((radeon_grkey.ckey.blue &0xF8)) | |
1855 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
1856 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1857 else | |
1858 #endif | |
4869 | 1859 besr.graphics_key_clr= |
1860 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1861 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
1862 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
1863 break; | |
1864 case 24: | |
1865 besr.graphics_key_clr= | |
1866 ((radeon_grkey.ckey.blue &0xFF)) | |
1867 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1868 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1869 break; | |
1870 case 32: | |
1871 besr.graphics_key_clr= | |
1872 ((radeon_grkey.ckey.blue &0xFF)) | |
1873 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1874 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1875 break; | |
1876 default: | |
1877 besr.ckey_on=0; | |
1878 besr.graphics_key_msk=0; | |
1879 besr.graphics_key_clr=0; | |
1880 } | |
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1881 #ifdef RAGE128 |
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1882 besr.graphics_key_msk=(1<<dbpp)-1; |
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1883 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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1884 #else |
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1885 besr.graphics_key_msk=besr.graphics_key_clr; |
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1886 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; |
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1887 #endif |
4869 | 1888 } |
1889 else | |
1890 { | |
1891 besr.ckey_on=0; | |
1892 besr.graphics_key_msk=0; | |
1893 besr.graphics_key_clr=0; | |
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1894 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 1895 } |
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1896 radeon_fifo_wait(3); |
4869 | 1897 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1898 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1899 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1900 } | |
1901 | |
1902 int vixGetGrKeys(vidix_grkey_t *grkey) | |
1903 { | |
1904 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
1905 return(0); | |
1906 } | |
1907 | |
1908 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
1909 { | |
1910 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
1911 set_gr_key(); | |
1912 return(0); | |
1913 } |