Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 8942:f381dbfd277e
M6 bug workaround by Hanno Bock <hanno@gmx.de>
author | alex |
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date | Mon, 13 Jan 2003 10:21:22 +0000 |
parents | 026ed72206ba |
children | 59b1bd7ccae1 |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
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6 PPC support by Alex Beregszaszi |
3996 | 7 */ |
8 | |
9 #include <errno.h> | |
10 #include <stdio.h> | |
11 #include <stdlib.h> | |
12 #include <string.h> | |
13 #include <math.h> | |
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14 #include <inttypes.h> |
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15 |
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16 #include "../../config.h" |
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17 #include "../../bswap.h" |
4201 | 18 #include "../../libdha/pci_ids.h" |
19 #include "../../libdha/pci_names.h" | |
3996 | 20 #include "../vidix.h" |
21 #include "../fourcc.h" | |
22 #include "../../libdha/libdha.h" | |
23 #include "radeon.h" | |
24 | |
25 #ifdef RAGE128 | |
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26 #define RADEON_MSG "[rage128]" |
3996 | 27 #define X_ADJUST 0 |
28 #else | |
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29 #define RADEON_MSG "[radeon]" |
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30 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 31 #ifndef RADEON |
32 #define RADEON | |
33 #endif | |
34 #endif | |
35 | |
4030 | 36 static int __verbose = 0; |
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37 #ifdef RADEON |
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38 static int is_shift_required = 0; |
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39 #endif |
4015 | 40 |
3996 | 41 typedef struct bes_registers_s |
42 { | |
43 /* base address of yuv framebuffer */ | |
44 uint32_t yuv_base; | |
45 uint32_t fourcc; | |
46 uint32_t dest_bpp; | |
47 /* YUV BES registers */ | |
48 uint32_t reg_load_cntl; | |
49 uint32_t h_inc; | |
50 uint32_t step_by; | |
51 uint32_t y_x_start; | |
52 uint32_t y_x_end; | |
53 uint32_t v_inc; | |
54 uint32_t p1_blank_lines_at_top; | |
55 uint32_t p23_blank_lines_at_top; | |
56 uint32_t vid_buf_pitch0_value; | |
57 uint32_t vid_buf_pitch1_value; | |
58 uint32_t p1_x_start_end; | |
59 uint32_t p2_x_start_end; | |
60 uint32_t p3_x_start_end; | |
61 uint32_t base_addr; | |
4930 | 62 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
63 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
64 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
65 uint32_t vid_nbufs; | |
3996 | 66 |
67 uint32_t p1_v_accum_init; | |
68 uint32_t p1_h_accum_init; | |
69 uint32_t p23_v_accum_init; | |
70 uint32_t p23_h_accum_init; | |
71 uint32_t scale_cntl; | |
72 uint32_t exclusive_horz; | |
73 uint32_t auto_flip_cntl; | |
74 uint32_t filter_cntl; | |
75 uint32_t key_cntl; | |
76 uint32_t test; | |
77 /* Configurable stuff */ | |
78 int double_buff; | |
79 | |
80 int brightness; | |
81 int saturation; | |
82 | |
83 int ckey_on; | |
84 uint32_t graphics_key_clr; | |
85 uint32_t graphics_key_msk; | |
4869 | 86 uint32_t ckey_cntl; |
3996 | 87 |
88 int deinterlace_on; | |
89 uint32_t deinterlace_pattern; | |
90 | |
91 } bes_registers_t; | |
92 | |
93 typedef struct video_registers_s | |
94 { | |
95 const char * sname; | |
96 uint32_t name; | |
97 uint32_t value; | |
98 }video_registers_t; | |
99 | |
100 static bes_registers_t besr; | |
101 #ifndef RAGE128 | |
8855 | 102 static int RadeonFamily=100; |
3996 | 103 #endif |
104 #define DECLARE_VREG(name) { #name, name, 0 } | |
105 static video_registers_t vregs[] = | |
106 { | |
107 DECLARE_VREG(VIDEOMUX_CNTL), | |
108 DECLARE_VREG(VIPPAD_MASK), | |
109 DECLARE_VREG(VIPPAD1_A), | |
110 DECLARE_VREG(VIPPAD1_EN), | |
111 DECLARE_VREG(VIPPAD1_Y), | |
112 DECLARE_VREG(OV0_Y_X_START), | |
113 DECLARE_VREG(OV0_Y_X_END), | |
114 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
115 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
116 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
117 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
118 DECLARE_VREG(OV0_SCALE_CNTL), | |
119 DECLARE_VREG(OV0_V_INC), | |
120 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
121 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
122 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
123 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
124 #ifdef RADEON | |
125 DECLARE_VREG(OV0_BASE_ADDR), | |
126 #endif | |
127 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
128 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
129 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
130 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
131 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
132 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
133 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
134 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
135 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
136 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
137 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
138 DECLARE_VREG(OV0_H_INC), | |
139 DECLARE_VREG(OV0_STEP_BY), | |
140 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
141 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
142 DECLARE_VREG(OV0_P1_X_START_END), | |
143 DECLARE_VREG(OV0_P2_X_START_END), | |
144 DECLARE_VREG(OV0_P3_X_START_END), | |
145 DECLARE_VREG(OV0_FILTER_CNTL), | |
146 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
147 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
148 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
149 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
150 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
151 DECLARE_VREG(OV0_FLAG_CNTL), | |
152 #ifdef RAGE128 | |
153 DECLARE_VREG(OV0_COLOUR_CNTL), | |
154 #else | |
155 DECLARE_VREG(OV0_SLICE_CNTL), | |
156 #endif | |
157 DECLARE_VREG(OV0_VID_KEY_CLR), | |
158 DECLARE_VREG(OV0_VID_KEY_MSK), | |
159 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
160 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
161 DECLARE_VREG(OV0_KEY_CNTL), | |
162 DECLARE_VREG(OV0_TEST), | |
163 DECLARE_VREG(OV0_LIN_TRANS_A), | |
164 DECLARE_VREG(OV0_LIN_TRANS_B), | |
165 DECLARE_VREG(OV0_LIN_TRANS_C), | |
166 DECLARE_VREG(OV0_LIN_TRANS_D), | |
167 DECLARE_VREG(OV0_LIN_TRANS_E), | |
168 DECLARE_VREG(OV0_LIN_TRANS_F), | |
169 DECLARE_VREG(OV0_GAMMA_0_F), | |
170 DECLARE_VREG(OV0_GAMMA_10_1F), | |
171 DECLARE_VREG(OV0_GAMMA_20_3F), | |
172 DECLARE_VREG(OV0_GAMMA_40_7F), | |
173 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
174 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
175 DECLARE_VREG(SUBPIC_CNTL), | |
176 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
177 DECLARE_VREG(SUBPIC_Y_X_START), | |
178 DECLARE_VREG(SUBPIC_Y_X_END), | |
179 DECLARE_VREG(SUBPIC_V_INC), | |
180 DECLARE_VREG(SUBPIC_H_INC), | |
181 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
182 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
183 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
184 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
185 DECLARE_VREG(SUBPIC_PITCH), | |
186 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
187 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
188 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
189 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
190 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
191 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
192 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
193 DECLARE_VREG(IDCT_RUNS), | |
194 DECLARE_VREG(IDCT_LEVELS), | |
195 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
196 DECLARE_VREG(IDCT_AUTH), | |
197 DECLARE_VREG(IDCT_CONTROL) | |
198 }; | |
4030 | 199 |
3996 | 200 static void * radeon_mmio_base = 0; |
201 static void * radeon_mem_base = 0; | |
202 static int32_t radeon_overlay_off = 0; | |
203 static uint32_t radeon_ram_size = 0; | |
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204 /* Restore on exit */ |
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205 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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206 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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207 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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208 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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209 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
3996 | 210 |
4012 | 211 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
212 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
213 | |
214 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
215 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
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216 |
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217 static inline uint32_t INREG (uint32_t addr) { |
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218 uint32_t tmp = GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr); |
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219 return le2me_32(tmp); |
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220 } |
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221 //#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) |
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222 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,le2me_32(val)) |
3996 | 223 #define OUTREGP(addr,val,mask) \ |
224 do { \ | |
225 unsigned int _tmp = INREG(addr); \ | |
226 _tmp &= (mask); \ | |
227 _tmp |= (val); \ | |
228 OUTREG(addr, _tmp); \ | |
229 } while (0) | |
230 | |
4666 | 231 static __inline__ uint32_t INPLL(uint32_t addr) |
232 { | |
233 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
234 return (INREG(CLOCK_CNTL_DATA)); | |
235 } | |
236 | |
237 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
238 OUTREG(CLOCK_CNTL_DATA, val) | |
239 #define OUTPLLP(addr,val,mask) \ | |
240 do { \ | |
241 unsigned int _tmp = INPLL(addr); \ | |
242 _tmp &= (mask); \ | |
243 _tmp |= (val); \ | |
244 OUTPLL(addr, _tmp); \ | |
245 } while (0) | |
246 | |
3996 | 247 static uint32_t radeon_vid_get_dbpp( void ) |
248 { | |
249 uint32_t dbpp,retval; | |
250 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
251 switch(dbpp) | |
252 { | |
253 case DST_8BPP: retval = 8; break; | |
254 case DST_15BPP: retval = 15; break; | |
255 case DST_16BPP: retval = 16; break; | |
256 case DST_24BPP: retval = 24; break; | |
257 default: retval=32; break; | |
258 } | |
259 return retval; | |
260 } | |
261 | |
262 static int radeon_is_dbl_scan( void ) | |
263 { | |
264 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
265 } | |
266 | |
267 static int radeon_is_interlace( void ) | |
268 { | |
269 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
270 } | |
271 | |
4666 | 272 static uint32_t radeon_get_xres( void ) |
273 { | |
274 /* FIXME: currently we extract that from CRTC!!!*/ | |
275 uint32_t xres,h_total; | |
276 h_total = INREG(CRTC_H_TOTAL_DISP); | |
277 xres = (h_total >> 16) & 0xffff; | |
278 return (xres + 1)*8; | |
279 } | |
280 | |
281 static uint32_t radeon_get_yres( void ) | |
282 { | |
283 /* FIXME: currently we extract that from CRTC!!!*/ | |
284 uint32_t yres,v_total; | |
285 v_total = INREG(CRTC_V_TOTAL_DISP); | |
286 yres = (v_total >> 16) & 0xffff; | |
287 return yres + 1; | |
288 } | |
289 | |
4689 | 290 static void radeon_wait_vsync(void) |
291 { | |
292 int i; | |
293 | |
294 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
295 for (i = 0; i < 2000000; i++) | |
296 { | |
297 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
298 } | |
299 } | |
300 | |
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301 #ifdef RAGE128 |
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302 static void _radeon_engine_idle(void); |
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303 static void _radeon_fifo_wait(unsigned); |
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304 #define radeon_engine_idle() _radeon_engine_idle() |
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305 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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306 /* Flush all dirty data in the Pixel Cache to memory. */ |
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307 static __inline__ void radeon_engine_flush ( void ) |
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308 { |
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309 unsigned i; |
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310 |
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311 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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312 for (i = 0; i < 2000000; i++) { |
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313 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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314 } |
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315 } |
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316 |
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317 /* Reset graphics card to known state. */ |
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318 static void radeon_engine_reset( void ) |
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319 { |
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320 uint32_t clock_cntl_index; |
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321 uint32_t mclk_cntl; |
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322 uint32_t gen_reset_cntl; |
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323 |
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324 radeon_engine_flush(); |
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325 |
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326 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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327 mclk_cntl = INPLL(MCLK_CNTL); |
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328 |
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329 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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330 |
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331 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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332 |
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333 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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334 INREG(GEN_RESET_CNTL); |
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335 OUTREG(GEN_RESET_CNTL, |
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336 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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337 INREG(GEN_RESET_CNTL); |
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338 |
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339 OUTPLL(MCLK_CNTL, mclk_cntl); |
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340 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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341 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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342 } |
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343 #else |
4689 | 344 |
3996 | 345 static __inline__ void radeon_engine_flush ( void ) |
346 { | |
347 int i; | |
348 | |
349 /* initiate flush */ | |
350 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
351 ~RB2D_DC_FLUSH_ALL); | |
352 | |
353 for (i=0; i < 2000000; i++) { | |
354 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
355 break; | |
356 } | |
357 } | |
358 | |
4666 | 359 static void _radeon_engine_idle(void); |
360 static void _radeon_fifo_wait(unsigned); | |
361 #define radeon_engine_idle() _radeon_engine_idle() | |
362 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 363 |
4666 | 364 static void radeon_engine_reset( void ) |
3996 | 365 { |
4666 | 366 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
367 | |
368 radeon_engine_flush (); | |
369 | |
370 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
371 mclk_cntl = INPLL(MCLK_CNTL); | |
372 | |
373 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
374 FORCEON_MCLKA | | |
375 FORCEON_MCLKB | | |
376 FORCEON_YCLKA | | |
377 FORCEON_YCLKB | | |
378 FORCEON_MC | | |
379 FORCEON_AIC)); | |
380 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 381 |
4666 | 382 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
383 SOFT_RESET_CP | | |
384 SOFT_RESET_HI | | |
385 SOFT_RESET_SE | | |
386 SOFT_RESET_RE | | |
387 SOFT_RESET_PP | | |
388 SOFT_RESET_E2 | | |
389 SOFT_RESET_RB | | |
390 SOFT_RESET_HDP); | |
391 INREG(RBBM_SOFT_RESET); | |
392 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
393 ~(SOFT_RESET_CP | | |
394 SOFT_RESET_HI | | |
395 SOFT_RESET_SE | | |
396 SOFT_RESET_RE | | |
397 SOFT_RESET_PP | | |
398 SOFT_RESET_E2 | | |
399 SOFT_RESET_RB | | |
400 SOFT_RESET_HDP)); | |
401 INREG(RBBM_SOFT_RESET); | |
402 | |
403 OUTPLL(MCLK_CNTL, mclk_cntl); | |
404 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
405 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
406 | |
407 return; | |
3996 | 408 } |
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409 #endif |
4666 | 410 static void radeon_engine_restore( void ) |
3996 | 411 { |
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412 #ifndef RAGE128 |
4666 | 413 int pitch64; |
414 uint32_t xres,yres,bpp; | |
415 radeon_fifo_wait(1); | |
416 xres = radeon_get_xres(); | |
417 yres = radeon_get_yres(); | |
418 bpp = radeon_vid_get_dbpp(); | |
419 /* turn of all automatic flushing - we'll do it all */ | |
420 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
421 | |
422 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
423 | |
424 radeon_fifo_wait(1); | |
425 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
426 (pitch64 << 22)); | |
427 | |
428 radeon_fifo_wait(1); | |
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429 //#if defined(__BIG_ENDIAN) |
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430 #if defined(WORDS_BIGENDIAN) |
4666 | 431 OUTREGP(DP_DATATYPE, |
432 HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
433 #else | |
434 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
435 #endif | |
436 | |
437 radeon_fifo_wait(1); | |
438 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
439 | DEFAULT_SC_BOTTOM_MAX)); | |
440 radeon_fifo_wait(1); | |
441 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
442 | GMC_BRUSH_SOLID_COLOR | |
443 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 444 |
4666 | 445 radeon_fifo_wait(7); |
446 OUTREG(DST_LINE_START, 0); | |
447 OUTREG(DST_LINE_END, 0); | |
448 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
449 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
450 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
451 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
452 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
453 | |
454 radeon_engine_idle(); | |
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455 #endif |
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456 } |
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457 #ifdef RAGE128 |
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458 static void _radeon_fifo_wait (unsigned entries) |
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459 { |
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460 unsigned i; |
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461 |
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462 for(;;) |
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463 { |
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464 for (i=0; i<2000000; i++) |
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465 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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466 return; |
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467 radeon_engine_reset(); |
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468 radeon_engine_restore(); |
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469 } |
4666 | 470 } |
471 | |
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472 static void _radeon_engine_idle ( void ) |
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473 { |
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474 unsigned i; |
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475 |
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476 /* ensure FIFO is empty before waiting for idle */ |
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477 radeon_fifo_wait (64); |
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478 for(;;) |
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479 { |
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480 for (i=0; i<2000000; i++) { |
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481 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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482 radeon_engine_flush (); |
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483 return; |
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484 } |
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485 } |
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486 radeon_engine_reset(); |
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487 radeon_engine_restore(); |
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488 } |
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489 } |
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490 #else |
4666 | 491 static void _radeon_fifo_wait (unsigned entries) |
492 { | |
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493 unsigned i; |
3996 | 494 |
4666 | 495 for(;;) |
496 { | |
497 for (i=0; i<2000000; i++) | |
498 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
499 return; | |
500 radeon_engine_reset(); | |
501 radeon_engine_restore(); | |
502 } | |
503 } | |
504 static void _radeon_engine_idle ( void ) | |
505 { | |
506 int i; | |
507 | |
508 /* ensure FIFO is empty before waiting for idle */ | |
509 radeon_fifo_wait (64); | |
510 for(;;) | |
511 { | |
3996 | 512 for (i=0; i<2000000; i++) { |
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513 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 514 radeon_engine_flush (); |
515 return; | |
516 } | |
517 } | |
4666 | 518 radeon_engine_reset(); |
519 radeon_engine_restore(); | |
520 } | |
3996 | 521 } |
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522 #endif |
3996 | 523 |
524 #ifndef RAGE128 | |
525 /* Reference color space transform data */ | |
526 typedef struct tagREF_TRANSFORM | |
527 { | |
528 float RefLuma; | |
529 float RefRCb; | |
530 float RefRCr; | |
531 float RefGCb; | |
532 float RefGCr; | |
533 float RefBCb; | |
534 float RefBCr; | |
535 } REF_TRANSFORM; | |
536 | |
537 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
538 REF_TRANSFORM trans[2] = | |
539 { | |
540 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
541 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
542 }; | |
543 /**************************************************************************** | |
544 * SetTransform * | |
545 * Function: Calculates and sets color space transform from supplied * | |
546 * reference transform, gamma, brightness, contrast, hue and * | |
547 * saturation. * | |
548 * Inputs: bright - brightness * | |
549 * cont - contrast * | |
550 * sat - saturation * | |
551 * hue - hue * | |
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552 * red_intensity - intense of red component * |
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553 * green_intensity - intense of green component * |
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554 * blue_intensity - intense of blue component * |
3996 | 555 * ref - index to the table of refernce transforms * |
556 * Outputs: NONE * | |
557 ****************************************************************************/ | |
558 | |
559 static void radeon_set_transform(float bright, float cont, float sat, | |
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560 float hue, float red_intensity, |
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561 float green_intensity,float blue_intensity, |
4284 | 562 unsigned ref) |
3996 | 563 { |
564 float OvHueSin, OvHueCos; | |
565 float CAdjLuma, CAdjOff; | |
4284 | 566 float RedAdj,GreenAdj,BlueAdj; |
3996 | 567 float CAdjRCb, CAdjRCr; |
568 float CAdjGCb, CAdjGCr; | |
569 float CAdjBCb, CAdjBCr; | |
570 float OvLuma, OvROff, OvGOff, OvBOff; | |
571 float OvRCb, OvRCr; | |
572 float OvGCb, OvGCr; | |
573 float OvBCb, OvBCr; | |
574 float Loff = 64.0; | |
575 float Coff = 512.0f; | |
576 | |
577 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
578 uint32_t dwOvRCb, dwOvRCr; | |
579 uint32_t dwOvGCb, dwOvGCr; | |
580 uint32_t dwOvBCb, dwOvBCr; | |
581 | |
582 if (ref >= 2) return; | |
583 | |
584 OvHueSin = sin((double)hue); | |
585 OvHueCos = cos((double)hue); | |
586 | |
587 CAdjLuma = cont * trans[ref].RefLuma; | |
588 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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589 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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590 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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591 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 592 |
593 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
594 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
595 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
596 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
597 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
598 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
599 | |
600 #if 0 /* default constants */ | |
601 CAdjLuma = 1.16455078125; | |
602 | |
603 CAdjRCb = 0.0; | |
604 CAdjRCr = 1.59619140625; | |
605 CAdjGCb = -0.39111328125; | |
606 CAdjGCr = -0.8125; | |
607 CAdjBCb = 2.01708984375; | |
608 CAdjBCr = 0; | |
609 #endif | |
610 OvLuma = CAdjLuma; | |
611 OvRCb = CAdjRCb; | |
612 OvRCr = CAdjRCr; | |
613 OvGCb = CAdjGCb; | |
614 OvGCr = CAdjGCr; | |
615 OvBCb = CAdjBCb; | |
616 OvBCr = CAdjBCr; | |
4284 | 617 OvROff = RedAdj + CAdjOff - |
3996 | 618 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 619 OvGOff = GreenAdj + CAdjOff - |
3996 | 620 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 621 OvBOff = BlueAdj + CAdjOff - |
3996 | 622 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
623 #if 0 /* default constants */ | |
624 OvROff = -888.5; | |
625 OvGOff = 545; | |
626 OvBOff = -1104; | |
627 #endif | |
628 | |
629 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
630 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
631 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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diff
changeset
|
632 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
2d64382e8dcf
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diff
changeset
|
633 as in Radeon is a lie */ |
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changeset
|
634 #if 0 |
8855 | 635 if(RadeonFamily == 100) |
3996 | 636 { |
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changeset
|
637 #endif |
3996 | 638 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
639 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
640 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
641 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
642 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
643 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
644 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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nick
parents:
4286
diff
changeset
|
645 #if 0 |
3996 | 646 } |
647 else | |
648 { | |
649 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
650 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
651 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
652 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
653 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
654 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
655 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
656 } | |
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657 #endif |
3996 | 658 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
659 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
660 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
661 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
662 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
663 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
664 } | |
665 | |
666 /* Gamma curve definition */ | |
667 typedef struct | |
668 { | |
669 unsigned int gammaReg; | |
670 unsigned int gammaSlope; | |
671 unsigned int gammaOffset; | |
672 }GAMMA_SETTINGS; | |
673 | |
674 /* Recommended gamma curve parameters */ | |
675 GAMMA_SETTINGS r200_def_gamma[18] = | |
676 { | |
677 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
678 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
679 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
680 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
681 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
682 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
683 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
684 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
685 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
686 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
687 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
688 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
689 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
690 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
691 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
692 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
693 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
694 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
695 }; | |
696 | |
697 GAMMA_SETTINGS r100_def_gamma[6] = | |
698 { | |
699 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
700 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
701 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
702 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
703 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
704 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
705 }; | |
706 | |
707 static void make_default_gamma_correction( void ) | |
708 { | |
709 size_t i; | |
8855 | 710 if(RadeonFamily == 100) { |
3996 | 711 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
712 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
713 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
714 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
715 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
716 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
717 for(i=0; i<6; i++){ | |
718 OUTREG(r100_def_gamma[i].gammaReg, | |
719 (r100_def_gamma[i].gammaSlope<<16) | | |
720 r100_def_gamma[i].gammaOffset); | |
721 } | |
722 } | |
723 else{ | |
724 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
725 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
726 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
727 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
728 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
729 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
730 | |
731 /* Default Gamma, | |
732 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
733 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
734 for(i=0; i<18; i++){ | |
735 OUTREG(r200_def_gamma[i].gammaReg, | |
736 (r200_def_gamma[i].gammaSlope<<16) | | |
737 r200_def_gamma[i].gammaOffset); | |
738 } | |
739 } | |
740 } | |
741 #endif | |
742 | |
743 static void radeon_vid_make_default(void) | |
744 { | |
745 #ifdef RAGE128 | |
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alex
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|
746 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 747 #else |
748 make_default_gamma_correction(); | |
749 #endif | |
750 besr.deinterlace_pattern = 0x900AAAAA; | |
751 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
752 besr.deinterlace_on=1; | |
753 besr.double_buff=1; | |
4869 | 754 besr.ckey_on=0; |
755 besr.graphics_key_msk=0; | |
756 besr.graphics_key_clr=0; | |
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43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
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|
757 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 758 } |
759 | |
760 | |
761 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
762 | |
4107 | 763 static unsigned short ati_card_ids[] = |
3996 | 764 { |
765 #ifdef RAGE128 | |
766 /* | |
767 This driver should be compatible with Rage128 (pro) chips. | |
768 (include adaptive deinterlacing!!!). | |
769 Moreover: the same logic can be used with Mach64 chips. | |
770 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
771 but they are incompatible by i/o ports. So if enthusiasts will want | |
772 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
773 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
774 fourccs (422 and 420 formats only). | |
775 */ | |
776 /* Rage128 Pro GL */ | |
4107 | 777 DEVICE_ATI_RAGE_128_PA_PRO, |
778 DEVICE_ATI_RAGE_128_PB_PRO, | |
779 DEVICE_ATI_RAGE_128_PC_PRO, | |
780 DEVICE_ATI_RAGE_128_PD_PRO, | |
781 DEVICE_ATI_RAGE_128_PE_PRO, | |
782 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 783 /* Rage128 Pro VR */ |
4107 | 784 DEVICE_ATI_RAGE_128_PG_PRO, |
785 DEVICE_ATI_RAGE_128_PH_PRO, | |
786 DEVICE_ATI_RAGE_128_PI_PRO, | |
787 DEVICE_ATI_RAGE_128_PJ_PRO, | |
788 DEVICE_ATI_RAGE_128_PK_PRO, | |
789 DEVICE_ATI_RAGE_128_PL_PRO, | |
790 DEVICE_ATI_RAGE_128_PM_PRO, | |
791 DEVICE_ATI_RAGE_128_PN_PRO, | |
792 DEVICE_ATI_RAGE_128_PO_PRO, | |
793 DEVICE_ATI_RAGE_128_PP_PRO, | |
794 DEVICE_ATI_RAGE_128_PQ_PRO, | |
795 DEVICE_ATI_RAGE_128_PR_PRO, | |
796 DEVICE_ATI_RAGE_128_PS_PRO, | |
797 DEVICE_ATI_RAGE_128_PT_PRO, | |
798 DEVICE_ATI_RAGE_128_PU_PRO, | |
799 DEVICE_ATI_RAGE_128_PV_PRO, | |
800 DEVICE_ATI_RAGE_128_PW_PRO, | |
801 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 802 /* Rage128 GL */ |
4107 | 803 DEVICE_ATI_RAGE_128_RE_SG, |
804 DEVICE_ATI_RAGE_128_RF_SG, | |
805 DEVICE_ATI_RAGE_128_RG, | |
806 DEVICE_ATI_RAGE_128_RK_VR, | |
807 DEVICE_ATI_RAGE_128_RL_VR, | |
808 DEVICE_ATI_RAGE_128_SE_4X, | |
809 DEVICE_ATI_RAGE_128_SF_4X, | |
810 DEVICE_ATI_RAGE_128_SG_4X, | |
8854 | 811 DEVICE_ATI_RAGE_128_SH, |
4107 | 812 DEVICE_ATI_RAGE_128_SK_4X, |
813 DEVICE_ATI_RAGE_128_SL_4X, | |
814 DEVICE_ATI_RAGE_128_SM_4X, | |
8854 | 815 DEVICE_ATI_RAGE_128_4X, |
4107 | 816 DEVICE_ATI_RAGE_128_PRO, |
817 DEVICE_ATI_RAGE_128_PRO2, | |
5165
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
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|
818 DEVICE_ATI_RAGE_128_PRO3, |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
changeset
|
819 /* these seem to be based on rage 128 instead of mach64 */ |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
changeset
|
820 DEVICE_ATI_RAGE_MOBILITY_M3, |
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michael
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|
821 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 822 #else |
823 /* Radeons (indeed: Rage 256 Pro ;) */ | |
8855 | 824 DEVICE_ATI_RADEON_R100_QD, |
825 DEVICE_ATI_RADEON_R100_QE, | |
826 DEVICE_ATI_RADEON_R100_QF, | |
827 DEVICE_ATI_RADEON_R100_QG, | |
828 DEVICE_ATI_RADEON_VE_QY, | |
829 DEVICE_ATI_RADEON_VE_QZ, | |
8854 | 830 DEVICE_ATI_RADEON_MOBILITY_M7, |
831 DEVICE_ATI_RADEON_MOBILITY_M72, | |
4107 | 832 DEVICE_ATI_RADEON_MOBILITY_M6, |
833 DEVICE_ATI_RADEON_MOBILITY_M62, | |
8855 | 834 DEVICE_ATI_RADEON_R200_BB, |
835 DEVICE_ATI_RADEON_R200_QH, | |
836 DEVICE_ATI_RADEON_R200_QI, | |
837 DEVICE_ATI_RADEON_R200_QJ, | |
838 DEVICE_ATI_RADEON_R200_QK, | |
8854 | 839 DEVICE_ATI_RADEON_R200_QL, |
8855 | 840 DEVICE_ATI_RADEON_R200_QH2, |
841 DEVICE_ATI_RADEON_R200_QI2, | |
842 DEVICE_ATI_RADEON_R200_QJ2, | |
843 DEVICE_ATI_RADEON_R200_QK2, | |
8854 | 844 DEVICE_ATI_RADEON_RV200_QW, |
8855 | 845 DEVICE_ATI_RADEON_RV200_QX, |
846 DEVICE_ATI_RADEON_R250_ID, | |
847 DEVICE_ATI_RADEON_R250_IE, | |
848 DEVICE_ATI_RADEON_R250_IF, | |
849 DEVICE_ATI_RADEON_R250_IG, | |
850 DEVICE_ATI_RADEON_R250_LD, | |
851 DEVICE_ATI_RADEON_R250_LE, | |
852 DEVICE_ATI_RADEON_R250_LF, | |
853 DEVICE_ATI_RADEON_R250_LG, | |
854 DEVICE_ATI_RADEON_R300_ND, | |
855 DEVICE_ATI_RADEON_R300_NE, | |
856 DEVICE_ATI_RADEON_R300_NF, | |
857 DEVICE_ATI_RADEON_R300_NG | |
3996 | 858 #endif |
859 }; | |
860 | |
861 static int find_chip(unsigned chip_id) | |
862 { | |
863 unsigned i; | |
4107 | 864 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 865 { |
4107 | 866 if(chip_id == ati_card_ids[i]) return i; |
3996 | 867 } |
868 return -1; | |
869 } | |
870 | |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
871 static pciinfo_t pci_info; |
3996 | 872 static int probed=0; |
873 | |
874 vidix_capability_t def_cap = | |
875 { | |
876 #ifdef RAGE128 | |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
877 "BES driver for Rage128 cards", |
3996 | 878 #else |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
879 "BES driver for Radeon cards", |
3996 | 880 #endif |
4327 | 881 "Nick Kurshev", |
3996 | 882 TYPE_OUTPUT | TYPE_FX, |
4191 | 883 { 0, 0, 0, 0 }, |
4282 | 884 2048, |
885 2048, | |
3996 | 886 4, |
887 4, | |
888 -1, | |
4264 | 889 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 890 VENDOR_ATI, |
3996 | 891 0, |
892 { 0, 0, 0, 0} | |
893 }; | |
894 | |
895 | |
4191 | 896 int vixProbe( int verbose,int force ) |
3996 | 897 { |
898 pciinfo_t lst[MAX_PCI_DEVICES]; | |
899 unsigned i,num_pci; | |
900 int err; | |
4030 | 901 __verbose = verbose; |
3996 | 902 err = pci_scan(lst,&num_pci); |
903 if(err) | |
904 { | |
905 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
906 return err; | |
907 } | |
908 else | |
909 { | |
910 err = ENXIO; | |
911 for(i=0;i<num_pci;i++) | |
912 { | |
4107 | 913 if(lst[i].vendor == VENDOR_ATI) |
3996 | 914 { |
915 int idx; | |
4191 | 916 const char *dname; |
3996 | 917 idx = find_chip(lst[i].device); |
4191 | 918 if(idx == -1 && force == PROBE_NORMAL) continue; |
919 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
920 dname = dname ? dname : "Unknown chip"; | |
921 printf(RADEON_MSG" Found chip: %s\n",dname); | |
3996 | 922 #ifndef RAGE128 |
4191 | 923 if(idx != -1) |
8855 | 924 { |
8876
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patch which removes the rage_ckey_model fix and updates
arpi
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8859
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changeset
|
925 switch(ati_card_ids[idx]) { |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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|
926 /* Original radeon */ |
026ed72206ba
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diff
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|
927 case DEVICE_ATI_RADEON_R100_QD: |
026ed72206ba
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diff
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|
928 case DEVICE_ATI_RADEON_R100_QE: |
026ed72206ba
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parents:
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diff
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|
929 case DEVICE_ATI_RADEON_R100_QF: |
026ed72206ba
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arpi
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|
930 case DEVICE_ATI_RADEON_R100_QG: |
026ed72206ba
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|
931 RadeonFamily = 100; |
026ed72206ba
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diff
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|
932 break; |
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diff
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|
933 |
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|
934 /* Radeon VE / Radeon Mobility */ |
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|
935 case DEVICE_ATI_RADEON_VE_QY: |
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|
936 case DEVICE_ATI_RADEON_VE_QZ: |
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|
937 case DEVICE_ATI_RADEON_MOBILITY_M6: |
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|
938 case DEVICE_ATI_RADEON_MOBILITY_M62: |
026ed72206ba
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arpi
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|
939 RadeonFamily = 120; |
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arpi
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diff
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|
940 break; |
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diff
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|
941 |
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arpi
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diff
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|
942 /* Radeon 7500 / Radeon Mobility 7500 */ |
026ed72206ba
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8859
diff
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|
943 case DEVICE_ATI_RADEON_RV200_QW: |
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diff
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|
944 case DEVICE_ATI_RADEON_RV200_QX: |
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arpi
parents:
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diff
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|
945 case DEVICE_ATI_RADEON_MOBILITY_M7: |
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arpi
parents:
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diff
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|
946 case DEVICE_ATI_RADEON_MOBILITY_M72: |
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arpi
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|
947 RadeonFamily = 150; |
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arpi
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diff
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|
948 break; |
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diff
changeset
|
949 |
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|
950 /* Radeon 8500 */ |
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|
951 case DEVICE_ATI_RADEON_R200_BB: |
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|
952 case DEVICE_ATI_RADEON_R200_QH: |
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|
953 case DEVICE_ATI_RADEON_R200_QI: |
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|
954 case DEVICE_ATI_RADEON_R200_QJ: |
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|
955 case DEVICE_ATI_RADEON_R200_QK: |
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|
956 case DEVICE_ATI_RADEON_R200_QL: |
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|
957 case DEVICE_ATI_RADEON_R200_QH2: |
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|
958 case DEVICE_ATI_RADEON_R200_QI2: |
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|
959 case DEVICE_ATI_RADEON_R200_QJ2: |
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960 case DEVICE_ATI_RADEON_R200_QK2: |
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patch which removes the rage_ckey_model fix and updates
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961 RadeonFamily = 200; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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962 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
changeset
|
963 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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8859
diff
changeset
|
964 /* Radeon 9000 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
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|
965 case DEVICE_ATI_RADEON_R250_ID: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
changeset
|
966 case DEVICE_ATI_RADEON_R250_IE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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8859
diff
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|
967 case DEVICE_ATI_RADEON_R250_IF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
changeset
|
968 case DEVICE_ATI_RADEON_R250_IG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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8859
diff
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|
969 case DEVICE_ATI_RADEON_R250_LD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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diff
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970 case DEVICE_ATI_RADEON_R250_LE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
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971 case DEVICE_ATI_RADEON_R250_LF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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diff
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972 case DEVICE_ATI_RADEON_R250_LG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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973 RadeonFamily = 250; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
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diff
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|
974 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
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diff
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|
975 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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8859
diff
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|
976 /* Radeon 9700 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
8859
diff
changeset
|
977 case DEVICE_ATI_RADEON_R300_ND: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
978 case DEVICE_ATI_RADEON_R300_NE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
979 case DEVICE_ATI_RADEON_R300_NF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
980 case DEVICE_ATI_RADEON_R300_NG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
981 RadeonFamily = 300; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
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|
982 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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parents:
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diff
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|
983 default: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
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diff
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|
984 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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|
985 } |
8855 | 986 } |
3996 | 987 #endif |
4193 | 988 if(force > PROBE_NORMAL) |
989 { | |
990 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
991 if(idx == -1) | |
992 #ifdef RAGE128 | |
4373 | 993 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 994 #else |
4373 | 995 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 996 #endif |
997 } | |
4191 | 998 def_cap.device_id = lst[i].device; |
3996 | 999 err = 0; |
1000 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
1001 probed=1; | |
1002 break; | |
1003 } | |
1004 } | |
1005 } | |
1006 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
1007 return err; | |
1008 } | |
1009 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
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diff
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|
1010 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
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diff
changeset
|
1011 |
3996 | 1012 int vixInit( void ) |
1013 { | |
4477 | 1014 int err; |
4012 | 1015 if(!probed) |
1016 { | |
1017 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
1018 return EINTR; | |
1019 } | |
1020 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 1021 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
1022 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1023 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
8942 | 1024 #ifdef RADEON |
1025 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ | |
1026 if (radeon_ram_size == 0 && | |
1027 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || | |
1028 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) | |
1029 { | |
1030 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); | |
1031 radeon_ram_size = 8192*1024; | |
1032 } | |
1033 #endif | |
3996 | 1034 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
1035 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 1036 radeon_vid_make_default(); |
1037 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 1038 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
1039 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
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diff
changeset
|
1040 |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
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diff
changeset
|
1041 radeon_fifo_wait(3); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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1042 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
d952b097c720
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1043 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
d952b097c720
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1044 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
d952b097c720
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1045 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
d952b097c720
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1046 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
d952b097c720
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diff
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|
1047 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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1048 |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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|
1049 #ifdef RADEON |
8859 | 1050 switch(RadeonFamily) |
1051 { | |
1052 case 100: | |
8876
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patch which removes the rage_ckey_model fix and updates
arpi
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diff
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|
1053 case 120: |
8859 | 1054 case 150: |
1055 case 250: | |
1056 is_shift_required=1; | |
1057 break; | |
1058 default: | |
1059 break; | |
1060 } | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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|
1061 #endif |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
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|
1062 |
6564
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remove colorkeying if destroying the driver - fixes some bugs
alex
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|
1063 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1064 return 0; |
1065 } | |
1066 | |
1067 void vixDestroy( void ) | |
1068 { | |
6564
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remove colorkeying if destroying the driver - fixes some bugs
alex
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diff
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|
1069 /* remove colorkeying */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
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diff
changeset
|
1070 radeon_fifo_wait(3); |
8553
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correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
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|
1071 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
d952b097c720
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diff
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|
1072 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
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|
1073 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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diff
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|
1074 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1075 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1076 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
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diff
changeset
|
1077 |
3996 | 1078 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 1079 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 1080 } |
1081 | |
1082 int vixGetCapability(vidix_capability_t *to) | |
1083 { | |
1084 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1085 return 0; | |
1086 } | |
1087 | |
6483 | 1088 /* |
1089 Full list of fourcc which are supported by Win2K redeon driver: | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1090 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1091 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1092 */ | |
3996 | 1093 uint32_t supported_fourcc[] = |
1094 { | |
6483 | 1095 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1096 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1097 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1098 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1099 IMGFMT_RGB16, IMGFMT_BGR16, |
1100 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1101 }; |
1102 | |
6483 | 1103 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1104 { |
6483 | 1105 unsigned int i; |
3996 | 1106 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1107 { | |
1108 if(fourcc==supported_fourcc[i]) return 1; | |
1109 } | |
1110 return 0; | |
1111 } | |
1112 | |
1113 int vixQueryFourcc(vidix_fourcc_t *to) | |
1114 { | |
1115 if(is_supported_fourcc(to->fourcc)) | |
1116 { | |
1117 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1118 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1119 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1120 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1121 VID_DEPTH_32BPP; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
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|
1122 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1123 return 0; |
1124 } | |
4015 | 1125 else to->depth = to->flags = 0; |
3996 | 1126 return ENOSYS; |
1127 } | |
1128 | |
1129 static void radeon_vid_dump_regs( void ) | |
1130 { | |
1131 size_t i; | |
4015 | 1132 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1133 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1134 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1135 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1136 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1137 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1138 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1139 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1140 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1141 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1142 } |
1143 | |
1144 static void radeon_vid_stop_video( void ) | |
1145 { | |
1146 radeon_engine_idle(); | |
1147 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1148 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1149 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1150 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
8857
a2710e35e2cc
Reduce flickering on window movement (from Christophe Badina)
arpi
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8856
diff
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|
1151 #ifdef RADEON |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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8859
diff
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|
1152 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); |
8857
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Reduce flickering on window movement (from Christophe Badina)
arpi
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8856
diff
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|
1153 #else |
3996 | 1154 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
8857
a2710e35e2cc
Reduce flickering on window movement (from Christophe Badina)
arpi
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diff
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|
1155 #endif |
3996 | 1156 OUTREG(OV0_TEST, 0); |
1157 } | |
1158 | |
1159 static void radeon_vid_display_video( void ) | |
1160 { | |
1161 int bes_flags; | |
1162 radeon_fifo_wait(2); | |
1163 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1164 radeon_engine_idle(); | |
1165 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1166 radeon_fifo_wait(15); | |
4666 | 1167 |
1168 /* Shutdown capturing */ | |
1169 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1170 OUTREG(CAP0_TRIG_CNTL, 0); | |
1171 | |
4689 | 1172 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1173 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1174 |
3996 | 1175 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1176 | |
4611 | 1177 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1178 #ifdef RAGE128 |
7493 | 1179 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1180 (((besr.saturation*31+31000)/2000) << 8) | | |
1181 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1182 #endif |
1183 radeon_fifo_wait(2); | |
4869 | 1184 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1185 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1186 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1187 |
1188 OUTREG(OV0_H_INC, besr.h_inc); | |
1189 OUTREG(OV0_STEP_BY, besr.step_by); | |
1190 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1191 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1192 OUTREG(OV0_V_INC, besr.v_inc); | |
1193 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1194 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1195 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1196 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1197 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1198 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1199 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1200 #ifdef RADEON | |
1201 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1202 #endif | |
4930 | 1203 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1204 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1205 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1206 radeon_fifo_wait(9); |
4930 | 1207 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1208 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1209 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1210 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1211 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1212 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1213 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1214 | |
6678 | 1215 #ifdef RADEON |
1216 bes_flags = SCALER_ENABLE | | |
1217 SCALER_SMART_SWITCH; | |
1218 // SCALER_HORZ_PICK_NEAREST | | |
1219 // SCALER_VERT_PICK_NEAREST | | |
1220 #endif | |
3996 | 1221 bes_flags = SCALER_ENABLE | |
1222 SCALER_SMART_SWITCH | | |
1223 SCALER_Y2R_TEMP | | |
1224 SCALER_PIX_EXPAND; | |
1225 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1226 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1227 #ifdef RAGE128 | |
1228 bes_flags |= SCALER_BURST_PER_PLANE; | |
1229 #endif | |
1230 switch(besr.fourcc) | |
1231 { | |
1232 case IMGFMT_RGB15: | |
1233 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1234 case IMGFMT_RGB16: |
3996 | 1235 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1236 /* |
3996 | 1237 case IMGFMT_RGB24: |
1238 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1239 */ |
3996 | 1240 case IMGFMT_RGB32: |
1241 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1242 /* 4:1:0 */ |
3996 | 1243 case IMGFMT_IF09: |
1244 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1245 /* 4:0:0 */ |
1246 case IMGFMT_Y800: | |
1247 case IMGFMT_Y8: | |
3996 | 1248 /* 4:2:0 */ |
1249 case IMGFMT_IYUV: | |
1250 case IMGFMT_I420: | |
6483 | 1251 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1252 /* 4:2:2 */ |
4455 | 1253 case IMGFMT_YVYU: |
3996 | 1254 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1255 case IMGFMT_YUY2: | |
1256 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1257 } | |
1258 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1259 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1260 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1261 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1262 } |
1263 | |
4456 | 1264 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1265 { |
4456 | 1266 unsigned pitch,spy,spv,spu; |
1267 spy = spv = spu = 0; | |
1268 switch(spitch->y) | |
1269 { | |
1270 case 16: | |
1271 case 32: | |
1272 case 64: | |
1273 case 128: | |
1274 case 256: spy = spitch->y; break; | |
1275 default: break; | |
1276 } | |
1277 switch(spitch->u) | |
1278 { | |
1279 case 16: | |
1280 case 32: | |
1281 case 64: | |
1282 case 128: | |
1283 case 256: spu = spitch->u; break; | |
1284 default: break; | |
1285 } | |
1286 switch(spitch->v) | |
1287 { | |
1288 case 16: | |
1289 case 32: | |
1290 case 64: | |
1291 case 128: | |
1292 case 256: spv = spitch->v; break; | |
1293 default: break; | |
1294 } | |
4009 | 1295 switch(fourcc) |
1296 { | |
1297 /* 4:2:0 */ | |
1298 case IMGFMT_IYUV: | |
1299 case IMGFMT_YV12: | |
4456 | 1300 case IMGFMT_I420: |
1301 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1302 else pitch = 32; | |
1303 break; | |
6483 | 1304 /* 4:1:0 */ |
1305 case IMGFMT_IF09: | |
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1306 case IMGFMT_YVU9: |
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1307 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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1308 else pitch = 64; |
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1309 break; |
4456 | 1310 default: |
1311 if(spy >= 16) pitch = spy; | |
1312 else pitch = 16; | |
1313 break; | |
4009 | 1314 } |
1315 return pitch; | |
1316 } | |
1317 | |
3996 | 1318 static int radeon_vid_init_video( vidix_playback_t *config ) |
1319 { | |
4930 | 1320 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1321 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1322 radeon_vid_stop_video(); |
1323 left = config->src.x << 16; | |
1324 top = config->src.y << 16; | |
1325 src_h = config->src.h; | |
1326 src_w = config->src.w; | |
6483 | 1327 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1328 if(config->fourcc == IMGFMT_YV12 || |
1329 config->fourcc == IMGFMT_I420 || | |
1330 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1331 if(config->fourcc == IMGFMT_YVU9 || |
1332 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1333 if(config->fourcc == IMGFMT_Y800 || | |
1334 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1335 if(config->fourcc == IMGFMT_RGB32 || |
1336 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1337 if(config->fourcc == IMGFMT_RGB32 || |
1338 config->fourcc == IMGFMT_BGR32 || | |
1339 config->fourcc == IMGFMT_RGB24 || | |
1340 config->fourcc == IMGFMT_BGR24 || | |
1341 config->fourcc == IMGFMT_RGB16 || | |
1342 config->fourcc == IMGFMT_BGR16 || | |
1343 config->fourcc == IMGFMT_RGB15 || | |
1344 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1345 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1346 mpitch = best_pitch-1; |
3996 | 1347 switch(config->fourcc) |
1348 { | |
6483 | 1349 /* 4:0:0 */ |
1350 case IMGFMT_Y800: | |
1351 case IMGFMT_Y8: | |
1352 /* 4:1:0 */ | |
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1353 case IMGFMT_YVU9: |
6483 | 1354 case IMGFMT_IF09: |
3996 | 1355 /* 4:2:0 */ |
1356 case IMGFMT_IYUV: | |
1357 case IMGFMT_YV12: | |
4415 | 1358 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1359 config->dest.pitch.y = |
1360 config->dest.pitch.u = | |
4415 | 1361 config->dest.pitch.v = best_pitch; |
3996 | 1362 break; |
4416 | 1363 /* RGB 4:4:4:4 */ |
1364 case IMGFMT_RGB32: | |
1365 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1366 config->dest.pitch.y = | |
1367 config->dest.pitch.u = | |
1368 config->dest.pitch.v = best_pitch; | |
1369 break; | |
3996 | 1370 /* 4:2:2 */ |
4455 | 1371 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1372 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1373 config->dest.pitch.y = |
1374 config->dest.pitch.u = | |
4415 | 1375 config->dest.pitch.v = best_pitch; |
3996 | 1376 break; |
1377 } | |
1378 dest_w = config->dest.w; | |
1379 dest_h = config->dest.h; | |
1380 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1381 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1382 besr.fourcc = config->fourcc; | |
1383 besr.v_inc = (src_h << 20) / dest_h; | |
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1384 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1385 h_inc = (src_w << 12) / dest_w; |
1386 step_by = 1; | |
1387 while(h_inc >= (2 << 12)) { | |
1388 step_by++; | |
1389 h_inc >>= 1; | |
1390 } | |
1391 | |
1392 /* keep everything in 16.16 */ | |
4015 | 1393 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1394 config->offsets[0] = 0; |
4930 | 1395 for(i=1;i<besr.vid_nbufs;i++) |
1396 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1397 if(is_420 || is_410 || is_400) |
3996 | 1398 { |
1399 uint32_t d1line,d2line,d3line; | |
1400 d1line = top*pitch; | |
6483 | 1401 if(is_420) |
1402 { | |
1403 d2line = src_h*pitch+(d1line>>2); | |
1404 d3line = d2line+((src_h*pitch)>>2); | |
1405 } | |
1406 else | |
1407 if(is_410) | |
1408 { | |
1409 d2line = src_h*pitch+(d1line>>4); | |
1410 d3line = d2line+((src_h*pitch)>>4); | |
1411 } | |
1412 else | |
1413 { | |
1414 d2line = 0; | |
1415 d3line = 0; | |
1416 } | |
3996 | 1417 d1line += (left >> 16) & ~15; |
6483 | 1418 if(is_420) |
1419 { | |
1420 d2line += (left >> 17) & ~15; | |
1421 d3line += (left >> 17) & ~15; | |
1422 } | |
1423 else | |
1424 if(is_410) | |
1425 { | |
1426 d2line += (left >> 18) & ~15; | |
1427 d3line += (left >> 18) & ~15; | |
1428 } | |
3996 | 1429 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1430 if(is_400) |
1431 { | |
1432 config->offset.v = 0; | |
1433 config->offset.u = 0; | |
1434 } | |
1435 else | |
1436 { | |
1437 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1438 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1439 } | |
4930 | 1440 for(i=0;i<besr.vid_nbufs;i++) |
1441 { | |
1442 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1443 if(is_400) |
1444 { | |
1445 besr.vid_buf_base_adrs_v[i]=0; | |
1446 besr.vid_buf_base_adrs_u[i]=0; | |
1447 } | |
1448 else | |
1449 { | |
1450 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1451 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1452 } | |
4930 | 1453 } |
1454 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1455 if(is_400) |
1456 { | |
1457 config->offset.v = 0; | |
1458 config->offset.u = 0; | |
1459 } | |
1460 else | |
1461 { | |
1462 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1463 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1464 } | |
3996 | 1465 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1466 { | |
1467 uint32_t tmp; | |
1468 tmp = config->offset.u; | |
1469 config->offset.u = config->offset.v; | |
1470 config->offset.v = tmp; | |
1471 } | |
1472 } | |
1473 else | |
1474 { | |
1475 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1476 for(i=0;i<besr.vid_nbufs;i++) |
1477 { | |
1478 besr.vid_buf_base_adrs_y[i] = | |
1479 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1480 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1481 } |
3996 | 1482 } |
1483 | |
1484 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1485 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1486 ((tmp << 12) & 0xf0000000); | |
1487 | |
1488 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1489 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1490 ((tmp << 12) & 0x70000000); | |
1491 tmp = (top & 0x0000ffff) + 0x00018000; | |
1492 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1493 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1494 | |
1495 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1496 besr.p23_v_accum_init = (is_420||is_410) ? |
1497 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1498 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1499 | |
6483 | 1500 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1501 left = (left >> 16) & 15; |
4571 | 1502 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1503 if(is_rgb32) |
4571 | 1504 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1505 else |
6483 | 1506 if(is_410) |
1507 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1508 else | |
4416 | 1509 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1510 besr.step_by = step_by | (step_by << 8); |
1511 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1512 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1513 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1514 if(is_420 || is_410) |
3996 | 1515 { |
6483 | 1516 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1517 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1518 } | |
1519 else besr.p23_blank_lines_at_top = 0; | |
1520 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1521 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1522 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1523 if (is_410||is_420) src_w>>=is_410?2:1; |
1524 if(is_400) | |
1525 { | |
1526 besr.p2_x_start_end = 0; | |
1527 besr.p3_x_start_end = 0; | |
1528 } | |
1529 else | |
1530 { | |
1531 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1532 besr.p3_x_start_end = besr.p2_x_start_end; | |
1533 } | |
4869 | 1534 |
3996 | 1535 return 0; |
1536 } | |
1537 | |
4009 | 1538 static void radeon_compute_framesize(vidix_playback_t *info) |
1539 { | |
4666 | 1540 unsigned pitch,awidth,dbpp; |
4456 | 1541 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1542 dbpp = radeon_vid_get_dbpp(); |
4033 | 1543 switch(info->fourcc) |
1544 { | |
1545 case IMGFMT_I420: | |
1546 case IMGFMT_YV12: | |
1547 case IMGFMT_IYUV: | |
4666 | 1548 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1549 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1550 break; |
6483 | 1551 case IMGFMT_Y800: |
1552 case IMGFMT_Y8: | |
1553 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1554 info->frame_size = awidth*info->src.h; | |
1555 break; | |
1556 case IMGFMT_IF09: | |
1557 case IMGFMT_YVU9: | |
1558 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1559 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1560 break; | |
4429 | 1561 case IMGFMT_RGB32: |
1562 case IMGFMT_BGR32: | |
4666 | 1563 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1564 info->frame_size = awidth*info->src.h; |
4429 | 1565 break; |
1566 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1567 default: |
1568 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1569 info->frame_size = awidth*info->src.h; |
4033 | 1570 break; |
1571 } | |
4009 | 1572 } |
1573 | |
3996 | 1574 int vixConfigPlayback(vidix_playback_t *info) |
1575 { | |
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1576 unsigned rgb_size,nfr; |
3996 | 1577 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1578 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1579 if(info->num_frames==1) besr.double_buff=0; |
1580 else besr.double_buff=1; | |
4009 | 1581 radeon_compute_framesize(info); |
4930 | 1582 |
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1583 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1584 nfr = info->num_frames; |
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1585 for(;nfr>0; nfr--) |
4930 | 1586 { |
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1587 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1588 radeon_overlay_off &= 0xffff0000; |
1589 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1590 } | |
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1591 if(nfr <= 3) |
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1592 { |
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1593 nfr = info->num_frames; |
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1594 for(;nfr>0; nfr--) |
4930 | 1595 { |
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1596 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1597 radeon_overlay_off &= 0xffff0000; |
1598 if(radeon_overlay_off > 0) break; | |
1599 } | |
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1600 } |
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1601 if(nfr <= 0) return EINVAL; |
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1602 info->num_frames = nfr; |
4930 | 1603 besr.vid_nbufs = info->num_frames; |
1604 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1605 radeon_vid_init_video(info); |
1606 return 0; | |
1607 } | |
1608 | |
1609 int vixPlaybackOn( void ) | |
1610 { | |
1611 radeon_vid_display_video(); | |
1612 return 0; | |
1613 } | |
1614 | |
1615 int vixPlaybackOff( void ) | |
1616 { | |
1617 radeon_vid_stop_video(); | |
1618 return 0; | |
1619 } | |
1620 | |
4033 | 1621 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1622 { |
4412 | 1623 uint32_t off[6]; |
4930 | 1624 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1625 /* |
1626 buf3-5 always should point onto second buffer for better | |
1627 deinterlacing and TV-in | |
1628 */ | |
4666 | 1629 if(!besr.double_buff) return 0; |
4930 | 1630 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1631 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1632 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1633 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1634 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1635 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1636 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1637 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1638 radeon_fifo_wait(8); |
3996 | 1639 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1640 radeon_engine_idle(); |
3996 | 1641 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1642 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1643 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1644 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1645 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1646 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1647 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1648 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1649 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1650 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1651 return 0; |
1652 } | |
1653 | |
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1654 vidix_video_eq_t equal = |
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1655 { |
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1656 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1657 #ifndef RAGE128 |
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1658 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1659 #endif |
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1660 , |
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1661 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1662 |
1663 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1664 { | |
1665 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1666 return 0; | |
1667 } | |
1668 | |
4229 | 1669 #ifndef RAGE128 |
1670 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1671 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1672 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1673 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1674 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1675 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1676 #endif | |
1677 | |
3996 | 1678 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1679 { | |
1680 #ifdef RAGE128 | |
1681 int br,sat; | |
4229 | 1682 #else |
1683 int itu_space; | |
3996 | 1684 #endif |
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1685 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1686 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1687 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1688 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1689 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1690 { |
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1691 equal.red_intensity = eq->red_intensity; |
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1692 equal.green_intensity = eq->green_intensity; |
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1693 equal.blue_intensity = eq->blue_intensity; |
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1694 } |
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1695 equal.flags = eq->flags; |
3996 | 1696 #ifdef RAGE128 |
1697 br = equal.brightness * 64 / 1000; | |
4229 | 1698 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1699 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1700 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1701 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1702 #else | |
4229 | 1703 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1704 RTFCheckParam(equal.brightness); | |
1705 RTFCheckParam(equal.saturation); | |
1706 RTFCheckParam(equal.contrast); | |
1707 RTFCheckParam(equal.hue); | |
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1708 RTFCheckParam(equal.red_intensity); |
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1709 RTFCheckParam(equal.green_intensity); |
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1710 RTFCheckParam(equal.blue_intensity); |
4229 | 1711 radeon_set_transform(RTFBrightness(equal.brightness), |
1712 RTFContrast(equal.contrast), | |
1713 RTFSaturation(equal.saturation), | |
1714 RTFHue(equal.hue), | |
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1715 RTFIntensity(equal.red_intensity), |
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1716 RTFIntensity(equal.green_intensity), |
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1717 RTFIntensity(equal.blue_intensity), |
4229 | 1718 itu_space); |
3996 | 1719 #endif |
1720 return 0; | |
1721 } | |
1722 | |
4611 | 1723 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1724 { | |
1725 unsigned sflg; | |
1726 switch(info->flags) | |
1727 { | |
1728 default: | |
1729 case CFG_NON_INTERLACED: | |
1730 besr.deinterlace_on = 0; | |
1731 break; | |
1732 case CFG_EVEN_ODD_INTERLACING: | |
1733 case CFG_INTERLACED: | |
1734 besr.deinterlace_on = 1; | |
1735 besr.deinterlace_pattern = 0x900AAAAA; | |
1736 break; | |
1737 case CFG_ODD_EVEN_INTERLACING: | |
1738 besr.deinterlace_on = 1; | |
1739 besr.deinterlace_pattern = 0x00055555; | |
1740 break; | |
1741 case CFG_UNIQUE_INTERLACING: | |
1742 besr.deinterlace_on = 1; | |
1743 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1744 break; | |
1745 } | |
1746 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1747 radeon_engine_idle(); | |
1748 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1749 radeon_fifo_wait(15); | |
1750 sflg = INREG(OV0_SCALE_CNTL); | |
1751 if(besr.deinterlace_on) | |
1752 { | |
1753 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1754 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1755 } | |
1756 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1757 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1758 return 0; | |
1759 } | |
1760 | |
1761 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1762 { | |
1763 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1764 else | |
1765 { | |
1766 info->flags = CFG_UNIQUE_INTERLACING; | |
1767 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1768 } | |
1769 return 0; | |
1770 } | |
4869 | 1771 |
1772 | |
1773 /* Graphic keys */ | |
1774 static vidix_grkey_t radeon_grkey; | |
1775 | |
1776 static void set_gr_key( void ) | |
1777 { | |
1778 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1779 { | |
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1780 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1781 besr.ckey_on=1; |
1782 | |
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1783 switch(dbpp) |
4869 | 1784 { |
1785 case 15: | |
8856 | 1786 #ifdef RADEON |
8858 | 1787 if(RadeonFamily > 100) |
8856 | 1788 besr.graphics_key_clr= |
1789 ((radeon_grkey.ckey.blue &0xF8)) | |
1790 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
1791 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1792 else | |
1793 #endif | |
4869 | 1794 besr.graphics_key_clr= |
1795 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1796 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
1797 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
1798 break; | |
1799 case 16: | |
8856 | 1800 #ifdef RADEON |
1801 /* This test may be too general/specific */ | |
8858 | 1802 if(RadeonFamily > 100) |
8856 | 1803 besr.graphics_key_clr= |
1804 ((radeon_grkey.ckey.blue &0xF8)) | |
1805 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
1806 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1807 else | |
1808 #endif | |
4869 | 1809 besr.graphics_key_clr= |
1810 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1811 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
1812 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
1813 break; | |
1814 case 24: | |
1815 besr.graphics_key_clr= | |
1816 ((radeon_grkey.ckey.blue &0xFF)) | |
1817 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1818 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1819 break; | |
1820 case 32: | |
1821 besr.graphics_key_clr= | |
1822 ((radeon_grkey.ckey.blue &0xFF)) | |
1823 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1824 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1825 break; | |
1826 default: | |
1827 besr.ckey_on=0; | |
1828 besr.graphics_key_msk=0; | |
1829 besr.graphics_key_clr=0; | |
1830 } | |
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1831 #ifdef RAGE128 |
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1832 besr.graphics_key_msk=(1<<dbpp)-1; |
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1833 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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1834 #else |
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1835 besr.graphics_key_msk=besr.graphics_key_clr; |
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1836 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; |
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1837 #endif |
4869 | 1838 } |
1839 else | |
1840 { | |
1841 besr.ckey_on=0; | |
1842 besr.graphics_key_msk=0; | |
1843 besr.graphics_key_clr=0; | |
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1844 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 1845 } |
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1846 radeon_fifo_wait(3); |
4869 | 1847 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1848 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1849 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1850 } | |
1851 | |
1852 int vixGetGrKeys(vidix_grkey_t *grkey) | |
1853 { | |
1854 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
1855 return(0); | |
1856 } | |
1857 | |
1858 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
1859 { | |
1860 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
1861 set_gr_key(); | |
1862 return(0); | |
1863 } |