Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3266:ff90589b635f
Fixed single buffering problems and -vo mga compatibility by number of buffers
author | nick |
---|---|
date | Sun, 02 Dec 2001 12:21:13 +0000 |
parents | ec69d8238c84 |
children | a4437ac3f034 |
rev | line source |
---|---|
2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
2870 | 15 */ |
16 | |
3266
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Fixed single buffering problems and -vo mga compatibility by number of buffers
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changeset
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17 #define RADEON_VID_VERSION "1.0.2" |
2951 | 18 |
2870 | 19 /* |
20 It's entirely possible this major conflicts with something else | |
21 mknod /dev/radeon_vid c 178 0 | |
3164 | 22 or |
23 mknod /dev/rage128_vid c 178 0 | |
24 for Rage128/Rage128Pro chips (althrough it doesn't matter) | |
25 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
26 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
27 ----------------------------------------------------------- | |
2870 | 28 TODO: |
3164 | 29 Highest priority: fbvid.h compatibility |
30 High priority: RGB/BGR 2-32, YVU9, IF09 support | |
3122 | 31 Middle priority: |
32 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? | |
33 OV0_AUTO_FLIP_CNTL | |
34 OV0_FILTER_CNTL | |
35 OV0_VIDEO_KEY_CLR | |
36 OV0_KEY_CNTL | |
3164 | 37 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV |
3122 | 38 YUNV, YVYU, Y41P, Y211, Y41T, Y42T, V422, V655, CLJR |
39 ^^^^ | |
40 YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
2870 | 41 */ |
42 | |
43 #include <linux/config.h> | |
44 #include <linux/version.h> | |
45 #include <linux/module.h> | |
46 #include <linux/types.h> | |
47 #include <linux/kernel.h> | |
48 #include <linux/sched.h> | |
49 #include <linux/mm.h> | |
50 #include <linux/string.h> | |
51 #include <linux/errno.h> | |
52 #include <linux/slab.h> | |
53 #include <linux/pci.h> | |
54 #include <linux/ioport.h> | |
55 #include <linux/init.h> | |
3265 | 56 #include <linux/byteorder/swab.h> |
2870 | 57 |
58 #include "radeon_vid.h" | |
59 #include "radeon.h" | |
60 | |
61 #ifdef CONFIG_MTRR | |
62 #include <asm/mtrr.h> | |
63 #endif | |
64 | |
65 #include <asm/uaccess.h> | |
66 #include <asm/system.h> | |
67 #include <asm/io.h> | |
68 | |
69 #define TRUE 1 | |
70 #define FALSE 0 | |
71 | |
72 #define RADEON_VID_MAJOR 178 | |
73 | |
74 | |
75 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
3198 | 76 #ifdef RAGE128 |
77 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
78 #else | |
79 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
80 #endif | |
2965 | 81 #ifdef MODULE_LICENSE |
2870 | 82 MODULE_LICENSE("GPL"); |
2965 | 83 #endif |
3265 | 84 #ifdef CONFIG_MTRR |
85 MODULE_PARM(mtrr, "i"); | |
86 MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); | |
87 static int mtrr __initdata = 1; | |
88 static struct { int vram; int vram_valid; } smtrr; | |
89 #endif | |
90 MODULE_PARM(swap_fourcc, "i"); | |
91 MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (dont't swap=0(default))"); | |
92 static int swap_fourcc __initdata = 0; | |
2870 | 93 |
3164 | 94 #ifdef RAGE128 |
95 #define RVID_MSG "rage128_vid: " | |
96 #define X_ADJUST 0 | |
97 #else | |
98 #define RVID_MSG "radeon_vid: " | |
99 #define X_ADJUST 8 | |
3198 | 100 #ifndef RADEON |
101 #define RADEON | |
102 #endif | |
3164 | 103 #endif |
104 | |
2870 | 105 typedef struct bes_registers_s |
106 { | |
107 /* base address of yuv framebuffer */ | |
108 uint32_t yuv_base; | |
109 uint32_t fourcc; | |
110 /* YUV BES registers */ | |
111 uint32_t reg_load_cntl; | |
112 uint32_t h_inc; | |
113 uint32_t step_by; | |
114 uint32_t y_x_start; | |
115 uint32_t y_x_end; | |
116 uint32_t v_inc; | |
117 uint32_t p1_blank_lines_at_top; | |
3019 | 118 uint32_t p23_blank_lines_at_top; |
2870 | 119 uint32_t vid_buf_pitch0_value; |
2944 | 120 uint32_t vid_buf_pitch1_value; |
2870 | 121 uint32_t p1_x_start_end; |
122 uint32_t p2_x_start_end; | |
123 uint32_t p3_x_start_end; | |
3122 | 124 uint32_t base_addr; |
2870 | 125 uint32_t vid_buf0_base_adrs; |
126 /* These ones are for auto flip: maybe in the future */ | |
127 uint32_t vid_buf1_base_adrs; | |
128 uint32_t vid_buf2_base_adrs; | |
129 uint32_t vid_buf3_base_adrs; | |
130 uint32_t vid_buf4_base_adrs; | |
131 uint32_t vid_buf5_base_adrs; | |
132 | |
133 uint32_t p1_v_accum_init; | |
134 uint32_t p1_h_accum_init; | |
3019 | 135 uint32_t p23_v_accum_init; |
2870 | 136 uint32_t p23_h_accum_init; |
137 uint32_t scale_cntl; | |
138 uint32_t exclusive_horz; | |
139 uint32_t auto_flip_cntl; | |
140 uint32_t filter_cntl; | |
3250 | 141 uint32_t graphics_key_msk; |
142 uint32_t key_cntl; | |
143 uint32_t test; | |
144 /* Configurable stuff */ | |
145 int double_buff; | |
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146 int brightness; |
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147 int saturation; |
2870 | 148 uint32_t graphics_key_clr; |
3250 | 149 int deinterlace_on; |
150 uint32_t deinterlace_pattern; | |
2870 | 151 } bes_registers_t; |
152 | |
153 typedef struct video_registers_s | |
154 { | |
155 uint32_t name; | |
156 uint32_t value; | |
157 }video_registers_t; | |
158 | |
159 static bes_registers_t besr; | |
160 static video_registers_t vregs[] = | |
161 { | |
162 { OV0_REG_LOAD_CNTL, 0 }, | |
163 { OV0_H_INC, 0 }, | |
164 { OV0_STEP_BY, 0 }, | |
165 { OV0_Y_X_START, 0 }, | |
166 { OV0_Y_X_END, 0 }, | |
167 { OV0_V_INC, 0 }, | |
168 { OV0_P1_BLANK_LINES_AT_TOP, 0 }, | |
3019 | 169 { OV0_P23_BLANK_LINES_AT_TOP, 0 }, |
2870 | 170 { OV0_VID_BUF_PITCH0_VALUE, 0 }, |
2944 | 171 { OV0_VID_BUF_PITCH1_VALUE, 0 }, |
2870 | 172 { OV0_P1_X_START_END, 0 }, |
173 { OV0_P2_X_START_END, 0 }, | |
174 { OV0_P3_X_START_END, 0 }, | |
3122 | 175 { OV0_BASE_ADDR, 0 }, |
2870 | 176 { OV0_VID_BUF0_BASE_ADRS, 0 }, |
177 { OV0_VID_BUF1_BASE_ADRS, 0 }, | |
178 { OV0_VID_BUF2_BASE_ADRS, 0 }, | |
179 { OV0_VID_BUF3_BASE_ADRS, 0 }, | |
180 { OV0_VID_BUF4_BASE_ADRS, 0 }, | |
181 { OV0_VID_BUF5_BASE_ADRS, 0 }, | |
182 { OV0_P1_V_ACCUM_INIT, 0 }, | |
183 { OV0_P1_H_ACCUM_INIT, 0 }, | |
3019 | 184 { OV0_P23_V_ACCUM_INIT, 0 }, |
2870 | 185 { OV0_P23_H_ACCUM_INIT, 0 }, |
186 { OV0_SCALE_CNTL, 0 }, | |
187 { OV0_EXCLUSIVE_HORZ, 0 }, | |
188 { OV0_AUTO_FLIP_CNTL, 0 }, | |
189 { OV0_FILTER_CNTL, 0 }, | |
190 { OV0_COLOUR_CNTL, 0 }, | |
191 { OV0_GRAPHICS_KEY_MSK, 0 }, | |
192 { OV0_GRAPHICS_KEY_CLR, 0 }, | |
193 { OV0_KEY_CNTL, 0 }, | |
194 { OV0_TEST, 0 } | |
195 }; | |
196 | |
197 static uint32_t radeon_vid_in_use = 0; | |
198 | |
199 static uint8_t *radeon_mmio_base = 0; | |
200 static uint32_t radeon_mem_base = 0; | |
3019 | 201 static int32_t radeon_overlay_off = 0; |
2870 | 202 static uint32_t radeon_ram_size = 0; |
3263 | 203 #define PARAM_BUFF_SIZE 4096 |
204 static uint8_t *radeon_param_buff = NULL; | |
205 static uint32_t radeon_param_buff_size=0; | |
206 static uint32_t radeon_param_buff_len=0; /* real length of buffer */ | |
2870 | 207 static mga_vid_config_t radeon_config; |
208 | |
2951 | 209 #undef DEBUG |
2870 | 210 #if DEBUG |
211 #define RTRACE printk | |
212 #else | |
213 #define RTRACE(...) ((void)0) | |
214 #endif | |
215 | |
3122 | 216 static char *fourcc_format_name(int format) |
217 { | |
218 switch(format) | |
219 { | |
220 case IMGFMT_RGB8: return("RGB 8-bit"); | |
221 case IMGFMT_RGB15: return("RGB 15-bit"); | |
222 case IMGFMT_RGB16: return("RGB 16-bit"); | |
223 case IMGFMT_RGB24: return("RGB 24-bit"); | |
224 case IMGFMT_RGB32: return("RGB 32-bit"); | |
225 case IMGFMT_BGR8: return("BGR 8-bit"); | |
226 case IMGFMT_BGR15: return("BGR 15-bit"); | |
227 case IMGFMT_BGR16: return("BGR 16-bit"); | |
228 case IMGFMT_BGR24: return("BGR 24-bit"); | |
229 case IMGFMT_BGR32: return("BGR 32-bit"); | |
230 case IMGFMT_YVU9: return("Planar YVU9"); | |
231 case IMGFMT_IF09: return("Planar IF09"); | |
232 case IMGFMT_YV12: return("Planar YV12"); | |
233 case IMGFMT_I420: return("Planar I420"); | |
234 case IMGFMT_IYUV: return("Planar IYUV"); | |
235 case IMGFMT_CLPL: return("Planar CLPL"); | |
3198 | 236 case IMGFMT_Y800: return("Planar Y800"); |
237 case IMGFMT_Y8: return("Planar Y8"); | |
238 case IMGFMT_IUYV: return("Packed IUYV"); | |
239 case IMGFMT_IY41: return("Packed IY41"); | |
3122 | 240 case IMGFMT_IYU1: return("Packed IYU1"); |
241 case IMGFMT_IYU2: return("Packed IYU2"); | |
242 case IMGFMT_UYVY: return("Packed UYVY"); | |
243 case IMGFMT_UYNV: return("Packed UYNV"); | |
244 case IMGFMT_cyuv: return("Packed CYUV"); | |
3198 | 245 case IMGFMT_Y422: return("Packed Y422"); |
3122 | 246 case IMGFMT_YUY2: return("Packed YUY2"); |
247 case IMGFMT_YUNV: return("Packed YUNV"); | |
248 case IMGFMT_YVYU: return("Packed YVYU"); | |
249 case IMGFMT_Y41P: return("Packed Y41P"); | |
250 case IMGFMT_Y211: return("Packed Y211"); | |
251 case IMGFMT_Y41T: return("Packed Y41T"); | |
252 case IMGFMT_Y42T: return("Packed Y42T"); | |
253 case IMGFMT_V422: return("Packed V422"); | |
254 case IMGFMT_V655: return("Packed V655"); | |
255 case IMGFMT_CLJR: return("Packed CLJR"); | |
256 case IMGFMT_YUVP: return("Packed YUVP"); | |
257 case IMGFMT_UYVP: return("Packed UYVP"); | |
3198 | 258 case IMGFMT_MPEGPES: return("Mpeg PES"); |
3122 | 259 } |
260 return("Unknown"); | |
261 } | |
262 | |
2870 | 263 |
264 /* | |
265 * IO macros | |
266 */ | |
267 | |
268 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
269 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
270 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
271 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
272 | |
3265 | 273 static void __init radeon_vid_save_state( void ) |
2870 | 274 { |
275 size_t i; | |
276 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
277 vregs[i].value = INREG(vregs[i].name); | |
278 } | |
279 | |
3265 | 280 static void __exit radeon_vid_restore_state( void ) |
2870 | 281 { |
282 size_t i; | |
283 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
284 OUTREG(vregs[i].name,vregs[i].value); | |
285 } | |
286 | |
287 static void radeon_vid_stop_video( void ) | |
288 { | |
289 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
290 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
291 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
292 OUTREG(OV0_FILTER_CNTL, 0x0000000f); | |
293 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
294 OUTREG(OV0_TEST, 0); | |
295 } | |
296 | |
297 static void radeon_vid_display_video( void ) | |
298 { | |
299 int bes_flags; | |
3164 | 300 RTRACE(RVID_MSG"OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
301 RTRACE(RVID_MSG"OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs); | |
302 RTRACE(RVID_MSG"OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 303 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
3164 | 304 RTRACE(RVID_MSG"OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n" |
2951 | 305 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end); |
3164 | 306 RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n" |
2951 | 307 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init); |
2870 | 308 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
309 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
2965 | 310 |
2870 | 311 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
312 | |
3250 | 313 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
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314 |
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315 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
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316 (besr.saturation << 8) | |
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317 (besr.saturation << 16)); |
2870 | 318 |
319 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
320 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2965 | 321 |
2870 | 322 OUTREG(OV0_H_INC, besr.h_inc); |
323 OUTREG(OV0_STEP_BY, besr.step_by); | |
324 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
325 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
326 OUTREG(OV0_V_INC, besr.v_inc); | |
327 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
3164 | 328 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
2870 | 329 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
2944 | 330 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 331 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
332 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
333 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
3198 | 334 #if 0 |
3122 | 335 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
336 #endif | |
2870 | 337 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
338 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
339 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
340 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
341 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
342 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
343 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
344 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
345 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
3164 | 346 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
2870 | 347 |
348 bes_flags = SCALER_ENABLE | | |
349 SCALER_SMART_SWITCH | | |
350 SCALER_HORZ_PICK_NEAREST; | |
3250 | 351 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; |
352 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
3198 | 353 #ifdef RAGE128 |
354 bes_flags |= SCALER_BURST_PER_PLANE; | |
355 #endif | |
2870 | 356 switch(besr.fourcc) |
357 { | |
358 case IMGFMT_RGB15: | |
359 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
360 case IMGFMT_RGB16: | |
361 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
362 case IMGFMT_RGB24: | |
363 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
364 case IMGFMT_RGB32: | |
365 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
3164 | 366 /* 4:1:0*/ |
367 case IMGFMT_IF09: | |
2870 | 368 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
3164 | 369 /* 4:2:0 */ |
3122 | 370 case IMGFMT_IYUV: |
2870 | 371 case IMGFMT_I420: |
3164 | 372 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
373 /* 4:2:2 */ | |
374 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
2870 | 375 case IMGFMT_YUY2: |
376 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
377 } | |
3164 | 378 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags); |
2870 | 379 OUTREG(OV0_SCALE_CNTL, bes_flags); |
380 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
381 } | |
382 | |
2951 | 383 #define XXX_SRC_X 0 |
384 #define XXX_SRC_Y 0 | |
2870 | 385 |
2944 | 386 #define XXX_WIDTH config->src_width |
387 #define XXX_HEIGHT config->src_height | |
2870 | 388 |
2951 | 389 #define XXX_DRW_W config->dest_width |
390 #define XXX_DRW_H config->dest_height | |
2925 | 391 |
2870 | 392 static int radeon_vid_init_video( mga_vid_config_t *config ) |
393 { | |
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394 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 395 int is_420; |
3164 | 396 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 397 ,(uint32_t)config->version |
2951 | 398 ,(uint32_t)config->format |
2870 | 399 ,(uint32_t)config->card_type |
400 ,(uint32_t)config->ram_size | |
401 ,(uint32_t)config->src_width | |
402 ,(uint32_t)config->src_height | |
403 ,(uint32_t)config->x_org | |
404 ,(uint32_t)config->y_org | |
405 ,(uint32_t)config->dest_width | |
406 ,(uint32_t)config->dest_height | |
407 ,(uint32_t)config->frame_size | |
408 ,(uint32_t)config->num_frames); | |
2917 | 409 radeon_vid_stop_video(); |
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410 left = XXX_SRC_X << 16; |
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411 top = XXX_SRC_Y << 16; |
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412 src_h = config->src_height; |
ef3b9b104648
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413 src_w = config->src_width; |
2870 | 414 switch(config->format) |
415 { | |
416 case IMGFMT_RGB15: | |
417 case IMGFMT_BGR15: | |
418 case IMGFMT_RGB16: | |
419 case IMGFMT_BGR16: | |
420 case IMGFMT_RGB24: | |
421 case IMGFMT_BGR24: | |
422 case IMGFMT_RGB32: | |
423 case IMGFMT_BGR32: | |
3164 | 424 /* 4:1:0 */ |
425 case IMGFMT_IF09: | |
2870 | 426 case IMGFMT_YVU9: |
3164 | 427 /* 4:2:0 */ |
2870 | 428 case IMGFMT_IYUV: |
429 case IMGFMT_YV12: | |
430 case IMGFMT_I420: | |
3164 | 431 /* 4:2:2 */ |
432 case IMGFMT_UYVY: | |
2870 | 433 case IMGFMT_YUY2: |
434 break; | |
435 default: | |
3164 | 436 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
2870 | 437 return -1; |
438 } | |
3019 | 439 is_420 = 0; |
3122 | 440 if(config->format == IMGFMT_YV12 || |
441 config->format == IMGFMT_I420 || | |
442 config->format == IMGFMT_IYUV) is_420 = 1; | |
2951 | 443 switch(config->format) |
444 { | |
3164 | 445 /* 4:1:0 */ |
2951 | 446 case IMGFMT_YVU9: |
3164 | 447 case IMGFMT_IF09: |
448 /* 4:2:0 */ | |
2951 | 449 case IMGFMT_IYUV: |
3164 | 450 case IMGFMT_YV12: |
451 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
452 /* 4:2:2 */ | |
453 default: | |
2951 | 454 case IMGFMT_UYVY: |
455 case IMGFMT_YUY2: | |
456 case IMGFMT_RGB15: | |
457 case IMGFMT_BGR15: | |
458 case IMGFMT_RGB16: | |
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459 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 460 case IMGFMT_RGB24: |
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461 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 462 case IMGFMT_RGB32: |
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463 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 464 } |
465 | |
2870 | 466 besr.fourcc = config->format; |
467 | |
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468 besr.v_inc = (src_h << 20) / XXX_DRW_H; |
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469 h_inc = (src_w << 12) / XXX_DRW_W; |
2944 | 470 step_by = 1; |
2870 | 471 |
2944 | 472 while(h_inc >= (2 << 12)) { |
473 step_by++; | |
474 h_inc >>= 1; | |
2870 | 475 } |
476 | |
477 /* keep everything in 16.16 */ | |
3164 | 478 besr.base_addr = radeon_mem_base; |
3019 | 479 if(is_420) |
480 { | |
3164 | 481 uint32_t d1line,d2line,d3line; |
482 d1line = top*pitch; | |
483 d2line = src_h*pitch+(d1line>>1); | |
484 d3line = d2line+((src_h*pitch)>>2); | |
485 d1line += (left >> 16) & ~15; | |
486 d2line += (left >> 17) & ~15; | |
487 d3line += (left >> 17) & ~15; | |
488 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
489 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
490 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
491 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
492 { | |
493 uint32_t tmp; | |
494 tmp = besr.vid_buf1_base_adrs; | |
495 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
496 besr.vid_buf2_base_adrs = tmp; | |
497 } | |
3019 | 498 } |
499 else | |
500 { | |
501 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
3198 | 502 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; |
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503 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 504 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
505 } | |
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506 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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507 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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508 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 509 |
2951 | 510 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 511 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 512 ((tmp << 12) & 0xf0000000); |
2870 | 513 |
2951 | 514 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 515 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 516 ((tmp << 12) & 0x70000000); |
517 tmp = (top & 0x0000ffff) + 0x00018000; | |
3122 | 518 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
519 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
3019 | 520 |
521 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
3122 | 522 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
523 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
3019 | 524 |
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525 leftUV = (left >> 17) & 15; |
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526 left = (left >> 16) & 15; |
2944 | 527 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
528 besr.step_by = step_by | (step_by << 8); | |
3164 | 529 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
530 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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531 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
3122 | 532 if(is_420) |
533 { | |
534 src_h = (src_h + 1) >> 1; | |
535 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
536 } | |
537 else besr.p23_blank_lines_at_top = 0; | |
2870 | 538 besr.vid_buf_pitch0_value = pitch; |
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539 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
3164 | 540 RTRACE(RVID_MSG"BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
541 RTRACE(RVID_MSG"BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); | |
542 RTRACE(RVID_MSG"BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 543 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
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544 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
3164 | 545 src_w>>=1; |
546 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
547 besr.p3_x_start_end = besr.p2_x_start_end; | |
2870 | 548 return 0; |
549 } | |
550 | |
551 static void radeon_vid_frame_sel(int frame) | |
552 { | |
3066 | 553 uint32_t off0,off1,off2; |
3250 | 554 if(!besr.double_buff) return; |
3066 | 555 if(frame%2) |
556 { | |
557 off0 = besr.vid_buf3_base_adrs; | |
558 off1 = besr.vid_buf4_base_adrs; | |
559 off2 = besr.vid_buf5_base_adrs; | |
560 } | |
561 else | |
562 { | |
563 off0 = besr.vid_buf0_base_adrs; | |
564 off1 = besr.vid_buf1_base_adrs; | |
565 off2 = besr.vid_buf2_base_adrs; | |
566 } | |
2917 | 567 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
568 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 569 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
570 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
571 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 572 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 573 } |
574 | |
3250 | 575 static void radeon_vid_make_default(void) |
576 { | |
577 besr.deinterlace_pattern = 0x900AAAAA; | |
578 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
579 besr.deinterlace_on=1; | |
580 besr.double_buff=1; | |
581 } | |
582 | |
583 | |
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584 static void radeon_vid_preset(void) |
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585 { |
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586 unsigned tmp; |
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587 tmp = INREG(OV0_COLOUR_CNTL); |
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588 besr.saturation = (tmp>>8)&0x1f; |
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589 besr.brightness = tmp & 0x7f; |
3250 | 590 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); |
591 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); | |
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592 } |
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593 |
2951 | 594 static int video_on = 0; |
595 | |
2870 | 596 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
597 { | |
598 int frame; | |
599 | |
600 switch(cmd) | |
601 { | |
602 case MGA_VID_CONFIG: | |
603 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base); | |
604 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base); | |
3164 | 605 RTRACE(RVID_MSG"Received configuration\n"); |
2870 | 606 |
607 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
608 { | |
3164 | 609 printk(RVID_MSG"failed copy from userspace\n"); |
3019 | 610 return -EFAULT; |
2870 | 611 } |
612 if(radeon_config.version != MGA_VID_VERSION){ | |
3164 | 613 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
3019 | 614 return -EFAULT; |
2870 | 615 } |
616 | |
617 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
3164 | 618 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
3019 | 619 return -EFAULT; |
2870 | 620 } |
621 | |
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622 if(radeon_config.num_frames<1){ |
3164 | 623 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
3019 | 624 return -EFAULT; |
2870 | 625 } |
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626 if(radeon_config.num_frames==1) besr.double_buff=0; |
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627 if(!besr.double_buff) radeon_config.num_frames=1; |
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628 else radeon_config.num_frames=2; |
2870 | 629 radeon_config.card_type = 0; |
630 radeon_config.ram_size = radeon_ram_size; | |
3019 | 631 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
632 radeon_overlay_off &= 0xffff0000; | |
633 if(radeon_overlay_off < 0){ | |
3164 | 634 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
3019 | 635 return -EFAULT; |
636 } | |
3164 | 637 RTRACE(RVID_MSG"using video overlay at offset %p\n",radeon_overlay_off); |
2870 | 638 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
639 { | |
3164 | 640 printk(RVID_MSG"failed copy to userspace\n"); |
3019 | 641 return -EFAULT; |
2870 | 642 } |
3265 | 643 if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); |
3164 | 644 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
2870 | 645 return radeon_vid_init_video(&radeon_config); |
646 break; | |
647 | |
648 case MGA_VID_ON: | |
3164 | 649 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
650 radeon_vid_display_video(); | |
2951 | 651 video_on = 1; |
2870 | 652 break; |
653 | |
654 case MGA_VID_OFF: | |
3164 | 655 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
2951 | 656 if(video_on) radeon_vid_stop_video(); |
657 video_on = 0; | |
2870 | 658 break; |
659 | |
660 case MGA_VID_FSEL: | |
661 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
662 { | |
3164 | 663 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
2870 | 664 return(-EFAULT); |
665 } | |
666 radeon_vid_frame_sel(frame); | |
667 break; | |
668 | |
669 default: | |
3164 | 670 printk(RVID_MSG"Invalid ioctl\n"); |
2870 | 671 return (-EINVAL); |
672 } | |
673 | |
674 return 0; | |
675 } | |
676 | |
677 struct ati_card_id_s | |
678 { | |
3164 | 679 const int id; |
680 const char name[17]; | |
681 }; | |
682 | |
683 const struct ati_card_id_s ati_card_ids[]= | |
2870 | 684 { |
3164 | 685 #ifdef RAGE128 |
686 /* | |
687 This driver should be compatible with Rage128 (pro) chips. | |
688 (include adaptive deinterlacing!!!). | |
689 Moreover: the same logic can be used with Mach64 chips. | |
690 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
691 but they are incompatible by i/o ports. So if enthusiasts will want | |
692 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
693 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
694 fourccs (422 and 420 formats only). | |
695 */ | |
696 /* Rage128 Pro GL */ | |
697 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
698 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
699 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
700 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
701 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
702 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
703 /* Rage128 Pro VR */ | |
704 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
705 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
706 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
707 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
708 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
709 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
710 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
711 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
712 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
713 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
714 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
715 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
716 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
717 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
718 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
719 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
720 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
721 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
722 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
723 /* Rage128 GL */ | |
724 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
725 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
726 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
727 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
728 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
729 /* Rage128 VR */ | |
730 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
731 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
732 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
733 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
734 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
735 /* Rage128 M3 */ | |
3198 | 736 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, |
737 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
3164 | 738 /* Rage128 Pro Ultra */ |
3198 | 739 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, |
740 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
741 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
3164 | 742 #else |
743 /* Radeons (indeed: Rage 256 Pro ;) */ | |
2870 | 744 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
745 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
746 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
747 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
748 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
749 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
750 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
751 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
752 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
753 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
754 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
3164 | 755 #endif |
2870 | 756 }; |
757 | |
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758 static int detected_chip; |
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759 |
3265 | 760 static int __init radeon_vid_config_card(void) |
2870 | 761 { |
762 struct pci_dev *dev = NULL; | |
763 size_t i; | |
764 | |
765 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
766 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
767 break; | |
3122 | 768 if(!dev) |
2870 | 769 { |
3164 | 770 printk(RVID_MSG"No supported cards found\n"); |
2870 | 771 return FALSE; |
772 } | |
773 | |
774 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
775 radeon_mem_base = dev->resource[0].start; | |
776 | |
3164 | 777 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
778 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
2870 | 779 |
3122 | 780 /* video memory size */ |
781 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
782 | |
3164 | 783 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
3122 | 784 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
785 radeon_ram_size /= 0x100000; | |
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786 detected_chip = i; |
3164 | 787 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
2870 | 788 |
789 return TRUE; | |
790 } | |
791 | |
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792 #define PARAM_BRIGHTNESS "brightness=" |
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793 #define PARAM_SATURATION "saturation=" |
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794 #define PARAM_DOUBLE_BUFF "double_buff=" |
3250 | 795 #define PARAM_COLOUR_KEY "colour_key=" |
796 #define PARAM_DEINTERLACE "deinterlace=" | |
797 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" | |
2870 | 798 |
3263 | 799 static void radeon_param_buff_fill( void ) |
2870 | 800 { |
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801 unsigned len,saturation; |
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802 long brightness; |
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803 brightness = besr.brightness; |
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804 saturation = besr.saturation; |
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805 len = 0; |
3263 | 806 len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); |
807 len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); | |
808 len += sprintf(&radeon_param_buff[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000); | |
809 len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); | |
810 len += sprintf(&radeon_param_buff[len],"Overlay offset: %p\n",radeon_overlay_off); | |
3265 | 811 len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); |
812 len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); | |
3263 | 813 len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); |
814 len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); | |
815 len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); | |
816 len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); | |
817 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",brightness); | |
818 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); | |
819 len += sprintf(&radeon_param_buff[len],PARAM_COLOUR_KEY"%X\n",besr.graphics_key_clr); | |
820 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); | |
821 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); | |
822 radeon_param_buff_len = len; | |
823 } | |
824 | |
825 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
826 { | |
827 uint32_t size; | |
828 if(!radeon_param_buff) return -ESPIPE; | |
829 if(!(*ppos)) radeon_param_buff_fill(); | |
830 if(*ppos >= radeon_param_buff_len) return 0; | |
831 size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); | |
832 memcpy(buf,radeon_param_buff,size); | |
833 *ppos += size; | |
834 return size; | |
2870 | 835 } |
836 | |
837 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
838 { | |
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839 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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840 { |
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841 long brightness; |
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842 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
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843 if(brightness >= -64 && brightness <= 63) |
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844 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | |
3250 | 845 (besr.saturation << 8) | |
846 (besr.saturation << 16)); | |
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847 } |
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848 else |
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849 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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850 { |
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851 long saturation; |
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852 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); |
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853 if(saturation >= 0 && saturation <= 31) |
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854 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
3250 | 855 (saturation << 8) | |
856 (saturation << 16)); | |
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857 } |
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858 else |
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859 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) |
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860 { |
3250 | 861 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; |
862 else besr.double_buff = 0; | |
863 } | |
864 else | |
865 if(memcmp(buf,PARAM_COLOUR_KEY,min(count,strlen(PARAM_COLOUR_KEY))) == 0) | |
866 { | |
867 long ckey; | |
868 ckey=simple_strtol(&buf[strlen(PARAM_COLOUR_KEY)],NULL,16); | |
869 OUTREG(OV0_GRAPHICS_KEY_CLR, ckey); | |
870 } | |
871 else | |
872 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) | |
873 { | |
874 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; | |
875 else besr.deinterlace_on = 0; | |
876 } | |
877 else | |
878 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) | |
879 { | |
880 long dpat; | |
881 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); | |
882 OUTREG(OV0_DEINTERLACE_PATTERN, dpat); | |
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883 } |
3263 | 884 else count = -EIO; |
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885 radeon_vid_preset(); |
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886 return count; |
2870 | 887 } |
888 | |
889 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
890 { | |
891 | |
3164 | 892 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
3019 | 893 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 894 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
895 { | |
3164 | 896 printk(RVID_MSG"error mapping video memory\n"); |
2870 | 897 return(-EAGAIN); |
898 } | |
899 | |
900 return(0); | |
901 } | |
902 | |
903 static int radeon_vid_release(struct inode *inode, struct file *file) | |
904 { | |
905 radeon_vid_in_use = 0; | |
906 radeon_vid_stop_video(); | |
907 | |
908 MOD_DEC_USE_COUNT; | |
909 return 0; | |
910 } | |
911 | |
912 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
913 { | |
914 return -ESPIPE; | |
915 } | |
916 | |
917 static int radeon_vid_open(struct inode *inode, struct file *file) | |
918 { | |
919 int minor = MINOR(inode->i_rdev); | |
920 | |
921 if(minor != 0) | |
922 return(-ENXIO); | |
923 | |
924 if(radeon_vid_in_use == 1) | |
925 return(-EBUSY); | |
926 | |
927 radeon_vid_in_use = 1; | |
928 MOD_INC_USE_COUNT; | |
929 return(0); | |
930 } | |
931 | |
932 #if LINUX_VERSION_CODE >= 0x020400 | |
933 static struct file_operations radeon_vid_fops = | |
934 { | |
935 llseek: radeon_vid_lseek, | |
936 read: radeon_vid_read, | |
937 write: radeon_vid_write, | |
938 ioctl: radeon_vid_ioctl, | |
939 mmap: radeon_vid_mmap, | |
940 open: radeon_vid_open, | |
941 release: radeon_vid_release | |
942 }; | |
943 #else | |
944 static struct file_operations radeon_vid_fops = | |
945 { | |
946 radeon_vid_lseek, | |
947 radeon_vid_read, | |
948 radeon_vid_write, | |
949 NULL, | |
950 NULL, | |
951 radeon_vid_ioctl, | |
952 radeon_vid_mmap, | |
953 radeon_vid_open, | |
954 NULL, | |
955 radeon_vid_release | |
956 }; | |
957 #endif | |
958 | |
959 /* | |
960 * Main Initialization Function | |
961 */ | |
962 | |
3265 | 963 static int __init radeon_vid_initialize(void) |
2870 | 964 { |
965 radeon_vid_in_use = 0; | |
3164 | 966 #ifdef RAGE128 |
967 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
968 #else | |
969 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
970 #endif | |
2870 | 971 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
972 { | |
3164 | 973 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
2870 | 974 return -EIO; |
975 } | |
976 | |
977 if (!radeon_vid_config_card()) | |
978 { | |
3164 | 979 printk(RVID_MSG"can't configure this card\n"); |
2870 | 980 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
981 return -EINVAL; | |
982 } | |
3263 | 983 radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); |
984 if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; | |
2870 | 985 radeon_vid_save_state(); |
3250 | 986 radeon_vid_make_default(); |
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987 radeon_vid_preset(); |
3265 | 988 #ifdef CONFIG_MTRR |
989 if (mtrr) { | |
990 smtrr.vram = mtrr_add(radeon_mem_base, | |
991 radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); | |
992 smtrr.vram_valid = 1; | |
993 /* let there be speed */ | |
994 printk(RVID_MSG"MTRR set to ON\n"); | |
995 } | |
996 #endif /* CONFIG_MTRR */ | |
2870 | 997 return(0); |
998 } | |
999 | |
3265 | 1000 int __init init_module(void) |
2870 | 1001 { |
1002 return radeon_vid_initialize(); | |
1003 } | |
1004 | |
3265 | 1005 void __exit cleanup_module(void) |
2870 | 1006 { |
1007 radeon_vid_restore_state(); | |
1008 if(radeon_mmio_base) | |
1009 iounmap(radeon_mmio_base); | |
3263 | 1010 kfree(radeon_param_buff); |
3164 | 1011 RTRACE(RVID_MSG"Cleaning up module\n"); |
2870 | 1012 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
3265 | 1013 #ifdef CONFIG_MTRR |
1014 if (smtrr.vram_valid) | |
1015 mtrr_del(smtrr.vram, radeon_mem_base, | |
1016 radeon_ram_size*0x100000); | |
1017 #endif /* CONFIG_MTRR */ | |
2870 | 1018 } |
1019 |