Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3278:404cfc1a0942
Color key still causes some troubles
author | nick |
---|---|
date | Mon, 03 Dec 2001 10:10:19 +0000 |
parents | a4437ac3f034 |
children | 27be0e71c0ee |
rev | line source |
---|---|
2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
2870 | 15 */ |
16 | |
3266
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Fixed single buffering problems and -vo mga compatibility by number of buffers
nick
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diff
changeset
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17 #define RADEON_VID_VERSION "1.0.2" |
2951 | 18 |
2870 | 19 /* |
20 It's entirely possible this major conflicts with something else | |
21 mknod /dev/radeon_vid c 178 0 | |
3164 | 22 or |
23 mknod /dev/rage128_vid c 178 0 | |
24 for Rage128/Rage128Pro chips (althrough it doesn't matter) | |
25 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
26 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
27 ----------------------------------------------------------- | |
2870 | 28 TODO: |
3164 | 29 Highest priority: fbvid.h compatibility |
30 High priority: RGB/BGR 2-32, YVU9, IF09 support | |
3122 | 31 Middle priority: |
32 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? | |
33 OV0_AUTO_FLIP_CNTL | |
34 OV0_FILTER_CNTL | |
35 OV0_VIDEO_KEY_CLR | |
36 OV0_KEY_CNTL | |
3164 | 37 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV |
3122 | 38 YUNV, YVYU, Y41P, Y211, Y41T, Y42T, V422, V655, CLJR |
39 ^^^^ | |
40 YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
2870 | 41 */ |
42 | |
43 #include <linux/config.h> | |
44 #include <linux/version.h> | |
45 #include <linux/module.h> | |
46 #include <linux/types.h> | |
47 #include <linux/kernel.h> | |
48 #include <linux/sched.h> | |
49 #include <linux/mm.h> | |
50 #include <linux/string.h> | |
51 #include <linux/errno.h> | |
52 #include <linux/slab.h> | |
53 #include <linux/pci.h> | |
54 #include <linux/ioport.h> | |
55 #include <linux/init.h> | |
3265 | 56 #include <linux/byteorder/swab.h> |
2870 | 57 |
58 #include "radeon_vid.h" | |
59 #include "radeon.h" | |
60 | |
61 #ifdef CONFIG_MTRR | |
62 #include <asm/mtrr.h> | |
63 #endif | |
64 | |
65 #include <asm/uaccess.h> | |
66 #include <asm/system.h> | |
67 #include <asm/io.h> | |
68 | |
69 #define TRUE 1 | |
70 #define FALSE 0 | |
71 | |
72 #define RADEON_VID_MAJOR 178 | |
73 | |
74 | |
75 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
3198 | 76 #ifdef RAGE128 |
77 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
78 #else | |
79 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
80 #endif | |
2965 | 81 #ifdef MODULE_LICENSE |
2870 | 82 MODULE_LICENSE("GPL"); |
2965 | 83 #endif |
3265 | 84 #ifdef CONFIG_MTRR |
85 MODULE_PARM(mtrr, "i"); | |
86 MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); | |
87 static int mtrr __initdata = 1; | |
88 static struct { int vram; int vram_valid; } smtrr; | |
89 #endif | |
90 MODULE_PARM(swap_fourcc, "i"); | |
91 MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (dont't swap=0(default))"); | |
92 static int swap_fourcc __initdata = 0; | |
2870 | 93 |
3164 | 94 #ifdef RAGE128 |
95 #define RVID_MSG "rage128_vid: " | |
96 #define X_ADJUST 0 | |
97 #else | |
98 #define RVID_MSG "radeon_vid: " | |
99 #define X_ADJUST 8 | |
3198 | 100 #ifndef RADEON |
101 #define RADEON | |
102 #endif | |
3164 | 103 #endif |
104 | |
2870 | 105 typedef struct bes_registers_s |
106 { | |
107 /* base address of yuv framebuffer */ | |
108 uint32_t yuv_base; | |
109 uint32_t fourcc; | |
3278 | 110 uint32_t dest_bpp; |
2870 | 111 /* YUV BES registers */ |
112 uint32_t reg_load_cntl; | |
113 uint32_t h_inc; | |
114 uint32_t step_by; | |
115 uint32_t y_x_start; | |
116 uint32_t y_x_end; | |
117 uint32_t v_inc; | |
118 uint32_t p1_blank_lines_at_top; | |
3019 | 119 uint32_t p23_blank_lines_at_top; |
2870 | 120 uint32_t vid_buf_pitch0_value; |
2944 | 121 uint32_t vid_buf_pitch1_value; |
2870 | 122 uint32_t p1_x_start_end; |
123 uint32_t p2_x_start_end; | |
124 uint32_t p3_x_start_end; | |
3122 | 125 uint32_t base_addr; |
2870 | 126 uint32_t vid_buf0_base_adrs; |
127 /* These ones are for auto flip: maybe in the future */ | |
128 uint32_t vid_buf1_base_adrs; | |
129 uint32_t vid_buf2_base_adrs; | |
130 uint32_t vid_buf3_base_adrs; | |
131 uint32_t vid_buf4_base_adrs; | |
132 uint32_t vid_buf5_base_adrs; | |
133 | |
134 uint32_t p1_v_accum_init; | |
135 uint32_t p1_h_accum_init; | |
3019 | 136 uint32_t p23_v_accum_init; |
2870 | 137 uint32_t p23_h_accum_init; |
138 uint32_t scale_cntl; | |
139 uint32_t exclusive_horz; | |
140 uint32_t auto_flip_cntl; | |
141 uint32_t filter_cntl; | |
3250 | 142 uint32_t key_cntl; |
143 uint32_t test; | |
144 /* Configurable stuff */ | |
145 int double_buff; | |
3278 | 146 |
3247
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Tune up driver through reading and writing /dev/radeon_vid ;)
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147 int brightness; |
7cec2396bde3
Tune up driver through reading and writing /dev/radeon_vid ;)
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148 int saturation; |
3278 | 149 |
150 int ckey_on; | |
2870 | 151 uint32_t graphics_key_clr; |
3278 | 152 uint32_t graphics_key_msk; |
153 | |
3250 | 154 int deinterlace_on; |
155 uint32_t deinterlace_pattern; | |
3278 | 156 |
2870 | 157 } bes_registers_t; |
158 | |
159 typedef struct video_registers_s | |
160 { | |
161 uint32_t name; | |
162 uint32_t value; | |
163 }video_registers_t; | |
164 | |
165 static bes_registers_t besr; | |
166 static video_registers_t vregs[] = | |
167 { | |
168 { OV0_REG_LOAD_CNTL, 0 }, | |
169 { OV0_H_INC, 0 }, | |
170 { OV0_STEP_BY, 0 }, | |
171 { OV0_Y_X_START, 0 }, | |
172 { OV0_Y_X_END, 0 }, | |
173 { OV0_V_INC, 0 }, | |
174 { OV0_P1_BLANK_LINES_AT_TOP, 0 }, | |
3019 | 175 { OV0_P23_BLANK_LINES_AT_TOP, 0 }, |
2870 | 176 { OV0_VID_BUF_PITCH0_VALUE, 0 }, |
2944 | 177 { OV0_VID_BUF_PITCH1_VALUE, 0 }, |
2870 | 178 { OV0_P1_X_START_END, 0 }, |
179 { OV0_P2_X_START_END, 0 }, | |
180 { OV0_P3_X_START_END, 0 }, | |
3122 | 181 { OV0_BASE_ADDR, 0 }, |
2870 | 182 { OV0_VID_BUF0_BASE_ADRS, 0 }, |
183 { OV0_VID_BUF1_BASE_ADRS, 0 }, | |
184 { OV0_VID_BUF2_BASE_ADRS, 0 }, | |
185 { OV0_VID_BUF3_BASE_ADRS, 0 }, | |
186 { OV0_VID_BUF4_BASE_ADRS, 0 }, | |
187 { OV0_VID_BUF5_BASE_ADRS, 0 }, | |
188 { OV0_P1_V_ACCUM_INIT, 0 }, | |
189 { OV0_P1_H_ACCUM_INIT, 0 }, | |
3019 | 190 { OV0_P23_V_ACCUM_INIT, 0 }, |
2870 | 191 { OV0_P23_H_ACCUM_INIT, 0 }, |
192 { OV0_SCALE_CNTL, 0 }, | |
193 { OV0_EXCLUSIVE_HORZ, 0 }, | |
194 { OV0_AUTO_FLIP_CNTL, 0 }, | |
195 { OV0_FILTER_CNTL, 0 }, | |
196 { OV0_COLOUR_CNTL, 0 }, | |
3278 | 197 { OV0_GRAPHICS_KEY_CLR, 0 }, |
2870 | 198 { OV0_GRAPHICS_KEY_MSK, 0 }, |
199 { OV0_KEY_CNTL, 0 }, | |
200 { OV0_TEST, 0 } | |
201 }; | |
202 | |
203 static uint32_t radeon_vid_in_use = 0; | |
204 | |
205 static uint8_t *radeon_mmio_base = 0; | |
206 static uint32_t radeon_mem_base = 0; | |
3019 | 207 static int32_t radeon_overlay_off = 0; |
2870 | 208 static uint32_t radeon_ram_size = 0; |
3263 | 209 #define PARAM_BUFF_SIZE 4096 |
210 static uint8_t *radeon_param_buff = NULL; | |
211 static uint32_t radeon_param_buff_size=0; | |
212 static uint32_t radeon_param_buff_len=0; /* real length of buffer */ | |
2870 | 213 static mga_vid_config_t radeon_config; |
214 | |
2951 | 215 #undef DEBUG |
2870 | 216 #if DEBUG |
217 #define RTRACE printk | |
218 #else | |
219 #define RTRACE(...) ((void)0) | |
220 #endif | |
221 | |
3122 | 222 static char *fourcc_format_name(int format) |
223 { | |
224 switch(format) | |
225 { | |
226 case IMGFMT_RGB8: return("RGB 8-bit"); | |
227 case IMGFMT_RGB15: return("RGB 15-bit"); | |
228 case IMGFMT_RGB16: return("RGB 16-bit"); | |
229 case IMGFMT_RGB24: return("RGB 24-bit"); | |
230 case IMGFMT_RGB32: return("RGB 32-bit"); | |
231 case IMGFMT_BGR8: return("BGR 8-bit"); | |
232 case IMGFMT_BGR15: return("BGR 15-bit"); | |
233 case IMGFMT_BGR16: return("BGR 16-bit"); | |
234 case IMGFMT_BGR24: return("BGR 24-bit"); | |
235 case IMGFMT_BGR32: return("BGR 32-bit"); | |
236 case IMGFMT_YVU9: return("Planar YVU9"); | |
237 case IMGFMT_IF09: return("Planar IF09"); | |
238 case IMGFMT_YV12: return("Planar YV12"); | |
239 case IMGFMT_I420: return("Planar I420"); | |
240 case IMGFMT_IYUV: return("Planar IYUV"); | |
241 case IMGFMT_CLPL: return("Planar CLPL"); | |
3198 | 242 case IMGFMT_Y800: return("Planar Y800"); |
243 case IMGFMT_Y8: return("Planar Y8"); | |
244 case IMGFMT_IUYV: return("Packed IUYV"); | |
245 case IMGFMT_IY41: return("Packed IY41"); | |
3122 | 246 case IMGFMT_IYU1: return("Packed IYU1"); |
247 case IMGFMT_IYU2: return("Packed IYU2"); | |
248 case IMGFMT_UYVY: return("Packed UYVY"); | |
249 case IMGFMT_UYNV: return("Packed UYNV"); | |
250 case IMGFMT_cyuv: return("Packed CYUV"); | |
3198 | 251 case IMGFMT_Y422: return("Packed Y422"); |
3122 | 252 case IMGFMT_YUY2: return("Packed YUY2"); |
253 case IMGFMT_YUNV: return("Packed YUNV"); | |
254 case IMGFMT_YVYU: return("Packed YVYU"); | |
255 case IMGFMT_Y41P: return("Packed Y41P"); | |
256 case IMGFMT_Y211: return("Packed Y211"); | |
257 case IMGFMT_Y41T: return("Packed Y41T"); | |
258 case IMGFMT_Y42T: return("Packed Y42T"); | |
259 case IMGFMT_V422: return("Packed V422"); | |
260 case IMGFMT_V655: return("Packed V655"); | |
261 case IMGFMT_CLJR: return("Packed CLJR"); | |
262 case IMGFMT_YUVP: return("Packed YUVP"); | |
263 case IMGFMT_UYVP: return("Packed UYVP"); | |
3198 | 264 case IMGFMT_MPEGPES: return("Mpeg PES"); |
3122 | 265 } |
266 return("Unknown"); | |
267 } | |
268 | |
2870 | 269 |
270 /* | |
271 * IO macros | |
272 */ | |
273 | |
274 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
275 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
276 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
277 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
278 | |
3278 | 279 static uint32_t radeon_vid_get_dbpp( void ) |
280 { | |
281 uint32_t dbpp,retval; | |
282 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
283 switch(dbpp) | |
284 { | |
285 case DST_8BPP: retval = 8; break; | |
286 case DST_15BPP: retval = 15; break; | |
287 case DST_16BPP: retval = 16; break; | |
288 case DST_24BPP: retval = 24; break; | |
289 default: retval=32; break; | |
290 } | |
291 return retval; | |
292 } | |
293 | |
3265 | 294 static void __init radeon_vid_save_state( void ) |
2870 | 295 { |
296 size_t i; | |
297 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
298 vregs[i].value = INREG(vregs[i].name); | |
299 } | |
300 | |
3265 | 301 static void __exit radeon_vid_restore_state( void ) |
2870 | 302 { |
303 size_t i; | |
304 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
305 OUTREG(vregs[i].name,vregs[i].value); | |
306 } | |
307 | |
308 static void radeon_vid_stop_video( void ) | |
309 { | |
310 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
311 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
312 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
313 OUTREG(OV0_FILTER_CNTL, 0x0000000f); | |
314 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
315 OUTREG(OV0_TEST, 0); | |
316 } | |
317 | |
318 static void radeon_vid_display_video( void ) | |
319 { | |
320 int bes_flags; | |
3164 | 321 RTRACE(RVID_MSG"OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
322 RTRACE(RVID_MSG"OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs); | |
323 RTRACE(RVID_MSG"OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 324 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
3164 | 325 RTRACE(RVID_MSG"OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n" |
2951 | 326 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end); |
3164 | 327 RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n" |
2951 | 328 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init); |
2870 | 329 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
330 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
2965 | 331 |
2870 | 332 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
333 | |
3250 | 334 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3266
ff90589b635f
Fixed single buffering problems and -vo mga compatibility by number of buffers
nick
parents:
3265
diff
changeset
|
335 |
ff90589b635f
Fixed single buffering problems and -vo mga compatibility by number of buffers
nick
parents:
3265
diff
changeset
|
336 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
ff90589b635f
Fixed single buffering problems and -vo mga compatibility by number of buffers
nick
parents:
3265
diff
changeset
|
337 (besr.saturation << 8) | |
ff90589b635f
Fixed single buffering problems and -vo mga compatibility by number of buffers
nick
parents:
3265
diff
changeset
|
338 (besr.saturation << 16)); |
3278 | 339 |
340 if(besr.ckey_on) | |
341 { | |
342 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
343 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
344 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_FALSE|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); | |
345 } | |
346 else OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
2870 | 347 |
348 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
349 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2965 | 350 |
2870 | 351 OUTREG(OV0_H_INC, besr.h_inc); |
352 OUTREG(OV0_STEP_BY, besr.step_by); | |
353 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
354 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
355 OUTREG(OV0_V_INC, besr.v_inc); | |
356 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
3164 | 357 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
2870 | 358 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
2944 | 359 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 360 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
361 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
362 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
3198 | 363 #if 0 |
3122 | 364 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
365 #endif | |
2870 | 366 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
367 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
368 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
369 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
370 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
371 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
372 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
373 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
374 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
3164 | 375 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
2870 | 376 |
377 bes_flags = SCALER_ENABLE | | |
378 SCALER_SMART_SWITCH | | |
379 SCALER_HORZ_PICK_NEAREST; | |
3250 | 380 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; |
381 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
3198 | 382 #ifdef RAGE128 |
383 bes_flags |= SCALER_BURST_PER_PLANE; | |
384 #endif | |
2870 | 385 switch(besr.fourcc) |
386 { | |
387 case IMGFMT_RGB15: | |
388 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
389 case IMGFMT_RGB16: | |
390 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
391 case IMGFMT_RGB24: | |
392 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
393 case IMGFMT_RGB32: | |
394 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
3164 | 395 /* 4:1:0*/ |
396 case IMGFMT_IF09: | |
2870 | 397 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
3164 | 398 /* 4:2:0 */ |
3122 | 399 case IMGFMT_IYUV: |
2870 | 400 case IMGFMT_I420: |
3164 | 401 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
402 /* 4:2:2 */ | |
403 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
2870 | 404 case IMGFMT_YUY2: |
405 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
406 } | |
3164 | 407 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags); |
2870 | 408 OUTREG(OV0_SCALE_CNTL, bes_flags); |
409 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
410 } | |
411 | |
3278 | 412 void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B) |
413 { | |
414 besr.ckey_on = ckey_on; | |
415 if(radeon_vid_get_dbpp() == 16) | |
416 { /* 5.6.5 mode, | |
417 note that these values depend on DAC_CNTL.EXPAND_MODE setting */ | |
418 R = (R<<3); | |
419 G = (G<<2); | |
420 B = (B<<3); | |
421 besr.graphics_key_msk=((R|0x7)<<16)|((G|0x3)<<8)|(B|0x7)|(0xff<<24); | |
422 } | |
423 else besr.graphics_key_msk = ((R)<<16)|((G) <<8)|(B)|(0xff<<24); | |
424 besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24); | |
425 } | |
426 | |
427 | |
2951 | 428 #define XXX_SRC_X 0 |
429 #define XXX_SRC_Y 0 | |
2870 | 430 |
2944 | 431 #define XXX_WIDTH config->src_width |
432 #define XXX_HEIGHT config->src_height | |
2870 | 433 |
2951 | 434 #define XXX_DRW_W config->dest_width |
435 #define XXX_DRW_H config->dest_height | |
2925 | 436 |
2870 | 437 static int radeon_vid_init_video( mga_vid_config_t *config ) |
438 { | |
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439 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 440 int is_420; |
3164 | 441 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 442 ,(uint32_t)config->version |
2951 | 443 ,(uint32_t)config->format |
2870 | 444 ,(uint32_t)config->card_type |
445 ,(uint32_t)config->ram_size | |
446 ,(uint32_t)config->src_width | |
447 ,(uint32_t)config->src_height | |
448 ,(uint32_t)config->x_org | |
449 ,(uint32_t)config->y_org | |
450 ,(uint32_t)config->dest_width | |
451 ,(uint32_t)config->dest_height | |
452 ,(uint32_t)config->frame_size | |
453 ,(uint32_t)config->num_frames); | |
2917 | 454 radeon_vid_stop_video(); |
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455 left = XXX_SRC_X << 16; |
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456 top = XXX_SRC_Y << 16; |
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457 src_h = config->src_height; |
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458 src_w = config->src_width; |
2870 | 459 switch(config->format) |
460 { | |
461 case IMGFMT_RGB15: | |
462 case IMGFMT_BGR15: | |
463 case IMGFMT_RGB16: | |
464 case IMGFMT_BGR16: | |
465 case IMGFMT_RGB24: | |
466 case IMGFMT_BGR24: | |
467 case IMGFMT_RGB32: | |
468 case IMGFMT_BGR32: | |
3164 | 469 /* 4:1:0 */ |
470 case IMGFMT_IF09: | |
2870 | 471 case IMGFMT_YVU9: |
3164 | 472 /* 4:2:0 */ |
2870 | 473 case IMGFMT_IYUV: |
474 case IMGFMT_YV12: | |
475 case IMGFMT_I420: | |
3164 | 476 /* 4:2:2 */ |
477 case IMGFMT_UYVY: | |
2870 | 478 case IMGFMT_YUY2: |
479 break; | |
480 default: | |
3164 | 481 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
2870 | 482 return -1; |
483 } | |
3019 | 484 is_420 = 0; |
3122 | 485 if(config->format == IMGFMT_YV12 || |
486 config->format == IMGFMT_I420 || | |
487 config->format == IMGFMT_IYUV) is_420 = 1; | |
2951 | 488 switch(config->format) |
489 { | |
3164 | 490 /* 4:1:0 */ |
2951 | 491 case IMGFMT_YVU9: |
3164 | 492 case IMGFMT_IF09: |
493 /* 4:2:0 */ | |
2951 | 494 case IMGFMT_IYUV: |
3164 | 495 case IMGFMT_YV12: |
496 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
497 /* 4:2:2 */ | |
498 default: | |
2951 | 499 case IMGFMT_UYVY: |
500 case IMGFMT_YUY2: | |
501 case IMGFMT_RGB15: | |
502 case IMGFMT_BGR15: | |
503 case IMGFMT_RGB16: | |
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504 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 505 case IMGFMT_RGB24: |
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506 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 507 case IMGFMT_RGB32: |
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508 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 509 } |
510 | |
3278 | 511 besr.dest_bpp = radeon_vid_get_dbpp(); |
2870 | 512 besr.fourcc = config->format; |
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513 besr.v_inc = (src_h << 20) / XXX_DRW_H; |
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514 h_inc = (src_w << 12) / XXX_DRW_W; |
2944 | 515 step_by = 1; |
2870 | 516 |
2944 | 517 while(h_inc >= (2 << 12)) { |
518 step_by++; | |
519 h_inc >>= 1; | |
2870 | 520 } |
521 | |
522 /* keep everything in 16.16 */ | |
3164 | 523 besr.base_addr = radeon_mem_base; |
3019 | 524 if(is_420) |
525 { | |
3164 | 526 uint32_t d1line,d2line,d3line; |
527 d1line = top*pitch; | |
528 d2line = src_h*pitch+(d1line>>1); | |
529 d3line = d2line+((src_h*pitch)>>2); | |
530 d1line += (left >> 16) & ~15; | |
531 d2line += (left >> 17) & ~15; | |
532 d3line += (left >> 17) & ~15; | |
533 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
534 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
535 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
536 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
537 { | |
538 uint32_t tmp; | |
539 tmp = besr.vid_buf1_base_adrs; | |
540 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
541 besr.vid_buf2_base_adrs = tmp; | |
542 } | |
3019 | 543 } |
544 else | |
545 { | |
546 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
3198 | 547 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; |
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548 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 549 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
550 } | |
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551 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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552 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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553 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 554 |
2951 | 555 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 556 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 557 ((tmp << 12) & 0xf0000000); |
2870 | 558 |
2951 | 559 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 560 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 561 ((tmp << 12) & 0x70000000); |
562 tmp = (top & 0x0000ffff) + 0x00018000; | |
3122 | 563 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
564 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
3019 | 565 |
566 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
3122 | 567 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
568 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
3019 | 569 |
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570 leftUV = (left >> 17) & 15; |
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571 left = (left >> 16) & 15; |
2944 | 572 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
573 besr.step_by = step_by | (step_by << 8); | |
3164 | 574 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
575 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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576 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
3122 | 577 if(is_420) |
578 { | |
579 src_h = (src_h + 1) >> 1; | |
580 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
581 } | |
582 else besr.p23_blank_lines_at_top = 0; | |
2870 | 583 besr.vid_buf_pitch0_value = pitch; |
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584 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
3164 | 585 RTRACE(RVID_MSG"BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
586 RTRACE(RVID_MSG"BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); | |
587 RTRACE(RVID_MSG"BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 588 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
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589 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
3164 | 590 src_w>>=1; |
591 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
592 besr.p3_x_start_end = besr.p2_x_start_end; | |
2870 | 593 return 0; |
594 } | |
595 | |
596 static void radeon_vid_frame_sel(int frame) | |
597 { | |
3066 | 598 uint32_t off0,off1,off2; |
3250 | 599 if(!besr.double_buff) return; |
3066 | 600 if(frame%2) |
601 { | |
602 off0 = besr.vid_buf3_base_adrs; | |
603 off1 = besr.vid_buf4_base_adrs; | |
604 off2 = besr.vid_buf5_base_adrs; | |
605 } | |
606 else | |
607 { | |
608 off0 = besr.vid_buf0_base_adrs; | |
609 off1 = besr.vid_buf1_base_adrs; | |
610 off2 = besr.vid_buf2_base_adrs; | |
611 } | |
2917 | 612 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
613 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 614 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
615 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
616 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 617 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 618 } |
619 | |
3250 | 620 static void radeon_vid_make_default(void) |
621 { | |
622 besr.deinterlace_pattern = 0x900AAAAA; | |
623 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
624 besr.deinterlace_on=1; | |
625 besr.double_buff=1; | |
626 } | |
627 | |
628 | |
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629 static void radeon_vid_preset(void) |
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630 { |
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631 unsigned tmp; |
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632 tmp = INREG(OV0_COLOUR_CNTL); |
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633 besr.saturation = (tmp>>8)&0x1f; |
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634 besr.brightness = tmp & 0x7f; |
3250 | 635 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); |
636 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); | |
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637 } |
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638 |
2951 | 639 static int video_on = 0; |
640 | |
2870 | 641 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
642 { | |
643 int frame; | |
644 | |
645 switch(cmd) | |
646 { | |
647 case MGA_VID_CONFIG: | |
648 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base); | |
649 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base); | |
3164 | 650 RTRACE(RVID_MSG"Received configuration\n"); |
2870 | 651 |
652 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
653 { | |
3164 | 654 printk(RVID_MSG"failed copy from userspace\n"); |
3019 | 655 return -EFAULT; |
2870 | 656 } |
657 if(radeon_config.version != MGA_VID_VERSION){ | |
3164 | 658 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
3019 | 659 return -EFAULT; |
2870 | 660 } |
661 | |
662 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
3164 | 663 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
3019 | 664 return -EFAULT; |
2870 | 665 } |
666 | |
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667 if(radeon_config.num_frames<1){ |
3164 | 668 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
3019 | 669 return -EFAULT; |
2870 | 670 } |
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671 if(radeon_config.num_frames==1) besr.double_buff=0; |
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672 if(!besr.double_buff) radeon_config.num_frames=1; |
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673 else radeon_config.num_frames=2; |
2870 | 674 radeon_config.card_type = 0; |
675 radeon_config.ram_size = radeon_ram_size; | |
3019 | 676 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
677 radeon_overlay_off &= 0xffff0000; | |
678 if(radeon_overlay_off < 0){ | |
3164 | 679 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
3019 | 680 return -EFAULT; |
681 } | |
3164 | 682 RTRACE(RVID_MSG"using video overlay at offset %p\n",radeon_overlay_off); |
2870 | 683 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
684 { | |
3164 | 685 printk(RVID_MSG"failed copy to userspace\n"); |
3019 | 686 return -EFAULT; |
2870 | 687 } |
3278 | 688 radeon_vid_set_color_key(radeon_config.colkey_on, |
689 radeon_config.colkey_red, | |
690 radeon_config.colkey_green, | |
691 radeon_config.colkey_blue); | |
3265 | 692 if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); |
3164 | 693 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
2870 | 694 return radeon_vid_init_video(&radeon_config); |
695 break; | |
696 | |
697 case MGA_VID_ON: | |
3164 | 698 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
699 radeon_vid_display_video(); | |
2951 | 700 video_on = 1; |
2870 | 701 break; |
702 | |
703 case MGA_VID_OFF: | |
3164 | 704 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
2951 | 705 if(video_on) radeon_vid_stop_video(); |
706 video_on = 0; | |
2870 | 707 break; |
708 | |
709 case MGA_VID_FSEL: | |
710 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
711 { | |
3164 | 712 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
2870 | 713 return(-EFAULT); |
714 } | |
715 radeon_vid_frame_sel(frame); | |
716 break; | |
717 | |
718 default: | |
3164 | 719 printk(RVID_MSG"Invalid ioctl\n"); |
2870 | 720 return (-EINVAL); |
721 } | |
722 | |
723 return 0; | |
724 } | |
725 | |
726 struct ati_card_id_s | |
727 { | |
3164 | 728 const int id; |
729 const char name[17]; | |
730 }; | |
731 | |
732 const struct ati_card_id_s ati_card_ids[]= | |
2870 | 733 { |
3164 | 734 #ifdef RAGE128 |
735 /* | |
736 This driver should be compatible with Rage128 (pro) chips. | |
737 (include adaptive deinterlacing!!!). | |
738 Moreover: the same logic can be used with Mach64 chips. | |
739 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
740 but they are incompatible by i/o ports. So if enthusiasts will want | |
741 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
742 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
743 fourccs (422 and 420 formats only). | |
744 */ | |
745 /* Rage128 Pro GL */ | |
746 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
747 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
748 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
749 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
750 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
751 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
752 /* Rage128 Pro VR */ | |
753 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
754 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
755 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
756 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
757 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
758 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
759 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
760 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
761 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
762 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
763 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
764 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
765 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
766 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
767 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
768 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
769 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
770 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
771 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
772 /* Rage128 GL */ | |
773 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
774 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
775 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
776 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
777 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
778 /* Rage128 VR */ | |
779 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
780 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
781 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
782 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
783 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
784 /* Rage128 M3 */ | |
3198 | 785 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, |
786 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
3164 | 787 /* Rage128 Pro Ultra */ |
3198 | 788 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, |
789 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
790 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
3164 | 791 #else |
792 /* Radeons (indeed: Rage 256 Pro ;) */ | |
2870 | 793 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
794 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
795 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
796 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
797 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
798 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
799 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
800 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
801 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
802 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
803 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
3164 | 804 #endif |
2870 | 805 }; |
806 | |
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807 static int detected_chip; |
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808 |
3265 | 809 static int __init radeon_vid_config_card(void) |
2870 | 810 { |
811 struct pci_dev *dev = NULL; | |
812 size_t i; | |
813 | |
814 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
815 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
816 break; | |
3122 | 817 if(!dev) |
2870 | 818 { |
3164 | 819 printk(RVID_MSG"No supported cards found\n"); |
2870 | 820 return FALSE; |
821 } | |
822 | |
823 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
824 radeon_mem_base = dev->resource[0].start; | |
825 | |
3164 | 826 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
827 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
2870 | 828 |
3122 | 829 /* video memory size */ |
830 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
831 | |
3164 | 832 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
3122 | 833 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
834 radeon_ram_size /= 0x100000; | |
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835 detected_chip = i; |
3164 | 836 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
2870 | 837 |
838 return TRUE; | |
839 } | |
840 | |
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841 #define PARAM_BRIGHTNESS "brightness=" |
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842 #define PARAM_SATURATION "saturation=" |
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843 #define PARAM_DOUBLE_BUFF "double_buff=" |
3250 | 844 #define PARAM_DEINTERLACE "deinterlace=" |
845 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" | |
2870 | 846 |
3263 | 847 static void radeon_param_buff_fill( void ) |
2870 | 848 { |
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849 unsigned len,saturation; |
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850 long brightness; |
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851 brightness = besr.brightness; |
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852 saturation = besr.saturation; |
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853 len = 0; |
3263 | 854 len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); |
855 len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); | |
856 len += sprintf(&radeon_param_buff[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000); | |
857 len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); | |
858 len += sprintf(&radeon_param_buff[len],"Overlay offset: %p\n",radeon_overlay_off); | |
3269 | 859 #ifdef CONFIG_MTRR |
3265 | 860 len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); |
3269 | 861 #endif |
3278 | 862 if(besr.ckey_on) len += sprintf(&radeon_param_buff[len],"Last used color_key=%X (mask=%X)\n",besr.graphics_key_clr,besr.graphics_key_msk); |
3265 | 863 len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); |
3278 | 864 len += sprintf(&radeon_param_buff[len],"Last BPP: %u\n",besr.dest_bpp); |
3263 | 865 len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); |
866 len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); | |
867 len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); | |
868 len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); | |
869 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",brightness); | |
870 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); | |
871 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); | |
872 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); | |
873 radeon_param_buff_len = len; | |
874 } | |
875 | |
876 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
877 { | |
878 uint32_t size; | |
879 if(!radeon_param_buff) return -ESPIPE; | |
880 if(!(*ppos)) radeon_param_buff_fill(); | |
881 if(*ppos >= radeon_param_buff_len) return 0; | |
882 size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); | |
883 memcpy(buf,radeon_param_buff,size); | |
884 *ppos += size; | |
885 return size; | |
2870 | 886 } |
887 | |
888 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
889 { | |
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890 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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891 { |
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892 long brightness; |
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893 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
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894 if(brightness >= -64 && brightness <= 63) |
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895 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | |
3250 | 896 (besr.saturation << 8) | |
897 (besr.saturation << 16)); | |
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898 } |
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899 else |
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900 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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901 { |
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902 long saturation; |
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903 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); |
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904 if(saturation >= 0 && saturation <= 31) |
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905 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
3250 | 906 (saturation << 8) | |
907 (saturation << 16)); | |
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908 } |
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909 else |
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910 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) |
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911 { |
3250 | 912 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; |
913 else besr.double_buff = 0; | |
914 } | |
915 else | |
916 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) | |
917 { | |
918 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; | |
919 else besr.deinterlace_on = 0; | |
920 } | |
921 else | |
922 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) | |
923 { | |
924 long dpat; | |
925 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); | |
926 OUTREG(OV0_DEINTERLACE_PATTERN, dpat); | |
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927 } |
3263 | 928 else count = -EIO; |
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929 radeon_vid_preset(); |
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930 return count; |
2870 | 931 } |
932 | |
933 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
934 { | |
935 | |
3164 | 936 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
3019 | 937 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 938 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
939 { | |
3164 | 940 printk(RVID_MSG"error mapping video memory\n"); |
2870 | 941 return(-EAGAIN); |
942 } | |
943 | |
944 return(0); | |
945 } | |
946 | |
947 static int radeon_vid_release(struct inode *inode, struct file *file) | |
948 { | |
949 radeon_vid_in_use = 0; | |
950 radeon_vid_stop_video(); | |
951 | |
952 MOD_DEC_USE_COUNT; | |
953 return 0; | |
954 } | |
955 | |
956 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
957 { | |
958 return -ESPIPE; | |
959 } | |
960 | |
961 static int radeon_vid_open(struct inode *inode, struct file *file) | |
962 { | |
963 int minor = MINOR(inode->i_rdev); | |
964 | |
965 if(minor != 0) | |
966 return(-ENXIO); | |
967 | |
968 if(radeon_vid_in_use == 1) | |
969 return(-EBUSY); | |
970 | |
971 radeon_vid_in_use = 1; | |
972 MOD_INC_USE_COUNT; | |
973 return(0); | |
974 } | |
975 | |
976 #if LINUX_VERSION_CODE >= 0x020400 | |
977 static struct file_operations radeon_vid_fops = | |
978 { | |
979 llseek: radeon_vid_lseek, | |
980 read: radeon_vid_read, | |
981 write: radeon_vid_write, | |
982 ioctl: radeon_vid_ioctl, | |
983 mmap: radeon_vid_mmap, | |
984 open: radeon_vid_open, | |
985 release: radeon_vid_release | |
986 }; | |
987 #else | |
988 static struct file_operations radeon_vid_fops = | |
989 { | |
990 radeon_vid_lseek, | |
991 radeon_vid_read, | |
992 radeon_vid_write, | |
993 NULL, | |
994 NULL, | |
995 radeon_vid_ioctl, | |
996 radeon_vid_mmap, | |
997 radeon_vid_open, | |
998 NULL, | |
999 radeon_vid_release | |
1000 }; | |
1001 #endif | |
1002 | |
1003 /* | |
1004 * Main Initialization Function | |
1005 */ | |
1006 | |
3265 | 1007 static int __init radeon_vid_initialize(void) |
2870 | 1008 { |
1009 radeon_vid_in_use = 0; | |
3164 | 1010 #ifdef RAGE128 |
1011 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
1012 #else | |
1013 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
1014 #endif | |
2870 | 1015 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
1016 { | |
3164 | 1017 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
2870 | 1018 return -EIO; |
1019 } | |
1020 | |
1021 if (!radeon_vid_config_card()) | |
1022 { | |
3164 | 1023 printk(RVID_MSG"can't configure this card\n"); |
2870 | 1024 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
1025 return -EINVAL; | |
1026 } | |
3263 | 1027 radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); |
1028 if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; | |
2870 | 1029 radeon_vid_save_state(); |
3250 | 1030 radeon_vid_make_default(); |
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1031 radeon_vid_preset(); |
3265 | 1032 #ifdef CONFIG_MTRR |
1033 if (mtrr) { | |
1034 smtrr.vram = mtrr_add(radeon_mem_base, | |
1035 radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); | |
1036 smtrr.vram_valid = 1; | |
1037 /* let there be speed */ | |
1038 printk(RVID_MSG"MTRR set to ON\n"); | |
1039 } | |
1040 #endif /* CONFIG_MTRR */ | |
2870 | 1041 return(0); |
1042 } | |
1043 | |
3265 | 1044 int __init init_module(void) |
2870 | 1045 { |
1046 return radeon_vid_initialize(); | |
1047 } | |
1048 | |
3265 | 1049 void __exit cleanup_module(void) |
2870 | 1050 { |
1051 radeon_vid_restore_state(); | |
1052 if(radeon_mmio_base) | |
1053 iounmap(radeon_mmio_base); | |
3263 | 1054 kfree(radeon_param_buff); |
3164 | 1055 RTRACE(RVID_MSG"Cleaning up module\n"); |
2870 | 1056 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
3265 | 1057 #ifdef CONFIG_MTRR |
1058 if (smtrr.vram_valid) | |
1059 mtrr_del(smtrr.vram, radeon_mem_base, | |
1060 radeon_ram_size*0x100000); | |
1061 #endif /* CONFIG_MTRR */ | |
2870 | 1062 } |
1063 |