Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3825:7735c5a87121
setuid hack disabled
author | arpi |
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date | Fri, 28 Dec 2001 02:04:06 +0000 |
parents | f5cc15e11d6e |
children | 80d0864322b9 |
rev | line source |
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2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
3366 | 15 * |
16 * SPECIAL THANKS TO: Hans-Peter Raschke for active testing and hacking | |
17 * Rage128(pro) stuff of this driver. | |
2870 | 18 */ |
19 | |
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20 #define RADEON_VID_VERSION "1.1.2" |
2951 | 21 |
2870 | 22 /* |
23 It's entirely possible this major conflicts with something else | |
24 mknod /dev/radeon_vid c 178 0 | |
3164 | 25 or |
26 mknod /dev/rage128_vid c 178 0 | |
3380 | 27 for Rage128/Rage128Pro chips (although it doesn't matter) |
3164 | 28 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
29 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
30 ----------------------------------------------------------- | |
2870 | 31 TODO: |
3164 | 32 Highest priority: fbvid.h compatibility |
3366 | 33 High priority: Fixing BUGS |
34 Middle priority: RGB/BGR 2-32, YVU9, IF09 support | |
35 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV, YUNV, YVYU, Y41P, Y211, Y41T, | |
36 ^^^^ | |
37 Y42T, V422, V655, CLJR, YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
38 ........................................................... | |
39 BUGS and LACKS: | |
40 Color and video keys don't work | |
41 Contrast and brightness are unconfigurable on radeons | |
2870 | 42 */ |
43 | |
44 #include <linux/config.h> | |
45 #include <linux/version.h> | |
46 #include <linux/module.h> | |
47 #include <linux/types.h> | |
48 #include <linux/kernel.h> | |
49 #include <linux/sched.h> | |
50 #include <linux/mm.h> | |
51 #include <linux/string.h> | |
52 #include <linux/errno.h> | |
53 #include <linux/slab.h> | |
54 #include <linux/pci.h> | |
55 #include <linux/ioport.h> | |
56 #include <linux/init.h> | |
3265 | 57 #include <linux/byteorder/swab.h> |
2870 | 58 |
59 #include "radeon_vid.h" | |
60 #include "radeon.h" | |
61 | |
62 #ifdef CONFIG_MTRR | |
63 #include <asm/mtrr.h> | |
64 #endif | |
65 | |
66 #include <asm/uaccess.h> | |
67 #include <asm/system.h> | |
68 #include <asm/io.h> | |
69 | |
70 #define TRUE 1 | |
71 #define FALSE 0 | |
72 | |
73 #define RADEON_VID_MAJOR 178 | |
74 | |
75 | |
76 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
3198 | 77 #ifdef RAGE128 |
78 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
79 #else | |
80 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
81 #endif | |
2965 | 82 #ifdef MODULE_LICENSE |
2870 | 83 MODULE_LICENSE("GPL"); |
2965 | 84 #endif |
3265 | 85 #ifdef CONFIG_MTRR |
86 MODULE_PARM(mtrr, "i"); | |
87 MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); | |
88 static int mtrr __initdata = 1; | |
89 static struct { int vram; int vram_valid; } smtrr; | |
90 #endif | |
91 MODULE_PARM(swap_fourcc, "i"); | |
92 MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (dont't swap=0(default))"); | |
93 static int swap_fourcc __initdata = 0; | |
2870 | 94 |
3164 | 95 #ifdef RAGE128 |
96 #define RVID_MSG "rage128_vid: " | |
97 #define X_ADJUST 0 | |
98 #else | |
99 #define RVID_MSG "radeon_vid: " | |
100 #define X_ADJUST 8 | |
3198 | 101 #ifndef RADEON |
102 #define RADEON | |
103 #endif | |
3164 | 104 #endif |
105 | |
3348 | 106 #undef DEBUG |
107 #if DEBUG | |
108 #define RTRACE printk | |
109 #else | |
110 #define RTRACE(...) ((void)0) | |
111 #endif | |
112 | |
2870 | 113 typedef struct bes_registers_s |
114 { | |
115 /* base address of yuv framebuffer */ | |
116 uint32_t yuv_base; | |
117 uint32_t fourcc; | |
3278 | 118 uint32_t dest_bpp; |
2870 | 119 /* YUV BES registers */ |
120 uint32_t reg_load_cntl; | |
121 uint32_t h_inc; | |
122 uint32_t step_by; | |
123 uint32_t y_x_start; | |
124 uint32_t y_x_end; | |
125 uint32_t v_inc; | |
126 uint32_t p1_blank_lines_at_top; | |
3019 | 127 uint32_t p23_blank_lines_at_top; |
2870 | 128 uint32_t vid_buf_pitch0_value; |
2944 | 129 uint32_t vid_buf_pitch1_value; |
2870 | 130 uint32_t p1_x_start_end; |
131 uint32_t p2_x_start_end; | |
132 uint32_t p3_x_start_end; | |
3122 | 133 uint32_t base_addr; |
2870 | 134 uint32_t vid_buf0_base_adrs; |
135 /* These ones are for auto flip: maybe in the future */ | |
136 uint32_t vid_buf1_base_adrs; | |
137 uint32_t vid_buf2_base_adrs; | |
138 uint32_t vid_buf3_base_adrs; | |
139 uint32_t vid_buf4_base_adrs; | |
140 uint32_t vid_buf5_base_adrs; | |
141 | |
142 uint32_t p1_v_accum_init; | |
143 uint32_t p1_h_accum_init; | |
3019 | 144 uint32_t p23_v_accum_init; |
2870 | 145 uint32_t p23_h_accum_init; |
146 uint32_t scale_cntl; | |
147 uint32_t exclusive_horz; | |
148 uint32_t auto_flip_cntl; | |
149 uint32_t filter_cntl; | |
3250 | 150 uint32_t key_cntl; |
151 uint32_t test; | |
152 /* Configurable stuff */ | |
153 int double_buff; | |
3278 | 154 |
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155 int brightness; |
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156 int saturation; |
3278 | 157 |
158 int ckey_on; | |
2870 | 159 uint32_t graphics_key_clr; |
3278 | 160 uint32_t graphics_key_msk; |
161 | |
3250 | 162 int deinterlace_on; |
163 uint32_t deinterlace_pattern; | |
3278 | 164 |
2870 | 165 } bes_registers_t; |
166 | |
167 typedef struct video_registers_s | |
168 { | |
3348 | 169 #ifdef DEBUG |
3305 | 170 const char * sname; |
3348 | 171 #endif |
2870 | 172 uint32_t name; |
173 uint32_t value; | |
174 }video_registers_t; | |
175 | |
176 static bes_registers_t besr; | |
3348 | 177 |
178 #ifdef DEBUG | |
179 #define DECLARE_VREG(name) { #name, name, 0 } | |
180 #else | |
181 #define DECLARE_VREG(name) { name, 0 } | |
182 #endif | |
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183 #ifdef DEBUG |
2870 | 184 static video_registers_t vregs[] = |
185 { | |
3473 | 186 DECLARE_VREG(VIDEOMUX_CNTL), |
187 DECLARE_VREG(VIPPAD_MASK), | |
188 DECLARE_VREG(VIPPAD1_A), | |
189 DECLARE_VREG(VIPPAD1_EN), | |
190 DECLARE_VREG(VIPPAD1_Y), | |
3348 | 191 DECLARE_VREG(OV0_Y_X_START), |
192 DECLARE_VREG(OV0_Y_X_END), | |
193 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
194 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
195 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
196 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
197 DECLARE_VREG(OV0_SCALE_CNTL), | |
198 DECLARE_VREG(OV0_V_INC), | |
199 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
200 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
201 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
202 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
3487 | 203 #ifdef RADEON |
3348 | 204 DECLARE_VREG(OV0_BASE_ADDR), |
3487 | 205 #endif |
3348 | 206 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), |
207 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
208 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
209 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
210 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
211 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
212 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
213 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
214 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
215 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
216 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
217 DECLARE_VREG(OV0_H_INC), | |
218 DECLARE_VREG(OV0_STEP_BY), | |
219 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
220 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
221 DECLARE_VREG(OV0_P1_X_START_END), | |
222 DECLARE_VREG(OV0_P2_X_START_END), | |
223 DECLARE_VREG(OV0_P3_X_START_END), | |
224 DECLARE_VREG(OV0_FILTER_CNTL), | |
225 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
226 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
227 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
228 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
229 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
230 DECLARE_VREG(OV0_FLAG_CNTL), | |
3470 | 231 #ifdef RAGE128 |
3348 | 232 DECLARE_VREG(OV0_COLOUR_CNTL), |
3470 | 233 #else |
234 DECLARE_VREG(OV0_SLICE_CNTL), | |
235 #endif | |
3348 | 236 DECLARE_VREG(OV0_VID_KEY_CLR), |
237 DECLARE_VREG(OV0_VID_KEY_MSK), | |
238 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
239 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
240 DECLARE_VREG(OV0_KEY_CNTL), | |
241 DECLARE_VREG(OV0_TEST), | |
242 DECLARE_VREG(OV0_LIN_TRANS_A), | |
243 DECLARE_VREG(OV0_LIN_TRANS_B), | |
244 DECLARE_VREG(OV0_LIN_TRANS_C), | |
245 DECLARE_VREG(OV0_LIN_TRANS_D), | |
246 DECLARE_VREG(OV0_LIN_TRANS_E), | |
247 DECLARE_VREG(OV0_LIN_TRANS_F), | |
248 DECLARE_VREG(OV0_GAMMA_0_F), | |
249 DECLARE_VREG(OV0_GAMMA_10_1F), | |
250 DECLARE_VREG(OV0_GAMMA_20_3F), | |
251 DECLARE_VREG(OV0_GAMMA_40_7F), | |
252 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
3473 | 253 DECLARE_VREG(OV0_GAMMA_3C0_3FF), |
254 DECLARE_VREG(SUBPIC_CNTL), | |
255 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
256 DECLARE_VREG(SUBPIC_Y_X_START), | |
257 DECLARE_VREG(SUBPIC_Y_X_END), | |
258 DECLARE_VREG(SUBPIC_V_INC), | |
259 DECLARE_VREG(SUBPIC_H_INC), | |
260 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
261 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
262 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
263 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
264 DECLARE_VREG(SUBPIC_PITCH), | |
265 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
266 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
267 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
268 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
269 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
270 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
271 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
272 DECLARE_VREG(IDCT_RUNS), | |
273 DECLARE_VREG(IDCT_LEVELS), | |
274 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
275 DECLARE_VREG(IDCT_AUTH), | |
276 DECLARE_VREG(IDCT_CONTROL) | |
2870 | 277 }; |
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278 #endif |
2870 | 279 static uint32_t radeon_vid_in_use = 0; |
280 | |
281 static uint8_t *radeon_mmio_base = 0; | |
282 static uint32_t radeon_mem_base = 0; | |
3019 | 283 static int32_t radeon_overlay_off = 0; |
2870 | 284 static uint32_t radeon_ram_size = 0; |
3263 | 285 #define PARAM_BUFF_SIZE 4096 |
286 static uint8_t *radeon_param_buff = NULL; | |
287 static uint32_t radeon_param_buff_size=0; | |
288 static uint32_t radeon_param_buff_len=0; /* real length of buffer */ | |
2870 | 289 static mga_vid_config_t radeon_config; |
290 | |
3122 | 291 static char *fourcc_format_name(int format) |
292 { | |
293 switch(format) | |
294 { | |
295 case IMGFMT_RGB8: return("RGB 8-bit"); | |
296 case IMGFMT_RGB15: return("RGB 15-bit"); | |
297 case IMGFMT_RGB16: return("RGB 16-bit"); | |
298 case IMGFMT_RGB24: return("RGB 24-bit"); | |
299 case IMGFMT_RGB32: return("RGB 32-bit"); | |
300 case IMGFMT_BGR8: return("BGR 8-bit"); | |
301 case IMGFMT_BGR15: return("BGR 15-bit"); | |
302 case IMGFMT_BGR16: return("BGR 16-bit"); | |
303 case IMGFMT_BGR24: return("BGR 24-bit"); | |
304 case IMGFMT_BGR32: return("BGR 32-bit"); | |
305 case IMGFMT_YVU9: return("Planar YVU9"); | |
306 case IMGFMT_IF09: return("Planar IF09"); | |
307 case IMGFMT_YV12: return("Planar YV12"); | |
308 case IMGFMT_I420: return("Planar I420"); | |
309 case IMGFMT_IYUV: return("Planar IYUV"); | |
310 case IMGFMT_CLPL: return("Planar CLPL"); | |
3198 | 311 case IMGFMT_Y800: return("Planar Y800"); |
312 case IMGFMT_Y8: return("Planar Y8"); | |
313 case IMGFMT_IUYV: return("Packed IUYV"); | |
314 case IMGFMT_IY41: return("Packed IY41"); | |
3122 | 315 case IMGFMT_IYU1: return("Packed IYU1"); |
316 case IMGFMT_IYU2: return("Packed IYU2"); | |
317 case IMGFMT_UYVY: return("Packed UYVY"); | |
318 case IMGFMT_UYNV: return("Packed UYNV"); | |
319 case IMGFMT_cyuv: return("Packed CYUV"); | |
3198 | 320 case IMGFMT_Y422: return("Packed Y422"); |
3122 | 321 case IMGFMT_YUY2: return("Packed YUY2"); |
322 case IMGFMT_YUNV: return("Packed YUNV"); | |
323 case IMGFMT_YVYU: return("Packed YVYU"); | |
324 case IMGFMT_Y41P: return("Packed Y41P"); | |
325 case IMGFMT_Y211: return("Packed Y211"); | |
326 case IMGFMT_Y41T: return("Packed Y41T"); | |
327 case IMGFMT_Y42T: return("Packed Y42T"); | |
328 case IMGFMT_V422: return("Packed V422"); | |
329 case IMGFMT_V655: return("Packed V655"); | |
330 case IMGFMT_CLJR: return("Packed CLJR"); | |
331 case IMGFMT_YUVP: return("Packed YUVP"); | |
332 case IMGFMT_UYVP: return("Packed UYVP"); | |
3198 | 333 case IMGFMT_MPEGPES: return("Mpeg PES"); |
3122 | 334 } |
335 return("Unknown"); | |
336 } | |
337 | |
2870 | 338 |
339 /* | |
340 * IO macros | |
341 */ | |
342 | |
343 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
344 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
345 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
346 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
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347 #define OUTREGP(addr,val,mask) \ |
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348 do { \ |
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349 unsigned int _tmp = INREG(addr); \ |
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350 _tmp &= (mask); \ |
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351 _tmp |= (val); \ |
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352 OUTREG(addr, _tmp); \ |
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353 } while (0) |
2870 | 354 |
3278 | 355 static uint32_t radeon_vid_get_dbpp( void ) |
356 { | |
357 uint32_t dbpp,retval; | |
358 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
359 switch(dbpp) | |
360 { | |
361 case DST_8BPP: retval = 8; break; | |
362 case DST_15BPP: retval = 15; break; | |
363 case DST_16BPP: retval = 16; break; | |
364 case DST_24BPP: retval = 24; break; | |
365 default: retval=32; break; | |
366 } | |
367 return retval; | |
368 } | |
369 | |
3369 | 370 static int radeon_is_dbl_scan( void ) |
371 { | |
372 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
373 } | |
374 | |
3380 | 375 static int radeon_is_interlace( void ) |
376 { | |
377 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
378 } | |
3369 | 379 |
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380 static __inline__ void radeon_engine_flush ( void ) |
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381 { |
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382 int i; |
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383 |
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384 /* initiate flush */ |
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385 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, |
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386 ~RB2D_DC_FLUSH_ALL); |
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387 |
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388 for (i=0; i < 2000000; i++) { |
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389 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) |
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390 break; |
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391 } |
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392 } |
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393 |
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394 |
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395 static __inline__ void _radeon_fifo_wait (int entries) |
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396 { |
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397 int i; |
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398 |
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399 for (i=0; i<2000000; i++) |
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400 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) |
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401 return; |
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402 } |
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403 |
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404 |
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405 static __inline__ void _radeon_engine_idle ( void ) |
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406 { |
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407 int i; |
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408 |
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409 /* ensure FIFO is empty before waiting for idle */ |
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410 _radeon_fifo_wait (64); |
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411 |
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412 for (i=0; i<2000000; i++) { |
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413 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { |
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414 radeon_engine_flush (); |
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415 return; |
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416 } |
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417 } |
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418 } |
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419 |
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420 #define radeon_engine_idle() _radeon_engine_idle() |
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421 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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422 |
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423 #if 0 |
3265 | 424 static void __init radeon_vid_save_state( void ) |
2870 | 425 { |
426 size_t i; | |
427 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
428 vregs[i].value = INREG(vregs[i].name); | |
429 } | |
430 | |
3265 | 431 static void __exit radeon_vid_restore_state( void ) |
2870 | 432 { |
433 size_t i; | |
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434 radeon_fifo_wait(2); |
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435 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
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436 radeon_engine_idle(); |
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437 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
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438 radeon_fifo_wait(15); |
2870 | 439 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
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440 { |
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441 radeon_fifo_wait(1); |
2870 | 442 OUTREG(vregs[i].name,vregs[i].value); |
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443 } |
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444 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 445 } |
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446 #endif |
3305 | 447 #ifdef DEBUG |
448 static void radeon_vid_dump_regs( void ) | |
449 { | |
450 size_t i; | |
451 printk(RVID_MSG"*** Begin of OV0 registers dump ***\n"); | |
452 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
453 printk(RVID_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
454 printk(RVID_MSG"*** End of OV0 registers dump ***\n"); | |
455 } | |
456 #endif | |
457 | |
2870 | 458 static void radeon_vid_stop_video( void ) |
459 { | |
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460 radeon_engine_idle(); |
2870 | 461 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); |
462 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
463 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
3487 | 464 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); |
2870 | 465 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
466 OUTREG(OV0_TEST, 0); | |
467 } | |
468 | |
469 static void radeon_vid_display_video( void ) | |
470 { | |
471 int bes_flags; | |
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472 radeon_fifo_wait(2); |
2870 | 473 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
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474 radeon_engine_idle(); |
2870 | 475 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
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476 radeon_fifo_wait(15); |
2870 | 477 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
3348 | 478 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); |
479 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2870 | 480 |
3250 | 481 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3470 | 482 #ifdef RAGE128 |
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483 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
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484 (besr.saturation << 8) | |
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485 (besr.saturation << 16)); |
3470 | 486 #endif |
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487 radeon_fifo_wait(2); |
3278 | 488 if(besr.ckey_on) |
489 { | |
490 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
491 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
3347 | 492 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); |
3278 | 493 } |
3366 | 494 else |
495 { | |
496 OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); | |
497 OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); | |
498 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
499 } | |
500 | |
2870 | 501 OUTREG(OV0_H_INC, besr.h_inc); |
502 OUTREG(OV0_STEP_BY, besr.step_by); | |
503 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
504 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
505 OUTREG(OV0_V_INC, besr.v_inc); | |
506 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
3164 | 507 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
2870 | 508 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
2944 | 509 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 510 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
511 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
512 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
3487 | 513 #ifdef RADEON |
3122 | 514 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
515 #endif | |
2870 | 516 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
517 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
518 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
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519 radeon_fifo_wait(9); |
2870 | 520 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); |
521 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
522 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
523 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
524 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
525 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
3164 | 526 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
2870 | 527 |
528 bes_flags = SCALER_ENABLE | | |
529 SCALER_SMART_SWITCH | | |
3334 | 530 #ifdef RADEON |
3305 | 531 SCALER_HORZ_PICK_NEAREST; |
3334 | 532 #else |
533 SCALER_Y2R_TEMP | | |
534 SCALER_PIX_EXPAND; | |
535 #endif | |
3250 | 536 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; |
537 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
3198 | 538 #ifdef RAGE128 |
539 bes_flags |= SCALER_BURST_PER_PLANE; | |
540 #endif | |
2870 | 541 switch(besr.fourcc) |
542 { | |
543 case IMGFMT_RGB15: | |
544 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
545 case IMGFMT_RGB16: | |
546 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
547 case IMGFMT_RGB24: | |
548 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
549 case IMGFMT_RGB32: | |
550 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
3164 | 551 /* 4:1:0*/ |
552 case IMGFMT_IF09: | |
2870 | 553 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
3164 | 554 /* 4:2:0 */ |
3122 | 555 case IMGFMT_IYUV: |
2870 | 556 case IMGFMT_I420: |
3305 | 557 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; |
558 break; | |
3164 | 559 /* 4:2:2 */ |
560 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
2870 | 561 case IMGFMT_YUY2: |
562 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
563 } | |
564 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
565 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
3305 | 566 #ifdef DEBUG |
567 radeon_vid_dump_regs(); | |
568 #endif | |
2870 | 569 } |
570 | |
3278 | 571 void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B) |
572 { | |
573 besr.ckey_on = ckey_on; | |
3347 | 574 besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1; |
3278 | 575 besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24); |
576 } | |
577 | |
578 | |
2951 | 579 #define XXX_SRC_X 0 |
580 #define XXX_SRC_Y 0 | |
2870 | 581 |
582 static int radeon_vid_init_video( mga_vid_config_t *config ) | |
583 { | |
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584 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 585 int is_420; |
3164 | 586 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 587 ,(uint32_t)config->version |
2951 | 588 ,(uint32_t)config->format |
2870 | 589 ,(uint32_t)config->card_type |
590 ,(uint32_t)config->ram_size | |
591 ,(uint32_t)config->src_width | |
592 ,(uint32_t)config->src_height | |
593 ,(uint32_t)config->x_org | |
594 ,(uint32_t)config->y_org | |
595 ,(uint32_t)config->dest_width | |
596 ,(uint32_t)config->dest_height | |
597 ,(uint32_t)config->frame_size | |
598 ,(uint32_t)config->num_frames); | |
2917 | 599 radeon_vid_stop_video(); |
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600 left = XXX_SRC_X << 16; |
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601 top = XXX_SRC_Y << 16; |
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602 src_h = config->src_height; |
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603 src_w = config->src_width; |
2870 | 604 switch(config->format) |
605 { | |
606 case IMGFMT_RGB15: | |
607 case IMGFMT_BGR15: | |
608 case IMGFMT_RGB16: | |
609 case IMGFMT_BGR16: | |
610 case IMGFMT_RGB24: | |
611 case IMGFMT_BGR24: | |
612 case IMGFMT_RGB32: | |
613 case IMGFMT_BGR32: | |
3164 | 614 /* 4:1:0 */ |
615 case IMGFMT_IF09: | |
2870 | 616 case IMGFMT_YVU9: |
3164 | 617 /* 4:2:0 */ |
2870 | 618 case IMGFMT_IYUV: |
619 case IMGFMT_YV12: | |
620 case IMGFMT_I420: | |
3164 | 621 /* 4:2:2 */ |
622 case IMGFMT_UYVY: | |
2870 | 623 case IMGFMT_YUY2: |
624 break; | |
625 default: | |
3164 | 626 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
2870 | 627 return -1; |
628 } | |
3019 | 629 is_420 = 0; |
3122 | 630 if(config->format == IMGFMT_YV12 || |
631 config->format == IMGFMT_I420 || | |
632 config->format == IMGFMT_IYUV) is_420 = 1; | |
2951 | 633 switch(config->format) |
634 { | |
3164 | 635 /* 4:1:0 */ |
2951 | 636 case IMGFMT_YVU9: |
3164 | 637 case IMGFMT_IF09: |
638 /* 4:2:0 */ | |
2951 | 639 case IMGFMT_IYUV: |
3164 | 640 case IMGFMT_YV12: |
641 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
642 /* 4:2:2 */ | |
643 default: | |
2951 | 644 case IMGFMT_UYVY: |
645 case IMGFMT_YUY2: | |
646 case IMGFMT_RGB15: | |
647 case IMGFMT_BGR15: | |
648 case IMGFMT_RGB16: | |
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649 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 650 case IMGFMT_RGB24: |
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651 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 652 case IMGFMT_RGB32: |
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653 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 654 } |
3380 | 655 if(radeon_is_dbl_scan()) config->dest_height *= 2; |
656 else | |
657 if(radeon_is_interlace()) config->dest_height /= 2; | |
3278 | 658 besr.dest_bpp = radeon_vid_get_dbpp(); |
2870 | 659 besr.fourcc = config->format; |
3369 | 660 besr.v_inc = (src_h << 20) / config->dest_height; |
661 h_inc = (src_w << 12) / config->dest_width; | |
2944 | 662 step_by = 1; |
2870 | 663 |
2944 | 664 while(h_inc >= (2 << 12)) { |
665 step_by++; | |
666 h_inc >>= 1; | |
2870 | 667 } |
668 | |
669 /* keep everything in 16.16 */ | |
3164 | 670 besr.base_addr = radeon_mem_base; |
3019 | 671 if(is_420) |
672 { | |
3164 | 673 uint32_t d1line,d2line,d3line; |
674 d1line = top*pitch; | |
675 d2line = src_h*pitch+(d1line>>1); | |
676 d3line = d2line+((src_h*pitch)>>2); | |
677 d1line += (left >> 16) & ~15; | |
678 d2line += (left >> 17) & ~15; | |
679 d3line += (left >> 17) & ~15; | |
680 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
681 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
682 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
683 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
684 { | |
685 uint32_t tmp; | |
686 tmp = besr.vid_buf1_base_adrs; | |
687 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
688 besr.vid_buf2_base_adrs = tmp; | |
689 } | |
3019 | 690 } |
691 else | |
692 { | |
693 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
3198 | 694 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; |
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695 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 696 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
697 } | |
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698 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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699 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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700 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 701 |
2951 | 702 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 703 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 704 ((tmp << 12) & 0xf0000000); |
2870 | 705 |
2951 | 706 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 707 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 708 ((tmp << 12) & 0x70000000); |
709 tmp = (top & 0x0000ffff) + 0x00018000; | |
3122 | 710 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
711 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
3019 | 712 |
713 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
3122 | 714 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
715 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
3019 | 716 |
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717 leftUV = (left >> 17) & 15; |
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718 left = (left >> 16) & 15; |
2944 | 719 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
720 besr.step_by = step_by | (step_by << 8); | |
3164 | 721 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
722 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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723 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
3122 | 724 if(is_420) |
725 { | |
726 src_h = (src_h + 1) >> 1; | |
727 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
728 } | |
729 else besr.p23_blank_lines_at_top = 0; | |
2870 | 730 besr.vid_buf_pitch0_value = pitch; |
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731 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
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732 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
3164 | 733 src_w>>=1; |
734 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
735 besr.p3_x_start_end = besr.p2_x_start_end; | |
2870 | 736 return 0; |
737 } | |
738 | |
739 static void radeon_vid_frame_sel(int frame) | |
740 { | |
3066 | 741 uint32_t off0,off1,off2; |
3250 | 742 if(!besr.double_buff) return; |
3066 | 743 if(frame%2) |
744 { | |
745 off0 = besr.vid_buf3_base_adrs; | |
746 off1 = besr.vid_buf4_base_adrs; | |
747 off2 = besr.vid_buf5_base_adrs; | |
748 } | |
749 else | |
750 { | |
751 off0 = besr.vid_buf0_base_adrs; | |
752 off1 = besr.vid_buf1_base_adrs; | |
753 off2 = besr.vid_buf2_base_adrs; | |
754 } | |
2917 | 755 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
756 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 757 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
758 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
759 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 760 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 761 } |
762 | |
3250 | 763 static void radeon_vid_make_default(void) |
764 { | |
3470 | 765 #ifdef RAGE128 |
3366 | 766 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ |
3470 | 767 #endif |
3250 | 768 besr.deinterlace_pattern = 0x900AAAAA; |
769 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
770 besr.deinterlace_on=1; | |
771 besr.double_buff=1; | |
772 } | |
773 | |
774 | |
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775 static void radeon_vid_preset(void) |
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776 { |
3470 | 777 #ifdef RAGE128 |
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778 unsigned tmp; |
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779 tmp = INREG(OV0_COLOUR_CNTL); |
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780 besr.saturation = (tmp>>8)&0x1f; |
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781 besr.brightness = tmp & 0x7f; |
3470 | 782 #endif |
3250 | 783 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); |
784 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); | |
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785 } |
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786 |
2951 | 787 static int video_on = 0; |
788 | |
2870 | 789 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
790 { | |
791 int frame; | |
792 | |
793 switch(cmd) | |
794 { | |
795 case MGA_VID_CONFIG: | |
3305 | 796 RTRACE(RVID_MSG"radeon_mmio_base = %p\n",radeon_mmio_base); |
797 RTRACE(RVID_MSG"radeon_mem_base = %08x\n",radeon_mem_base); | |
3164 | 798 RTRACE(RVID_MSG"Received configuration\n"); |
2870 | 799 |
800 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
801 { | |
3164 | 802 printk(RVID_MSG"failed copy from userspace\n"); |
3019 | 803 return -EFAULT; |
2870 | 804 } |
805 if(radeon_config.version != MGA_VID_VERSION){ | |
3164 | 806 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
3019 | 807 return -EFAULT; |
2870 | 808 } |
809 | |
810 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
3164 | 811 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
3019 | 812 return -EFAULT; |
2870 | 813 } |
814 | |
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815 if(radeon_config.num_frames<1){ |
3164 | 816 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
3019 | 817 return -EFAULT; |
2870 | 818 } |
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819 if(radeon_config.num_frames==1) besr.double_buff=0; |
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820 if(!besr.double_buff) radeon_config.num_frames=1; |
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821 else radeon_config.num_frames=2; |
2870 | 822 radeon_config.card_type = 0; |
823 radeon_config.ram_size = radeon_ram_size; | |
3019 | 824 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
825 radeon_overlay_off &= 0xffff0000; | |
826 if(radeon_overlay_off < 0){ | |
3164 | 827 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
3019 | 828 return -EFAULT; |
829 } | |
3305 | 830 RTRACE(RVID_MSG"using video overlay at offset %08X\n",radeon_overlay_off); |
2870 | 831 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
832 { | |
3164 | 833 printk(RVID_MSG"failed copy to userspace\n"); |
3019 | 834 return -EFAULT; |
2870 | 835 } |
3278 | 836 radeon_vid_set_color_key(radeon_config.colkey_on, |
837 radeon_config.colkey_red, | |
838 radeon_config.colkey_green, | |
839 radeon_config.colkey_blue); | |
3265 | 840 if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); |
3164 | 841 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
2870 | 842 return radeon_vid_init_video(&radeon_config); |
843 break; | |
844 | |
845 case MGA_VID_ON: | |
3164 | 846 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
847 radeon_vid_display_video(); | |
2951 | 848 video_on = 1; |
2870 | 849 break; |
850 | |
851 case MGA_VID_OFF: | |
3164 | 852 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
2951 | 853 if(video_on) radeon_vid_stop_video(); |
854 video_on = 0; | |
2870 | 855 break; |
856 | |
857 case MGA_VID_FSEL: | |
858 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
859 { | |
3164 | 860 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
2870 | 861 return(-EFAULT); |
862 } | |
863 radeon_vid_frame_sel(frame); | |
864 break; | |
865 | |
866 default: | |
3164 | 867 printk(RVID_MSG"Invalid ioctl\n"); |
2870 | 868 return (-EINVAL); |
869 } | |
870 | |
871 return 0; | |
872 } | |
873 | |
874 struct ati_card_id_s | |
875 { | |
3164 | 876 const int id; |
877 const char name[17]; | |
878 }; | |
879 | |
880 const struct ati_card_id_s ati_card_ids[]= | |
2870 | 881 { |
3164 | 882 #ifdef RAGE128 |
883 /* | |
884 This driver should be compatible with Rage128 (pro) chips. | |
885 (include adaptive deinterlacing!!!). | |
886 Moreover: the same logic can be used with Mach64 chips. | |
887 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
888 but they are incompatible by i/o ports. So if enthusiasts will want | |
889 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
890 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
891 fourccs (422 and 420 formats only). | |
892 */ | |
893 /* Rage128 Pro GL */ | |
894 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
895 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
896 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
897 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
898 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
899 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
900 /* Rage128 Pro VR */ | |
901 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
902 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
903 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
904 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
905 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
906 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
907 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
908 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
909 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
910 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
911 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
912 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
913 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
914 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
915 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
916 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
917 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
918 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
919 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
920 /* Rage128 GL */ | |
921 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
922 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
923 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
924 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
925 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
926 /* Rage128 VR */ | |
927 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
928 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
929 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
930 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
931 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
932 /* Rage128 M3 */ | |
3198 | 933 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, |
934 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
3164 | 935 /* Rage128 Pro Ultra */ |
3198 | 936 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, |
937 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
938 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
3164 | 939 #else |
940 /* Radeons (indeed: Rage 256 Pro ;) */ | |
2870 | 941 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
942 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
943 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
944 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
945 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
946 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
947 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
948 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
949 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
950 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
951 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
3164 | 952 #endif |
2870 | 953 }; |
954 | |
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955 static int detected_chip; |
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956 |
3265 | 957 static int __init radeon_vid_config_card(void) |
2870 | 958 { |
959 struct pci_dev *dev = NULL; | |
960 size_t i; | |
961 | |
962 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
963 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
964 break; | |
3122 | 965 if(!dev) |
2870 | 966 { |
3164 | 967 printk(RVID_MSG"No supported cards found\n"); |
2870 | 968 return FALSE; |
969 } | |
970 | |
971 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
972 radeon_mem_base = dev->resource[0].start; | |
973 | |
3164 | 974 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
975 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
2870 | 976 |
3122 | 977 /* video memory size */ |
978 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
979 | |
3164 | 980 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
3122 | 981 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
982 radeon_ram_size /= 0x100000; | |
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983 detected_chip = i; |
3164 | 984 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
2870 | 985 |
986 return TRUE; | |
987 } | |
988 | |
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989 #define PARAM_BRIGHTNESS "brightness=" |
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990 #define PARAM_SATURATION "saturation=" |
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991 #define PARAM_DOUBLE_BUFF "double_buff=" |
3250 | 992 #define PARAM_DEINTERLACE "deinterlace=" |
993 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" | |
2870 | 994 |
3263 | 995 static void radeon_param_buff_fill( void ) |
2870 | 996 { |
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997 unsigned len,saturation; |
3366 | 998 int8_t brightness; |
999 brightness = besr.brightness & 0x7f; | |
1000 /* FIXME: It's probably x86 specific convertion. But it doesn't matter | |
1001 for general logic - only for printing value */ | |
1002 if(brightness > 63) brightness = (((~besr.brightness) & 0x3f)+1) * (-1); | |
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1003 saturation = besr.saturation; |
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1004 len = 0; |
3263 | 1005 len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); |
1006 len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); | |
3334 | 1007 len += sprintf(&radeon_param_buff[len],"Memory: %x:%x\n",radeon_mem_base,radeon_ram_size*0x100000); |
3263 | 1008 len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); |
3334 | 1009 len += sprintf(&radeon_param_buff[len],"Overlay offset: %x\n",radeon_overlay_off); |
3269 | 1010 #ifdef CONFIG_MTRR |
3265 | 1011 len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); |
3269 | 1012 #endif |
3278 | 1013 if(besr.ckey_on) len += sprintf(&radeon_param_buff[len],"Last used color_key=%X (mask=%X)\n",besr.graphics_key_clr,besr.graphics_key_msk); |
3265 | 1014 len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); |
3278 | 1015 len += sprintf(&radeon_param_buff[len],"Last BPP: %u\n",besr.dest_bpp); |
3263 | 1016 len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); |
1017 len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); | |
1018 len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); | |
1019 len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); | |
3470 | 1020 #ifdef RAGE128 |
3366 | 1021 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",(int)brightness); |
3263 | 1022 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); |
3470 | 1023 #endif |
3263 | 1024 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); |
1025 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); | |
1026 radeon_param_buff_len = len; | |
1027 } | |
1028 | |
1029 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
1030 { | |
1031 uint32_t size; | |
1032 if(!radeon_param_buff) return -ESPIPE; | |
1033 if(!(*ppos)) radeon_param_buff_fill(); | |
1034 if(*ppos >= radeon_param_buff_len) return 0; | |
1035 size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); | |
1036 memcpy(buf,radeon_param_buff,size); | |
1037 *ppos += size; | |
1038 return size; | |
2870 | 1039 } |
1040 | |
1041 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
1042 { | |
3470 | 1043 #ifdef RAGE128 |
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1044 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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1045 { |
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1046 long brightness; |
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1047 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
3368 | 1048 if(brightness >= -64 && brightness <= 63) |
1049 { | |
1050 besr.brightness = brightness; | |
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1051 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | |
3250 | 1052 (besr.saturation << 8) | |
1053 (besr.saturation << 16)); | |
3368 | 1054 } |
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1055 } |
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1056 else |
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1057 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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1058 { |
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1059 long saturation; |
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1060 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); |
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1061 if(saturation >= 0 && saturation <= 31) |
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1062 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
3250 | 1063 (saturation << 8) | |
1064 (saturation << 16)); | |
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1065 } |
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1066 else |
3470 | 1067 #endif |
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1068 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) |
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1069 { |
3250 | 1070 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; |
1071 else besr.double_buff = 0; | |
1072 } | |
1073 else | |
1074 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) | |
1075 { | |
1076 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; | |
1077 else besr.deinterlace_on = 0; | |
1078 } | |
1079 else | |
1080 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) | |
1081 { | |
1082 long dpat; | |
1083 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); | |
1084 OUTREG(OV0_DEINTERLACE_PATTERN, dpat); | |
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1085 } |
3263 | 1086 else count = -EIO; |
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1087 radeon_vid_preset(); |
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1088 return count; |
2870 | 1089 } |
1090 | |
1091 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
1092 { | |
1093 | |
3164 | 1094 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
3019 | 1095 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 1096 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
1097 { | |
3164 | 1098 printk(RVID_MSG"error mapping video memory\n"); |
2870 | 1099 return(-EAGAIN); |
1100 } | |
1101 | |
1102 return(0); | |
1103 } | |
1104 | |
1105 static int radeon_vid_release(struct inode *inode, struct file *file) | |
1106 { | |
1107 radeon_vid_in_use = 0; | |
1108 radeon_vid_stop_video(); | |
1109 | |
1110 MOD_DEC_USE_COUNT; | |
1111 return 0; | |
1112 } | |
1113 | |
1114 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
1115 { | |
1116 return -ESPIPE; | |
1117 } | |
1118 | |
1119 static int radeon_vid_open(struct inode *inode, struct file *file) | |
1120 { | |
1121 int minor = MINOR(inode->i_rdev); | |
1122 | |
1123 if(minor != 0) | |
1124 return(-ENXIO); | |
1125 | |
1126 if(radeon_vid_in_use == 1) | |
1127 return(-EBUSY); | |
1128 | |
1129 radeon_vid_in_use = 1; | |
1130 MOD_INC_USE_COUNT; | |
1131 return(0); | |
1132 } | |
1133 | |
1134 #if LINUX_VERSION_CODE >= 0x020400 | |
1135 static struct file_operations radeon_vid_fops = | |
1136 { | |
1137 llseek: radeon_vid_lseek, | |
3366 | 1138 read: radeon_vid_read, |
2870 | 1139 write: radeon_vid_write, |
3366 | 1140 /* |
1141 readdir: | |
1142 poll: | |
1143 */ | |
2870 | 1144 ioctl: radeon_vid_ioctl, |
3366 | 1145 mmap: radeon_vid_mmap, |
1146 open: radeon_vid_open, | |
1147 /* | |
1148 flush: | |
1149 */ | |
2870 | 1150 release: radeon_vid_release |
3366 | 1151 /* |
1152 fsync: | |
1153 fasync: | |
1154 lock: | |
1155 readv: | |
1156 writev: | |
1157 sendpage: | |
1158 get_unmapped_area: | |
1159 */ | |
2870 | 1160 }; |
1161 #else | |
1162 static struct file_operations radeon_vid_fops = | |
1163 { | |
1164 radeon_vid_lseek, | |
1165 radeon_vid_read, | |
1166 radeon_vid_write, | |
1167 NULL, | |
1168 NULL, | |
1169 radeon_vid_ioctl, | |
1170 radeon_vid_mmap, | |
1171 radeon_vid_open, | |
1172 NULL, | |
1173 radeon_vid_release | |
1174 }; | |
1175 #endif | |
1176 | |
1177 /* | |
1178 * Main Initialization Function | |
1179 */ | |
1180 | |
3265 | 1181 static int __init radeon_vid_initialize(void) |
2870 | 1182 { |
1183 radeon_vid_in_use = 0; | |
3164 | 1184 #ifdef RAGE128 |
1185 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
1186 #else | |
1187 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
1188 #endif | |
2870 | 1189 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
1190 { | |
3164 | 1191 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
2870 | 1192 return -EIO; |
1193 } | |
1194 | |
1195 if (!radeon_vid_config_card()) | |
1196 { | |
3164 | 1197 printk(RVID_MSG"can't configure this card\n"); |
2870 | 1198 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
1199 return -EINVAL; | |
1200 } | |
3263 | 1201 radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); |
1202 if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; | |
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1203 #if 0 |
2870 | 1204 radeon_vid_save_state(); |
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1205 #endif |
3250 | 1206 radeon_vid_make_default(); |
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1207 radeon_vid_preset(); |
3265 | 1208 #ifdef CONFIG_MTRR |
1209 if (mtrr) { | |
1210 smtrr.vram = mtrr_add(radeon_mem_base, | |
1211 radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); | |
1212 smtrr.vram_valid = 1; | |
1213 /* let there be speed */ | |
1214 printk(RVID_MSG"MTRR set to ON\n"); | |
1215 } | |
1216 #endif /* CONFIG_MTRR */ | |
2870 | 1217 return(0); |
1218 } | |
1219 | |
3265 | 1220 int __init init_module(void) |
2870 | 1221 { |
1222 return radeon_vid_initialize(); | |
1223 } | |
1224 | |
3265 | 1225 void __exit cleanup_module(void) |
2870 | 1226 { |
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1227 #if 0 |
2870 | 1228 radeon_vid_restore_state(); |
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1229 #endif |
2870 | 1230 if(radeon_mmio_base) |
1231 iounmap(radeon_mmio_base); | |
3263 | 1232 kfree(radeon_param_buff); |
3164 | 1233 RTRACE(RVID_MSG"Cleaning up module\n"); |
2870 | 1234 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
3265 | 1235 #ifdef CONFIG_MTRR |
1236 if (smtrr.vram_valid) | |
1237 mtrr_del(smtrr.vram, radeon_mem_base, | |
1238 radeon_ram_size*0x100000); | |
1239 #endif /* CONFIG_MTRR */ | |
2870 | 1240 } |
1241 |