Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 5929:9e7d54e7be58
- frame_time delayed one frame, as it's really duration of current frame,
as suggested by Atmosfear some time ago, when talking about -mf...
- limiting usleep time, to avoid sound skips and ensure responsiveness,
inspired by asf patch from Albeu. it solves problem with very low fps .wmv files
| author | arpi |
|---|---|
| date | Thu, 02 May 2002 02:03:59 +0000 (2002-05-02) |
| parents | af4dcf6751dc |
| children | cc66affa965a |
| rev | line source |
|---|---|
| 2870 | 1 /* |
| 2 * | |
| 3 * radeon_vid.c | |
| 4 * | |
| 5 * Copyright (C) 2001 Nick Kurshev | |
| 6 * | |
| 3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
| 2870 | 8 * |
| 9 * This software has been released under the terms of the GNU Public | |
| 10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
| 11 * | |
| 12 * This file is partly based on mga_vid and sis_vid stuff from | |
| 13 * mplayer's package. | |
| 2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
| 3366 | 15 * |
| 16 * SPECIAL THANKS TO: Hans-Peter Raschke for active testing and hacking | |
| 17 * Rage128(pro) stuff of this driver. | |
| 2870 | 18 */ |
| 19 | |
| 3940 | 20 #define RADEON_VID_VERSION "1.2.1" |
| 2951 | 21 |
| 2870 | 22 /* |
| 23 It's entirely possible this major conflicts with something else | |
| 24 mknod /dev/radeon_vid c 178 0 | |
| 3164 | 25 or |
| 26 mknod /dev/rage128_vid c 178 0 | |
| 3380 | 27 for Rage128/Rage128Pro chips (although it doesn't matter) |
| 3164 | 28 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| 29 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
| 30 ----------------------------------------------------------- | |
| 2870 | 31 TODO: |
| 3164 | 32 Highest priority: fbvid.h compatibility |
| 3366 | 33 High priority: Fixing BUGS |
| 34 Middle priority: RGB/BGR 2-32, YVU9, IF09 support | |
| 35 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV, YUNV, YVYU, Y41P, Y211, Y41T, | |
| 36 ^^^^ | |
| 37 Y42T, V422, V655, CLJR, YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
| 38 ........................................................... | |
| 39 BUGS and LACKS: | |
| 40 Color and video keys don't work | |
| 2870 | 41 */ |
| 42 | |
| 43 #include <linux/config.h> | |
| 44 #include <linux/version.h> | |
| 45 #include <linux/module.h> | |
| 46 #include <linux/types.h> | |
| 47 #include <linux/kernel.h> | |
| 48 #include <linux/sched.h> | |
| 49 #include <linux/mm.h> | |
| 50 #include <linux/string.h> | |
| 51 #include <linux/errno.h> | |
| 52 #include <linux/slab.h> | |
| 53 #include <linux/pci.h> | |
| 54 #include <linux/ioport.h> | |
| 55 #include <linux/init.h> | |
| 3265 | 56 #include <linux/byteorder/swab.h> |
| 2870 | 57 |
| 58 #include "radeon_vid.h" | |
| 59 #include "radeon.h" | |
| 60 | |
| 61 #ifdef CONFIG_MTRR | |
| 62 #include <asm/mtrr.h> | |
| 63 #endif | |
| 64 | |
| 65 #include <asm/uaccess.h> | |
| 66 #include <asm/system.h> | |
| 67 #include <asm/io.h> | |
| 68 | |
| 69 #define TRUE 1 | |
| 70 #define FALSE 0 | |
| 71 | |
| 72 #define RADEON_VID_MAJOR 178 | |
| 73 | |
| 74 | |
| 75 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
| 3198 | 76 #ifdef RAGE128 |
| 77 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
| 78 #else | |
| 79 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
| 80 #endif | |
| 2965 | 81 #ifdef MODULE_LICENSE |
| 2870 | 82 MODULE_LICENSE("GPL"); |
| 2965 | 83 #endif |
| 3265 | 84 #ifdef CONFIG_MTRR |
| 85 MODULE_PARM(mtrr, "i"); | |
| 86 MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); | |
| 87 static int mtrr __initdata = 1; | |
| 88 static struct { int vram; int vram_valid; } smtrr; | |
| 89 #endif | |
| 90 MODULE_PARM(swap_fourcc, "i"); | |
| 91 MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (dont't swap=0(default))"); | |
| 92 static int swap_fourcc __initdata = 0; | |
| 2870 | 93 |
| 3164 | 94 #ifdef RAGE128 |
| 95 #define RVID_MSG "rage128_vid: " | |
| 96 #define X_ADJUST 0 | |
| 97 #else | |
| 98 #define RVID_MSG "radeon_vid: " | |
| 99 #define X_ADJUST 8 | |
| 3198 | 100 #ifndef RADEON |
| 101 #define RADEON | |
| 102 #endif | |
| 3164 | 103 #endif |
| 104 | |
| 3348 | 105 #undef DEBUG |
| 106 #if DEBUG | |
| 107 #define RTRACE printk | |
| 108 #else | |
| 109 #define RTRACE(...) ((void)0) | |
| 110 #endif | |
| 111 | |
| 3940 | 112 #ifndef RAGE128 |
| 113 #if defined(__i386__) | |
| 114 /* Ugly but only way */ | |
| 115 #undef AVOID_FPU | |
| 116 static double inline __FastSin(double x) | |
| 117 { | |
| 118 register double res; | |
| 119 __asm __volatile("fsin":"=t"(res):"0"(x)); | |
| 120 return res; | |
| 121 } | |
| 122 #undef sin | |
| 123 #define sin(x) __FastSin(x) | |
| 124 | |
| 125 static double inline __FastCos(double x) | |
| 126 { | |
| 127 register double res; | |
| 128 __asm __volatile("fcos":"=t"(res):"0"(x)); | |
| 129 return res; | |
| 130 } | |
| 131 #undef cos | |
| 132 #define cos(x) __FastCos(x) | |
| 133 #else | |
| 3944 | 134 #include "generic_math.h" |
| 3940 | 135 #endif /*__386__*/ |
| 136 #endif /*RAGE128*/ | |
| 137 | |
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138 #if !defined( RAGE128 ) && !defined( AVOID_FPU ) |
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139 #define RADEON_FPU 1 |
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140 #endif |
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141 |
| 2870 | 142 typedef struct bes_registers_s |
| 143 { | |
| 144 /* base address of yuv framebuffer */ | |
| 145 uint32_t yuv_base; | |
| 146 uint32_t fourcc; | |
| 3278 | 147 uint32_t dest_bpp; |
| 2870 | 148 /* YUV BES registers */ |
| 149 uint32_t reg_load_cntl; | |
| 150 uint32_t h_inc; | |
| 151 uint32_t step_by; | |
| 152 uint32_t y_x_start; | |
| 153 uint32_t y_x_end; | |
| 154 uint32_t v_inc; | |
| 155 uint32_t p1_blank_lines_at_top; | |
| 3019 | 156 uint32_t p23_blank_lines_at_top; |
| 2870 | 157 uint32_t vid_buf_pitch0_value; |
| 2944 | 158 uint32_t vid_buf_pitch1_value; |
| 2870 | 159 uint32_t p1_x_start_end; |
| 160 uint32_t p2_x_start_end; | |
| 161 uint32_t p3_x_start_end; | |
| 3122 | 162 uint32_t base_addr; |
| 2870 | 163 uint32_t vid_buf0_base_adrs; |
| 164 /* These ones are for auto flip: maybe in the future */ | |
| 165 uint32_t vid_buf1_base_adrs; | |
| 166 uint32_t vid_buf2_base_adrs; | |
| 167 uint32_t vid_buf3_base_adrs; | |
| 168 uint32_t vid_buf4_base_adrs; | |
| 169 uint32_t vid_buf5_base_adrs; | |
| 170 | |
| 171 uint32_t p1_v_accum_init; | |
| 172 uint32_t p1_h_accum_init; | |
| 3019 | 173 uint32_t p23_v_accum_init; |
| 2870 | 174 uint32_t p23_h_accum_init; |
| 175 uint32_t scale_cntl; | |
| 176 uint32_t exclusive_horz; | |
| 177 uint32_t auto_flip_cntl; | |
| 178 uint32_t filter_cntl; | |
| 3250 | 179 uint32_t key_cntl; |
| 180 uint32_t test; | |
| 181 /* Configurable stuff */ | |
| 182 int double_buff; | |
| 3278 | 183 |
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184 int brightness; |
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185 int saturation; |
| 3278 | 186 |
| 187 int ckey_on; | |
| 2870 | 188 uint32_t graphics_key_clr; |
| 3278 | 189 uint32_t graphics_key_msk; |
| 190 | |
| 3250 | 191 int deinterlace_on; |
| 192 uint32_t deinterlace_pattern; | |
| 3278 | 193 |
| 2870 | 194 } bes_registers_t; |
| 195 | |
| 196 typedef struct video_registers_s | |
| 197 { | |
| 3348 | 198 #ifdef DEBUG |
| 3305 | 199 const char * sname; |
| 3348 | 200 #endif |
| 2870 | 201 uint32_t name; |
| 202 uint32_t value; | |
| 203 }video_registers_t; | |
| 204 | |
| 205 static bes_registers_t besr; | |
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206 #ifndef RAGE128 |
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207 static int IsR200=0; |
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208 #endif |
| 3348 | 209 #ifdef DEBUG |
| 210 #define DECLARE_VREG(name) { #name, name, 0 } | |
| 211 #else | |
| 212 #define DECLARE_VREG(name) { name, 0 } | |
| 213 #endif | |
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214 #ifdef DEBUG |
| 2870 | 215 static video_registers_t vregs[] = |
| 216 { | |
| 3473 | 217 DECLARE_VREG(VIDEOMUX_CNTL), |
| 218 DECLARE_VREG(VIPPAD_MASK), | |
| 219 DECLARE_VREG(VIPPAD1_A), | |
| 220 DECLARE_VREG(VIPPAD1_EN), | |
| 221 DECLARE_VREG(VIPPAD1_Y), | |
| 3348 | 222 DECLARE_VREG(OV0_Y_X_START), |
| 223 DECLARE_VREG(OV0_Y_X_END), | |
| 224 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
| 225 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
| 226 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
| 227 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
| 228 DECLARE_VREG(OV0_SCALE_CNTL), | |
| 229 DECLARE_VREG(OV0_V_INC), | |
| 230 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
| 231 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
| 232 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
| 233 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
| 3487 | 234 #ifdef RADEON |
| 3348 | 235 DECLARE_VREG(OV0_BASE_ADDR), |
| 3487 | 236 #endif |
| 3348 | 237 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), |
| 238 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
| 239 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
| 240 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
| 241 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
| 242 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
| 243 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
| 244 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
| 245 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
| 246 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
| 247 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
| 248 DECLARE_VREG(OV0_H_INC), | |
| 249 DECLARE_VREG(OV0_STEP_BY), | |
| 250 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
| 251 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
| 252 DECLARE_VREG(OV0_P1_X_START_END), | |
| 253 DECLARE_VREG(OV0_P2_X_START_END), | |
| 254 DECLARE_VREG(OV0_P3_X_START_END), | |
| 255 DECLARE_VREG(OV0_FILTER_CNTL), | |
| 256 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
| 257 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
| 258 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
| 259 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
| 260 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
| 261 DECLARE_VREG(OV0_FLAG_CNTL), | |
| 3470 | 262 #ifdef RAGE128 |
| 3348 | 263 DECLARE_VREG(OV0_COLOUR_CNTL), |
| 3470 | 264 #else |
| 265 DECLARE_VREG(OV0_SLICE_CNTL), | |
| 266 #endif | |
| 3348 | 267 DECLARE_VREG(OV0_VID_KEY_CLR), |
| 268 DECLARE_VREG(OV0_VID_KEY_MSK), | |
| 269 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
| 270 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
| 271 DECLARE_VREG(OV0_KEY_CNTL), | |
| 272 DECLARE_VREG(OV0_TEST), | |
| 273 DECLARE_VREG(OV0_LIN_TRANS_A), | |
| 274 DECLARE_VREG(OV0_LIN_TRANS_B), | |
| 275 DECLARE_VREG(OV0_LIN_TRANS_C), | |
| 276 DECLARE_VREG(OV0_LIN_TRANS_D), | |
| 277 DECLARE_VREG(OV0_LIN_TRANS_E), | |
| 278 DECLARE_VREG(OV0_LIN_TRANS_F), | |
| 279 DECLARE_VREG(OV0_GAMMA_0_F), | |
| 280 DECLARE_VREG(OV0_GAMMA_10_1F), | |
| 281 DECLARE_VREG(OV0_GAMMA_20_3F), | |
| 282 DECLARE_VREG(OV0_GAMMA_40_7F), | |
| 283 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
| 3473 | 284 DECLARE_VREG(OV0_GAMMA_3C0_3FF), |
| 285 DECLARE_VREG(SUBPIC_CNTL), | |
| 286 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
| 287 DECLARE_VREG(SUBPIC_Y_X_START), | |
| 288 DECLARE_VREG(SUBPIC_Y_X_END), | |
| 289 DECLARE_VREG(SUBPIC_V_INC), | |
| 290 DECLARE_VREG(SUBPIC_H_INC), | |
| 291 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
| 292 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
| 293 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
| 294 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
| 295 DECLARE_VREG(SUBPIC_PITCH), | |
| 296 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
| 297 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
| 298 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
| 299 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
| 300 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
| 301 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
| 302 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
| 303 DECLARE_VREG(IDCT_RUNS), | |
| 304 DECLARE_VREG(IDCT_LEVELS), | |
| 305 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
| 306 DECLARE_VREG(IDCT_AUTH), | |
| 307 DECLARE_VREG(IDCT_CONTROL) | |
| 2870 | 308 }; |
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309 #endif |
| 2870 | 310 static uint32_t radeon_vid_in_use = 0; |
| 311 | |
| 312 static uint8_t *radeon_mmio_base = 0; | |
| 313 static uint32_t radeon_mem_base = 0; | |
| 3019 | 314 static int32_t radeon_overlay_off = 0; |
| 2870 | 315 static uint32_t radeon_ram_size = 0; |
| 3263 | 316 #define PARAM_BUFF_SIZE 4096 |
| 317 static uint8_t *radeon_param_buff = NULL; | |
| 318 static uint32_t radeon_param_buff_size=0; | |
| 319 static uint32_t radeon_param_buff_len=0; /* real length of buffer */ | |
| 2870 | 320 static mga_vid_config_t radeon_config; |
| 321 | |
| 3122 | 322 static char *fourcc_format_name(int format) |
| 323 { | |
| 324 switch(format) | |
| 325 { | |
| 326 case IMGFMT_RGB8: return("RGB 8-bit"); | |
| 327 case IMGFMT_RGB15: return("RGB 15-bit"); | |
| 328 case IMGFMT_RGB16: return("RGB 16-bit"); | |
| 329 case IMGFMT_RGB24: return("RGB 24-bit"); | |
| 330 case IMGFMT_RGB32: return("RGB 32-bit"); | |
| 331 case IMGFMT_BGR8: return("BGR 8-bit"); | |
| 332 case IMGFMT_BGR15: return("BGR 15-bit"); | |
| 333 case IMGFMT_BGR16: return("BGR 16-bit"); | |
| 334 case IMGFMT_BGR24: return("BGR 24-bit"); | |
| 335 case IMGFMT_BGR32: return("BGR 32-bit"); | |
| 336 case IMGFMT_YVU9: return("Planar YVU9"); | |
| 337 case IMGFMT_IF09: return("Planar IF09"); | |
| 338 case IMGFMT_YV12: return("Planar YV12"); | |
| 339 case IMGFMT_I420: return("Planar I420"); | |
| 340 case IMGFMT_IYUV: return("Planar IYUV"); | |
| 341 case IMGFMT_CLPL: return("Planar CLPL"); | |
| 3198 | 342 case IMGFMT_Y800: return("Planar Y800"); |
| 343 case IMGFMT_Y8: return("Planar Y8"); | |
| 344 case IMGFMT_IUYV: return("Packed IUYV"); | |
| 345 case IMGFMT_IY41: return("Packed IY41"); | |
| 3122 | 346 case IMGFMT_IYU1: return("Packed IYU1"); |
| 347 case IMGFMT_IYU2: return("Packed IYU2"); | |
| 348 case IMGFMT_UYVY: return("Packed UYVY"); | |
| 349 case IMGFMT_UYNV: return("Packed UYNV"); | |
| 350 case IMGFMT_cyuv: return("Packed CYUV"); | |
| 3198 | 351 case IMGFMT_Y422: return("Packed Y422"); |
| 3122 | 352 case IMGFMT_YUY2: return("Packed YUY2"); |
| 353 case IMGFMT_YUNV: return("Packed YUNV"); | |
| 354 case IMGFMT_YVYU: return("Packed YVYU"); | |
| 355 case IMGFMT_Y41P: return("Packed Y41P"); | |
| 356 case IMGFMT_Y211: return("Packed Y211"); | |
| 357 case IMGFMT_Y41T: return("Packed Y41T"); | |
| 358 case IMGFMT_Y42T: return("Packed Y42T"); | |
| 359 case IMGFMT_V422: return("Packed V422"); | |
| 360 case IMGFMT_V655: return("Packed V655"); | |
| 361 case IMGFMT_CLJR: return("Packed CLJR"); | |
| 362 case IMGFMT_YUVP: return("Packed YUVP"); | |
| 363 case IMGFMT_UYVP: return("Packed UYVP"); | |
| 3198 | 364 case IMGFMT_MPEGPES: return("Mpeg PES"); |
| 3122 | 365 } |
| 366 return("Unknown"); | |
| 367 } | |
| 368 | |
| 2870 | 369 |
| 370 /* | |
| 371 * IO macros | |
| 372 */ | |
| 373 | |
| 374 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
| 375 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
| 376 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
| 377 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
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378 #define OUTREGP(addr,val,mask) \ |
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379 do { \ |
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380 unsigned int _tmp = INREG(addr); \ |
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381 _tmp &= (mask); \ |
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382 _tmp |= (val); \ |
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383 OUTREG(addr, _tmp); \ |
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384 } while (0) |
| 2870 | 385 |
| 3278 | 386 static uint32_t radeon_vid_get_dbpp( void ) |
| 387 { | |
| 388 uint32_t dbpp,retval; | |
| 389 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
| 390 switch(dbpp) | |
| 391 { | |
| 392 case DST_8BPP: retval = 8; break; | |
| 393 case DST_15BPP: retval = 15; break; | |
| 394 case DST_16BPP: retval = 16; break; | |
| 395 case DST_24BPP: retval = 24; break; | |
| 396 default: retval=32; break; | |
| 397 } | |
| 398 return retval; | |
| 399 } | |
| 400 | |
| 3369 | 401 static int radeon_is_dbl_scan( void ) |
| 402 { | |
| 403 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
| 404 } | |
| 405 | |
| 3380 | 406 static int radeon_is_interlace( void ) |
| 407 { | |
| 408 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
| 409 } | |
| 3369 | 410 |
|
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411 static __inline__ void radeon_engine_flush ( void ) |
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412 { |
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413 int i; |
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414 |
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415 /* initiate flush */ |
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416 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, |
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417 ~RB2D_DC_FLUSH_ALL); |
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418 |
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419 for (i=0; i < 2000000; i++) { |
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420 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) |
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421 break; |
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422 } |
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423 } |
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424 |
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425 |
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426 static __inline__ void _radeon_fifo_wait (int entries) |
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427 { |
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428 int i; |
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429 |
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430 for (i=0; i<2000000; i++) |
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431 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) |
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432 return; |
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433 } |
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434 |
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435 |
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436 static __inline__ void _radeon_engine_idle ( void ) |
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437 { |
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438 int i; |
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439 |
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440 /* ensure FIFO is empty before waiting for idle */ |
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441 _radeon_fifo_wait (64); |
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442 |
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443 for (i=0; i<2000000; i++) { |
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444 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { |
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445 radeon_engine_flush (); |
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446 return; |
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447 } |
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448 } |
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449 } |
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450 |
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451 #define radeon_engine_idle() _radeon_engine_idle() |
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452 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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453 |
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454 #if 0 |
| 3265 | 455 static void __init radeon_vid_save_state( void ) |
| 2870 | 456 { |
| 457 size_t i; | |
| 458 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
| 459 vregs[i].value = INREG(vregs[i].name); | |
| 460 } | |
| 461 | |
| 3265 | 462 static void __exit radeon_vid_restore_state( void ) |
| 2870 | 463 { |
| 464 size_t i; | |
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465 radeon_fifo_wait(2); |
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466 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
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467 radeon_engine_idle(); |
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468 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
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469 radeon_fifo_wait(15); |
| 2870 | 470 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
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471 { |
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472 radeon_fifo_wait(1); |
| 2870 | 473 OUTREG(vregs[i].name,vregs[i].value); |
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474 } |
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475 OUTREG(OV0_REG_LOAD_CNTL, 0); |
| 2870 | 476 } |
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477 #endif |
| 3305 | 478 #ifdef DEBUG |
| 479 static void radeon_vid_dump_regs( void ) | |
| 480 { | |
| 481 size_t i; | |
| 482 printk(RVID_MSG"*** Begin of OV0 registers dump ***\n"); | |
| 483 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
| 484 printk(RVID_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
| 485 printk(RVID_MSG"*** End of OV0 registers dump ***\n"); | |
| 486 } | |
| 487 #endif | |
| 488 | |
|
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489 #ifdef RADEON_FPU |
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490 /* Reference color space transform data */ |
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491 typedef struct tagREF_TRANSFORM |
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492 { |
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493 float RefLuma; |
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494 float RefRCb; |
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495 float RefRCr; |
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496 float RefGCb; |
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497 float RefGCr; |
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498 float RefBCb; |
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499 float RefBCr; |
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500 } REF_TRANSFORM; |
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501 |
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502 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ |
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503 REF_TRANSFORM trans[2] = |
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504 { |
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505 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ |
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506 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ |
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507 }; |
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508 /**************************************************************************** |
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509 * SetTransform * |
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510 * Function: Calculates and sets color space transform from supplied * |
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511 * reference transform, gamma, brightness, contrast, hue and * |
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512 * saturation. * |
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513 * Inputs: bright - brightness * |
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514 * cont - contrast * |
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515 * sat - saturation * |
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516 * hue - hue * |
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517 * ref - index to the table of refernce transforms * |
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518 * Outputs: NONE * |
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519 ****************************************************************************/ |
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520 |
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521 static void radeon_set_transform(float bright, float cont, float sat, |
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522 float hue, unsigned ref) |
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523 { |
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524 float OvHueSin, OvHueCos; |
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525 float CAdjLuma, CAdjOff; |
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526 float CAdjRCb, CAdjRCr; |
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527 float CAdjGCb, CAdjGCr; |
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528 float CAdjBCb, CAdjBCr; |
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529 float OvLuma, OvROff, OvGOff, OvBOff; |
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530 float OvRCb, OvRCr; |
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531 float OvGCb, OvGCr; |
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532 float OvBCb, OvBCr; |
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533 float Loff = 64.0; |
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534 float Coff = 512.0f; |
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535 |
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536 u32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; |
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537 u32 dwOvRCb, dwOvRCr; |
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538 u32 dwOvGCb, dwOvGCr; |
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539 u32 dwOvBCb, dwOvBCr; |
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540 |
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541 if (ref >= 2) return; |
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542 |
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543 OvHueSin = sin((double)hue); |
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544 OvHueCos = cos((double)hue); |
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545 |
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546 CAdjLuma = cont * trans[ref].RefLuma; |
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547 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; |
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|
548 |
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549 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; |
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550 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; |
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551 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); |
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552 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); |
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553 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; |
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|
554 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; |
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|
555 |
|
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|
556 #if 0 /* default constants */ |
|
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|
557 CAdjLuma = 1.16455078125; |
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|
558 |
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559 CAdjRCb = 0.0; |
|
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560 CAdjRCr = 1.59619140625; |
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561 CAdjGCb = -0.39111328125; |
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|
562 CAdjGCr = -0.8125; |
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563 CAdjBCb = 2.01708984375; |
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|
564 CAdjBCr = 0; |
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|
565 #endif |
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|
566 OvLuma = CAdjLuma; |
|
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567 OvRCb = CAdjRCb; |
|
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568 OvRCr = CAdjRCr; |
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|
569 OvGCb = CAdjGCb; |
|
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570 OvGCr = CAdjGCr; |
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571 OvBCb = CAdjBCb; |
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|
572 OvBCr = CAdjBCr; |
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573 OvROff = CAdjOff - |
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574 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
|
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575 OvGOff = CAdjOff - |
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576 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
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577 OvBOff = CAdjOff - |
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578 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
|
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|
579 #if 0 /* default constants */ |
|
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580 OvROff = -888.5; |
|
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581 OvGOff = 545; |
|
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582 OvBOff = -1104; |
|
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583 #endif |
|
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|
584 |
|
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585 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; |
|
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586 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; |
|
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587 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; |
|
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|
588 if(!IsR200) |
|
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|
589 { |
|
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590 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
|
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591 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; |
|
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592 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; |
|
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|
593 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; |
|
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594 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; |
|
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595 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; |
|
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596 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; |
|
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|
597 } |
|
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598 else |
|
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changeset
|
599 { |
|
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600 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; |
|
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601 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; |
|
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|
602 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; |
|
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603 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; |
|
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|
604 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; |
|
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605 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; |
|
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606 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; |
|
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|
607 } |
|
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|
608 |
|
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|
609 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
|
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610 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); |
|
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611 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); |
|
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612 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); |
|
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|
613 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); |
|
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|
614 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); |
|
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|
615 } |
|
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|
616 #endif |
|
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|
617 |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
618 #ifndef RAGE128 |
|
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|
619 /* Gamma curve definition */ |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
620 typedef struct |
|
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|
621 { |
|
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|
622 unsigned int gammaReg; |
|
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|
623 unsigned int gammaSlope; |
|
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|
624 unsigned int gammaOffset; |
|
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|
625 }GAMMA_SETTINGS; |
|
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|
626 |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
627 /* Recommended gamma curve parameters */ |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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628 GAMMA_SETTINGS r200_def_gamma[18] = |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
629 { |
|
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|
630 {OV0_GAMMA_0_F, 0x100, 0x0000}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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631 {OV0_GAMMA_10_1F, 0x100, 0x0020}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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632 {OV0_GAMMA_20_3F, 0x100, 0x0040}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
633 {OV0_GAMMA_40_7F, 0x100, 0x0080}, |
|
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634 {OV0_GAMMA_80_BF, 0x100, 0x0100}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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635 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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636 {OV0_GAMMA_100_13F, 0x100, 0x0200}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
637 {OV0_GAMMA_140_17F, 0x100, 0x0200}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
638 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
639 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
640 {OV0_GAMMA_200_23F, 0x100, 0x0400}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
641 {OV0_GAMMA_240_27F, 0x100, 0x0400}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
642 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
643 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
644 {OV0_GAMMA_300_33F, 0x100, 0x0600}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
645 {OV0_GAMMA_340_37F, 0x100, 0x0600}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
646 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
647 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
648 }; |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
649 |
|
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diff
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|
650 GAMMA_SETTINGS r100_def_gamma[6] = |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
651 { |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
652 {OV0_GAMMA_0_F, 0x100, 0x0000}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
653 {OV0_GAMMA_10_1F, 0x100, 0x0020}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
654 {OV0_GAMMA_20_3F, 0x100, 0x0040}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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changeset
|
655 {OV0_GAMMA_40_7F, 0x100, 0x0080}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
656 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
657 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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|
658 }; |
|
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Radeon specific gamma correction initialization. (from gatos.sf.net)
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changeset
|
659 |
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660 static void make_default_gamma_correction( void ) |
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661 { |
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662 size_t i; |
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663 if(!IsR200){ |
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664 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
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665 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); |
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666 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); |
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667 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); |
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668 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); |
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669 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); |
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670 for(i=0; i<6; i++){ |
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671 OUTREG(r100_def_gamma[i].gammaReg, |
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672 (r100_def_gamma[i].gammaSlope<<16) | |
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673 r100_def_gamma[i].gammaOffset); |
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674 } |
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675 } |
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676 else{ |
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677 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); |
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678 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); |
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679 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); |
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680 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); |
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681 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); |
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682 OUTREG(OV0_LIN_TRANS_F, 0x175f); |
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683 |
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684 /* Default Gamma, |
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685 Of 18 segments for gamma cure, all segments in R200 are programmable, |
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686 while only lower 4 and upper 2 segments are programmable in Radeon*/ |
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687 for(i=0; i<18; i++){ |
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688 OUTREG(r200_def_gamma[i].gammaReg, |
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689 (r200_def_gamma[i].gammaSlope<<16) | |
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690 r200_def_gamma[i].gammaOffset); |
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691 } |
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692 } |
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693 } |
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694 #endif |
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695 |
| 2870 | 696 static void radeon_vid_stop_video( void ) |
| 697 { | |
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698 radeon_engine_idle(); |
| 2870 | 699 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); |
| 700 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
| 701 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
| 3487 | 702 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); |
| 2870 | 703 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
| 704 OUTREG(OV0_TEST, 0); | |
| 705 } | |
| 706 | |
| 707 static void radeon_vid_display_video( void ) | |
| 708 { | |
| 709 int bes_flags; | |
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710 radeon_fifo_wait(2); |
| 2870 | 711 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
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712 radeon_engine_idle(); |
| 2870 | 713 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
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714 radeon_fifo_wait(15); |
| 2870 | 715 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
| 3348 | 716 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); |
| 717 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
| 2870 | 718 |
| 3250 | 719 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
| 3470 | 720 #ifdef RAGE128 |
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721 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
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722 (besr.saturation << 8) | |
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723 (besr.saturation << 16)); |
| 3470 | 724 #endif |
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725 radeon_fifo_wait(2); |
| 3278 | 726 if(besr.ckey_on) |
| 727 { | |
| 728 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
| 729 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
| 3347 | 730 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); |
| 3278 | 731 } |
| 3366 | 732 else |
| 733 { | |
| 734 OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); | |
| 735 OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); | |
| 736 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
| 737 } | |
| 738 | |
| 2870 | 739 OUTREG(OV0_H_INC, besr.h_inc); |
| 740 OUTREG(OV0_STEP_BY, besr.step_by); | |
| 741 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
| 742 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
| 743 OUTREG(OV0_V_INC, besr.v_inc); | |
| 744 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
| 3164 | 745 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
| 2870 | 746 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
| 2944 | 747 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
| 2870 | 748 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
| 749 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
| 750 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
| 3487 | 751 #ifdef RADEON |
| 3122 | 752 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
| 753 #endif | |
| 2870 | 754 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
| 755 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
| 756 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
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757 radeon_fifo_wait(9); |
| 2870 | 758 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); |
| 759 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
| 760 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
| 761 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
| 762 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
| 763 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
| 3164 | 764 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
| 2870 | 765 |
| 766 bes_flags = SCALER_ENABLE | | |
| 767 SCALER_SMART_SWITCH | | |
| 3334 | 768 #ifdef RADEON |
| 3305 | 769 SCALER_HORZ_PICK_NEAREST; |
| 3334 | 770 #else |
| 771 SCALER_Y2R_TEMP | | |
| 772 SCALER_PIX_EXPAND; | |
| 773 #endif | |
| 3250 | 774 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; |
| 775 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
| 3198 | 776 #ifdef RAGE128 |
| 777 bes_flags |= SCALER_BURST_PER_PLANE; | |
| 778 #endif | |
| 2870 | 779 switch(besr.fourcc) |
| 780 { | |
| 781 case IMGFMT_RGB15: | |
| 782 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
| 783 case IMGFMT_RGB16: | |
| 784 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
| 785 case IMGFMT_RGB24: | |
| 786 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
| 787 case IMGFMT_RGB32: | |
| 788 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
| 3164 | 789 /* 4:1:0*/ |
| 790 case IMGFMT_IF09: | |
| 2870 | 791 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
| 3164 | 792 /* 4:2:0 */ |
| 3122 | 793 case IMGFMT_IYUV: |
| 2870 | 794 case IMGFMT_I420: |
| 3305 | 795 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; |
| 796 break; | |
| 3164 | 797 /* 4:2:2 */ |
| 798 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
| 2870 | 799 case IMGFMT_YUY2: |
| 800 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
| 801 } | |
| 802 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
| 803 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
| 3305 | 804 #ifdef DEBUG |
| 805 radeon_vid_dump_regs(); | |
| 806 #endif | |
| 2870 | 807 } |
| 808 | |
| 3278 | 809 void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B) |
| 810 { | |
| 811 besr.ckey_on = ckey_on; | |
| 3347 | 812 besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1; |
| 3278 | 813 besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24); |
| 814 } | |
| 815 | |
| 816 | |
| 2951 | 817 #define XXX_SRC_X 0 |
| 818 #define XXX_SRC_Y 0 | |
| 2870 | 819 |
| 820 static int radeon_vid_init_video( mga_vid_config_t *config ) | |
| 821 { | |
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822 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
| 3019 | 823 int is_420; |
| 3164 | 824 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
| 2870 | 825 ,(uint32_t)config->version |
| 2951 | 826 ,(uint32_t)config->format |
| 2870 | 827 ,(uint32_t)config->card_type |
| 828 ,(uint32_t)config->ram_size | |
| 829 ,(uint32_t)config->src_width | |
| 830 ,(uint32_t)config->src_height | |
| 831 ,(uint32_t)config->x_org | |
| 832 ,(uint32_t)config->y_org | |
| 833 ,(uint32_t)config->dest_width | |
| 834 ,(uint32_t)config->dest_height | |
| 835 ,(uint32_t)config->frame_size | |
| 836 ,(uint32_t)config->num_frames); | |
| 2917 | 837 radeon_vid_stop_video(); |
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838 left = XXX_SRC_X << 16; |
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839 top = XXX_SRC_Y << 16; |
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840 src_h = config->src_height; |
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841 src_w = config->src_width; |
| 2870 | 842 switch(config->format) |
| 843 { | |
| 844 case IMGFMT_RGB15: | |
| 845 case IMGFMT_BGR15: | |
| 846 case IMGFMT_RGB16: | |
| 847 case IMGFMT_BGR16: | |
| 848 case IMGFMT_RGB24: | |
| 849 case IMGFMT_BGR24: | |
| 850 case IMGFMT_RGB32: | |
| 851 case IMGFMT_BGR32: | |
| 3164 | 852 /* 4:1:0 */ |
| 853 case IMGFMT_IF09: | |
| 2870 | 854 case IMGFMT_YVU9: |
| 3164 | 855 /* 4:2:0 */ |
| 2870 | 856 case IMGFMT_IYUV: |
| 857 case IMGFMT_YV12: | |
| 858 case IMGFMT_I420: | |
| 3164 | 859 /* 4:2:2 */ |
| 860 case IMGFMT_UYVY: | |
| 2870 | 861 case IMGFMT_YUY2: |
| 862 break; | |
| 863 default: | |
| 3164 | 864 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
| 2870 | 865 return -1; |
| 866 } | |
| 3019 | 867 is_420 = 0; |
| 3122 | 868 if(config->format == IMGFMT_YV12 || |
| 869 config->format == IMGFMT_I420 || | |
| 870 config->format == IMGFMT_IYUV) is_420 = 1; | |
| 2951 | 871 switch(config->format) |
| 872 { | |
| 3164 | 873 /* 4:1:0 */ |
| 2951 | 874 case IMGFMT_YVU9: |
| 3164 | 875 case IMGFMT_IF09: |
| 876 /* 4:2:0 */ | |
| 2951 | 877 case IMGFMT_IYUV: |
| 3164 | 878 case IMGFMT_YV12: |
| 879 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
| 880 /* 4:2:2 */ | |
| 881 default: | |
| 2951 | 882 case IMGFMT_UYVY: |
| 883 case IMGFMT_YUY2: | |
| 884 case IMGFMT_RGB15: | |
| 885 case IMGFMT_BGR15: | |
| 886 case IMGFMT_RGB16: | |
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887 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
| 2951 | 888 case IMGFMT_RGB24: |
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889 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
| 2951 | 890 case IMGFMT_RGB32: |
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891 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
| 2951 | 892 } |
| 3380 | 893 if(radeon_is_dbl_scan()) config->dest_height *= 2; |
| 894 else | |
| 895 if(radeon_is_interlace()) config->dest_height /= 2; | |
| 3278 | 896 besr.dest_bpp = radeon_vid_get_dbpp(); |
| 2870 | 897 besr.fourcc = config->format; |
| 3369 | 898 besr.v_inc = (src_h << 20) / config->dest_height; |
| 899 h_inc = (src_w << 12) / config->dest_width; | |
| 2944 | 900 step_by = 1; |
| 2870 | 901 |
| 2944 | 902 while(h_inc >= (2 << 12)) { |
| 903 step_by++; | |
| 904 h_inc >>= 1; | |
| 2870 | 905 } |
| 906 | |
| 907 /* keep everything in 16.16 */ | |
| 3164 | 908 besr.base_addr = radeon_mem_base; |
| 3019 | 909 if(is_420) |
| 910 { | |
| 3164 | 911 uint32_t d1line,d2line,d3line; |
| 912 d1line = top*pitch; | |
| 913 d2line = src_h*pitch+(d1line>>1); | |
| 914 d3line = d2line+((src_h*pitch)>>2); | |
| 915 d1line += (left >> 16) & ~15; | |
| 916 d2line += (left >> 17) & ~15; | |
| 917 d3line += (left >> 17) & ~15; | |
| 918 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
| 919 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
| 920 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
| 921 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
| 922 { | |
| 923 uint32_t tmp; | |
| 924 tmp = besr.vid_buf1_base_adrs; | |
| 925 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
| 926 besr.vid_buf2_base_adrs = tmp; | |
| 927 } | |
| 3019 | 928 } |
| 929 else | |
| 930 { | |
| 931 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
| 3198 | 932 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; |
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933 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
| 3019 | 934 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
| 935 } | |
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936 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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937 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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938 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
| 2870 | 939 |
| 2951 | 940 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
| 2870 | 941 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
| 2951 | 942 ((tmp << 12) & 0xf0000000); |
| 2870 | 943 |
| 2951 | 944 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
| 2870 | 945 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
| 2951 | 946 ((tmp << 12) & 0x70000000); |
| 947 tmp = (top & 0x0000ffff) + 0x00018000; | |
| 3122 | 948 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
| 949 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
| 3019 | 950 |
| 951 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
| 3122 | 952 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
| 953 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
| 3019 | 954 |
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955 leftUV = (left >> 17) & 15; |
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956 left = (left >> 16) & 15; |
| 2944 | 957 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
| 958 besr.step_by = step_by | (step_by << 8); | |
| 3164 | 959 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
| 960 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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961 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
| 3122 | 962 if(is_420) |
| 963 { | |
| 964 src_h = (src_h + 1) >> 1; | |
| 965 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
| 966 } | |
| 967 else besr.p23_blank_lines_at_top = 0; | |
| 2870 | 968 besr.vid_buf_pitch0_value = pitch; |
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969 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
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970 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
| 3164 | 971 src_w>>=1; |
| 972 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
| 973 besr.p3_x_start_end = besr.p2_x_start_end; | |
| 2870 | 974 return 0; |
| 975 } | |
| 976 | |
| 977 static void radeon_vid_frame_sel(int frame) | |
| 978 { | |
| 3066 | 979 uint32_t off0,off1,off2; |
| 3250 | 980 if(!besr.double_buff) return; |
| 3066 | 981 if(frame%2) |
| 982 { | |
| 983 off0 = besr.vid_buf3_base_adrs; | |
| 984 off1 = besr.vid_buf4_base_adrs; | |
| 985 off2 = besr.vid_buf5_base_adrs; | |
| 986 } | |
| 987 else | |
| 988 { | |
| 989 off0 = besr.vid_buf0_base_adrs; | |
| 990 off1 = besr.vid_buf1_base_adrs; | |
| 991 off2 = besr.vid_buf2_base_adrs; | |
| 992 } | |
| 2917 | 993 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
| 994 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
| 3066 | 995 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
| 996 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
| 997 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
| 2917 | 998 OUTREG(OV0_REG_LOAD_CNTL, 0); |
| 2870 | 999 } |
| 1000 | |
| 3250 | 1001 static void radeon_vid_make_default(void) |
| 1002 { | |
| 3470 | 1003 #ifdef RAGE128 |
| 3366 | 1004 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ |
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1005 #else |
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1006 make_default_gamma_correction(); |
| 3470 | 1007 #endif |
| 3250 | 1008 besr.deinterlace_pattern = 0x900AAAAA; |
| 1009 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
| 1010 besr.deinterlace_on=1; | |
| 1011 besr.double_buff=1; | |
| 1012 } | |
| 1013 | |
| 1014 | |
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1015 static void radeon_vid_preset(void) |
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1016 { |
| 3470 | 1017 #ifdef RAGE128 |
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1018 unsigned tmp; |
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1019 tmp = INREG(OV0_COLOUR_CNTL); |
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1020 besr.saturation = (tmp>>8)&0x1f; |
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1021 besr.brightness = tmp & 0x7f; |
| 3470 | 1022 #endif |
| 3250 | 1023 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); |
| 1024 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); | |
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1025 } |
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1026 |
| 2951 | 1027 static int video_on = 0; |
| 1028 | |
| 2870 | 1029 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
| 1030 { | |
| 1031 int frame; | |
| 1032 | |
| 1033 switch(cmd) | |
| 1034 { | |
| 1035 case MGA_VID_CONFIG: | |
| 3305 | 1036 RTRACE(RVID_MSG"radeon_mmio_base = %p\n",radeon_mmio_base); |
| 1037 RTRACE(RVID_MSG"radeon_mem_base = %08x\n",radeon_mem_base); | |
| 3164 | 1038 RTRACE(RVID_MSG"Received configuration\n"); |
| 2870 | 1039 |
| 1040 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
| 1041 { | |
| 3164 | 1042 printk(RVID_MSG"failed copy from userspace\n"); |
| 3019 | 1043 return -EFAULT; |
| 2870 | 1044 } |
| 1045 if(radeon_config.version != MGA_VID_VERSION){ | |
| 3164 | 1046 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
| 3019 | 1047 return -EFAULT; |
| 2870 | 1048 } |
| 1049 | |
| 1050 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
| 3164 | 1051 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
| 3019 | 1052 return -EFAULT; |
| 2870 | 1053 } |
| 1054 | |
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1055 if(radeon_config.num_frames<1){ |
| 3164 | 1056 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
| 3019 | 1057 return -EFAULT; |
| 2870 | 1058 } |
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1059 if(radeon_config.num_frames==1) besr.double_buff=0; |
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1060 if(!besr.double_buff) radeon_config.num_frames=1; |
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1061 else radeon_config.num_frames=2; |
| 2870 | 1062 radeon_config.card_type = 0; |
| 1063 radeon_config.ram_size = radeon_ram_size; | |
| 3019 | 1064 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
| 1065 radeon_overlay_off &= 0xffff0000; | |
| 1066 if(radeon_overlay_off < 0){ | |
| 3164 | 1067 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
| 3019 | 1068 return -EFAULT; |
| 1069 } | |
| 3305 | 1070 RTRACE(RVID_MSG"using video overlay at offset %08X\n",radeon_overlay_off); |
| 2870 | 1071 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
| 1072 { | |
| 3164 | 1073 printk(RVID_MSG"failed copy to userspace\n"); |
| 3019 | 1074 return -EFAULT; |
| 2870 | 1075 } |
| 3278 | 1076 radeon_vid_set_color_key(radeon_config.colkey_on, |
| 1077 radeon_config.colkey_red, | |
| 1078 radeon_config.colkey_green, | |
| 1079 radeon_config.colkey_blue); | |
| 3265 | 1080 if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); |
| 3164 | 1081 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
| 2870 | 1082 return radeon_vid_init_video(&radeon_config); |
| 1083 break; | |
| 1084 | |
| 1085 case MGA_VID_ON: | |
| 3164 | 1086 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
| 1087 radeon_vid_display_video(); | |
| 2951 | 1088 video_on = 1; |
| 2870 | 1089 break; |
| 1090 | |
| 1091 case MGA_VID_OFF: | |
| 3164 | 1092 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
| 2951 | 1093 if(video_on) radeon_vid_stop_video(); |
| 1094 video_on = 0; | |
| 2870 | 1095 break; |
| 1096 | |
| 1097 case MGA_VID_FSEL: | |
| 1098 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
| 1099 { | |
| 3164 | 1100 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
| 2870 | 1101 return(-EFAULT); |
| 1102 } | |
| 1103 radeon_vid_frame_sel(frame); | |
| 1104 break; | |
| 1105 | |
| 1106 default: | |
| 3164 | 1107 printk(RVID_MSG"Invalid ioctl\n"); |
| 2870 | 1108 return (-EINVAL); |
| 1109 } | |
| 1110 | |
| 1111 return 0; | |
| 1112 } | |
| 1113 | |
| 1114 struct ati_card_id_s | |
| 1115 { | |
| 3164 | 1116 const int id; |
| 1117 const char name[17]; | |
| 1118 }; | |
| 1119 | |
| 1120 const struct ati_card_id_s ati_card_ids[]= | |
| 2870 | 1121 { |
| 3164 | 1122 #ifdef RAGE128 |
| 1123 /* | |
| 1124 This driver should be compatible with Rage128 (pro) chips. | |
| 1125 (include adaptive deinterlacing!!!). | |
| 1126 Moreover: the same logic can be used with Mach64 chips. | |
| 1127 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
| 1128 but they are incompatible by i/o ports. So if enthusiasts will want | |
| 1129 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
| 1130 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
| 1131 fourccs (422 and 420 formats only). | |
| 1132 */ | |
| 1133 /* Rage128 Pro GL */ | |
| 1134 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
| 1135 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
| 1136 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
| 1137 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
| 1138 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
| 1139 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
| 1140 /* Rage128 Pro VR */ | |
| 1141 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
| 1142 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
| 1143 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
| 1144 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
| 1145 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
| 1146 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
| 1147 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
| 1148 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
| 1149 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
| 1150 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
| 1151 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
| 1152 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
| 1153 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
| 1154 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
| 1155 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
| 1156 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
| 1157 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
| 1158 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
| 1159 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
| 1160 /* Rage128 GL */ | |
| 1161 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
| 1162 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
| 1163 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
| 1164 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
| 1165 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
| 1166 /* Rage128 VR */ | |
| 1167 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
| 1168 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
| 1169 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
| 1170 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
| 1171 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
| 1172 /* Rage128 M3 */ | |
| 3198 | 1173 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, |
| 1174 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
| 3164 | 1175 /* Rage128 Pro Ultra */ |
| 3198 | 1176 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, |
| 1177 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
| 1178 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
| 3164 | 1179 #else |
| 1180 /* Radeons (indeed: Rage 256 Pro ;) */ | |
| 2870 | 1181 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
| 1182 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
| 1183 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
| 1184 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
| 1185 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
| 1186 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
| 1187 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
| 1188 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
| 1189 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
| 1190 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
| 3940 | 1191 { PCI_DEVICE_ID_R200_BB, "Radeon2 8500 AIW" }, |
| 2870 | 1192 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } |
| 3164 | 1193 #endif |
| 2870 | 1194 }; |
| 1195 | |
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1196 static int detected_chip; |
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1197 |
| 3265 | 1198 static int __init radeon_vid_config_card(void) |
| 2870 | 1199 { |
| 1200 struct pci_dev *dev = NULL; | |
| 1201 size_t i; | |
| 1202 | |
| 1203 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
| 1204 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
| 1205 break; | |
| 3122 | 1206 if(!dev) |
| 2870 | 1207 { |
| 3164 | 1208 printk(RVID_MSG"No supported cards found\n"); |
| 2870 | 1209 return FALSE; |
| 1210 } | |
| 1211 | |
| 1212 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
| 1213 radeon_mem_base = dev->resource[0].start; | |
| 1214 | |
| 3164 | 1215 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
| 1216 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
| 2870 | 1217 |
| 3122 | 1218 /* video memory size */ |
| 1219 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
| 1220 | |
| 3164 | 1221 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
| 3122 | 1222 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
| 1223 radeon_ram_size /= 0x100000; | |
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1224 detected_chip = i; |
| 3164 | 1225 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
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1226 #ifndef RAGE128 |
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1227 if(ati_card_ids[i].id == PCI_DEVICE_ID_R200_QL || |
| 3940 | 1228 ati_card_ids[i].id == PCI_DEVICE_ID_R200_BB || |
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1229 ati_card_ids[i].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1; |
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1230 #endif |
| 2870 | 1231 return TRUE; |
| 1232 } | |
| 1233 | |
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1234 #define PARAM_BRIGHTNESS "brightness=" |
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1235 #define PARAM_SATURATION "saturation=" |
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1236 #define PARAM_CONTRAST "contrast=" |
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1237 #define PARAM_HUE "hue=" |
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1238 #define PARAM_DOUBLE_BUFF "double_buff=" |
| 3250 | 1239 #define PARAM_DEINTERLACE "deinterlace=" |
| 1240 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" | |
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1241 #ifdef RADEON_FPU |
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1242 static int ovBrightness=0, ovSaturation=0, ovContrast=0, ovHue=0, ov_trans_idx=0; |
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1243 #endif |
| 2870 | 1244 |
| 3263 | 1245 static void radeon_param_buff_fill( void ) |
| 2870 | 1246 { |
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1247 unsigned len,saturation; |
| 3366 | 1248 int8_t brightness; |
| 1249 brightness = besr.brightness & 0x7f; | |
| 1250 /* FIXME: It's probably x86 specific convertion. But it doesn't matter | |
| 1251 for general logic - only for printing value */ | |
| 1252 if(brightness > 63) brightness = (((~besr.brightness) & 0x3f)+1) * (-1); | |
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1253 saturation = besr.saturation; |
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1254 len = 0; |
| 3263 | 1255 len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); |
| 1256 len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); | |
| 3334 | 1257 len += sprintf(&radeon_param_buff[len],"Memory: %x:%x\n",radeon_mem_base,radeon_ram_size*0x100000); |
| 3263 | 1258 len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); |
| 3334 | 1259 len += sprintf(&radeon_param_buff[len],"Overlay offset: %x\n",radeon_overlay_off); |
| 3269 | 1260 #ifdef CONFIG_MTRR |
| 3265 | 1261 len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); |
| 3269 | 1262 #endif |
| 3278 | 1263 if(besr.ckey_on) len += sprintf(&radeon_param_buff[len],"Last used color_key=%X (mask=%X)\n",besr.graphics_key_clr,besr.graphics_key_msk); |
| 3265 | 1264 len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); |
| 3278 | 1265 len += sprintf(&radeon_param_buff[len],"Last BPP: %u\n",besr.dest_bpp); |
| 3263 | 1266 len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); |
| 1267 len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); | |
| 1268 len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); | |
| 1269 len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); | |
| 3470 | 1270 #ifdef RAGE128 |
| 3366 | 1271 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",(int)brightness); |
| 3263 | 1272 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); |
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1273 #else |
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1274 #ifdef RADEON_FPU |
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1275 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",ovBrightness); |
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1276 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%i\n",ovSaturation); |
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1277 len += sprintf(&radeon_param_buff[len],PARAM_CONTRAST"%i\n",ovContrast); |
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1278 len += sprintf(&radeon_param_buff[len],PARAM_HUE"%i\n",ovHue); |
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1279 #endif |
| 3470 | 1280 #endif |
| 3263 | 1281 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); |
| 1282 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); | |
| 1283 radeon_param_buff_len = len; | |
| 1284 } | |
| 1285 | |
| 1286 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
| 1287 { | |
| 1288 uint32_t size; | |
| 1289 if(!radeon_param_buff) return -ESPIPE; | |
| 1290 if(!(*ppos)) radeon_param_buff_fill(); | |
| 1291 if(*ppos >= radeon_param_buff_len) return 0; | |
| 1292 size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); | |
| 1293 memcpy(buf,radeon_param_buff,size); | |
| 1294 *ppos += size; | |
| 1295 return size; | |
| 2870 | 1296 } |
| 1297 | |
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1298 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) |
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1299 #define RTFBrightness(a) (((a)*1.0)/2000.0) |
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1300 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
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1301 #define RTFHue(a) (((a)*3.1416)/1000.0) |
| 3940 | 1302 #define RadeonSetParm(a,b,c,d) if((b)>=(c)&&(b)<=(d)) { (a)=(b);\ |
| 1303 radeon_set_transform(RTFBrightness(ovBrightness),RTFContrast(ovContrast)\ | |
| 1304 ,RTFSaturation(ovSaturation),RTFHue(ovHue),ov_trans_idx); } | |
| 1305 | |
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1306 |
| 2870 | 1307 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) |
| 1308 { | |
| 3470 | 1309 #ifdef RAGE128 |
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1310 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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1311 { |
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1312 long brightness; |
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1313 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
| 3368 | 1314 if(brightness >= -64 && brightness <= 63) |
| 1315 { | |
| 1316 besr.brightness = brightness; | |
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1317 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | |
| 3250 | 1318 (besr.saturation << 8) | |
| 1319 (besr.saturation << 16)); | |
| 3368 | 1320 } |
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1321 } |
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1322 else |
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1323 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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1324 { |
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1325 long saturation; |
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1326 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); |
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1327 if(saturation >= 0 && saturation <= 31) |
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1328 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
| 3250 | 1329 (saturation << 8) | |
| 1330 (saturation << 16)); | |
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1331 } |
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1332 else |
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1333 #else |
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1334 #ifdef RADEON_FPU |
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1335 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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1336 { |
| 3940 | 1337 int tmp; |
| 1338 tmp=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); | |
| 1339 RadeonSetParm(ovBrightness,tmp,-1000,1000); | |
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1340 } |
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1341 else |
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1342 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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1343 { |
| 3940 | 1344 int tmp; |
| 1345 tmp=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); | |
| 1346 RadeonSetParm(ovSaturation,tmp,-1000,1000); | |
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1347 } |
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1348 else |
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1349 if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0) |
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1350 { |
| 3940 | 1351 int tmp; |
| 1352 tmp=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10); | |
| 1353 RadeonSetParm(ovContrast,tmp,-1000,1000); | |
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1354 } |
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1355 else |
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1356 if(memcmp(buf,PARAM_HUE,min(count,strlen(PARAM_HUE))) == 0) |
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1357 { |
| 3940 | 1358 int tmp; |
| 1359 tmp=simple_strtol(&buf[strlen(PARAM_HUE)],NULL,10); | |
| 1360 RadeonSetParm(ovHue,tmp,-1000,1000); | |
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1361 } |
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1362 else |
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1363 #endif |
| 3470 | 1364 #endif |
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1365 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) |
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1366 { |
| 3250 | 1367 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; |
| 1368 else besr.double_buff = 0; | |
| 1369 } | |
| 1370 else | |
| 1371 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) | |
| 1372 { | |
| 1373 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; | |
| 1374 else besr.deinterlace_on = 0; | |
| 1375 } | |
| 1376 else | |
| 1377 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) | |
| 1378 { | |
| 1379 long dpat; | |
| 1380 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); | |
| 1381 OUTREG(OV0_DEINTERLACE_PATTERN, dpat); | |
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1382 } |
| 3263 | 1383 else count = -EIO; |
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1384 radeon_vid_preset(); |
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1385 return count; |
| 2870 | 1386 } |
| 1387 | |
| 1388 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
| 1389 { | |
| 1390 | |
| 3164 | 1391 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
| 3019 | 1392 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
| 2870 | 1393 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
| 1394 { | |
| 3164 | 1395 printk(RVID_MSG"error mapping video memory\n"); |
| 2870 | 1396 return(-EAGAIN); |
| 1397 } | |
| 1398 | |
| 1399 return(0); | |
| 1400 } | |
| 1401 | |
| 1402 static int radeon_vid_release(struct inode *inode, struct file *file) | |
| 1403 { | |
| 1404 radeon_vid_in_use = 0; | |
| 1405 radeon_vid_stop_video(); | |
| 1406 | |
| 1407 MOD_DEC_USE_COUNT; | |
| 1408 return 0; | |
| 1409 } | |
| 1410 | |
| 1411 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
| 1412 { | |
| 1413 return -ESPIPE; | |
| 1414 } | |
| 1415 | |
| 1416 static int radeon_vid_open(struct inode *inode, struct file *file) | |
| 1417 { | |
| 1418 int minor = MINOR(inode->i_rdev); | |
| 1419 | |
| 1420 if(minor != 0) | |
| 1421 return(-ENXIO); | |
| 1422 | |
| 1423 if(radeon_vid_in_use == 1) | |
| 1424 return(-EBUSY); | |
| 1425 | |
| 1426 radeon_vid_in_use = 1; | |
| 1427 MOD_INC_USE_COUNT; | |
| 1428 return(0); | |
| 1429 } | |
| 1430 | |
| 1431 #if LINUX_VERSION_CODE >= 0x020400 | |
| 1432 static struct file_operations radeon_vid_fops = | |
| 1433 { | |
| 1434 llseek: radeon_vid_lseek, | |
| 3366 | 1435 read: radeon_vid_read, |
| 2870 | 1436 write: radeon_vid_write, |
| 3366 | 1437 /* |
| 1438 readdir: | |
| 1439 poll: | |
| 1440 */ | |
| 2870 | 1441 ioctl: radeon_vid_ioctl, |
| 3366 | 1442 mmap: radeon_vid_mmap, |
| 1443 open: radeon_vid_open, | |
| 1444 /* | |
| 1445 flush: | |
| 1446 */ | |
| 2870 | 1447 release: radeon_vid_release |
| 3366 | 1448 /* |
| 1449 fsync: | |
| 1450 fasync: | |
| 1451 lock: | |
| 1452 readv: | |
| 1453 writev: | |
| 1454 sendpage: | |
| 1455 get_unmapped_area: | |
| 1456 */ | |
| 2870 | 1457 }; |
| 1458 #else | |
| 1459 static struct file_operations radeon_vid_fops = | |
| 1460 { | |
| 1461 radeon_vid_lseek, | |
| 1462 radeon_vid_read, | |
| 1463 radeon_vid_write, | |
| 1464 NULL, | |
| 1465 NULL, | |
| 1466 radeon_vid_ioctl, | |
| 1467 radeon_vid_mmap, | |
| 1468 radeon_vid_open, | |
| 1469 NULL, | |
| 1470 radeon_vid_release | |
| 1471 }; | |
| 1472 #endif | |
| 1473 | |
| 1474 /* | |
| 1475 * Main Initialization Function | |
| 1476 */ | |
| 1477 | |
| 3265 | 1478 static int __init radeon_vid_initialize(void) |
| 2870 | 1479 { |
| 1480 radeon_vid_in_use = 0; | |
| 3164 | 1481 #ifdef RAGE128 |
| 1482 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
| 1483 #else | |
| 1484 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
| 1485 #endif | |
| 2870 | 1486 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
| 1487 { | |
| 3164 | 1488 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
| 2870 | 1489 return -EIO; |
| 1490 } | |
| 1491 | |
| 1492 if (!radeon_vid_config_card()) | |
| 1493 { | |
| 3164 | 1494 printk(RVID_MSG"can't configure this card\n"); |
| 2870 | 1495 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
| 1496 return -EINVAL; | |
| 1497 } | |
| 3263 | 1498 radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); |
| 1499 if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; | |
|
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1500 #if 0 |
| 2870 | 1501 radeon_vid_save_state(); |
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3607
f5cc15e11d6e
+ Added support of FIFO engine (suggested by Vladimir Dergachev)
nick
parents:
3487
diff
changeset
|
1502 #endif |
| 3250 | 1503 radeon_vid_make_default(); |
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3247
7cec2396bde3
Tune up driver through reading and writing /dev/radeon_vid ;)
nick
parents:
3198
diff
changeset
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1504 radeon_vid_preset(); |
| 3265 | 1505 #ifdef CONFIG_MTRR |
| 1506 if (mtrr) { | |
| 1507 smtrr.vram = mtrr_add(radeon_mem_base, | |
| 1508 radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); | |
| 1509 smtrr.vram_valid = 1; | |
| 1510 /* let there be speed */ | |
| 1511 printk(RVID_MSG"MTRR set to ON\n"); | |
| 1512 } | |
| 1513 #endif /* CONFIG_MTRR */ | |
| 2870 | 1514 return(0); |
| 1515 } | |
| 1516 | |
| 3265 | 1517 int __init init_module(void) |
| 2870 | 1518 { |
| 1519 return radeon_vid_initialize(); | |
| 1520 } | |
| 1521 | |
| 3265 | 1522 void __exit cleanup_module(void) |
| 2870 | 1523 { |
|
3607
f5cc15e11d6e
+ Added support of FIFO engine (suggested by Vladimir Dergachev)
nick
parents:
3487
diff
changeset
|
1524 #if 0 |
| 2870 | 1525 radeon_vid_restore_state(); |
|
3607
f5cc15e11d6e
+ Added support of FIFO engine (suggested by Vladimir Dergachev)
nick
parents:
3487
diff
changeset
|
1526 #endif |
| 2870 | 1527 if(radeon_mmio_base) |
| 1528 iounmap(radeon_mmio_base); | |
| 3263 | 1529 kfree(radeon_param_buff); |
| 3164 | 1530 RTRACE(RVID_MSG"Cleaning up module\n"); |
| 2870 | 1531 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
| 3265 | 1532 #ifdef CONFIG_MTRR |
| 1533 if (smtrr.vram_valid) | |
| 1534 mtrr_del(smtrr.vram, radeon_mem_base, | |
| 1535 radeon_ram_size*0x100000); | |
| 1536 #endif /* CONFIG_MTRR */ | |
| 2870 | 1537 } |
| 1538 |