Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 12361:a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
author | faust3 |
---|---|
date | Fri, 30 Apr 2004 20:20:37 +0000 |
parents | b52e831261b1 |
children | 83a18b230e8c |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
12286 | 6 |
7 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) | |
8 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch) | |
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9 PPC support by Alex Beregszaszi |
3996 | 10 */ |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <math.h> | |
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17 #include <inttypes.h> |
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18 |
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19 #include "../../config.h" |
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20 #include "../../bswap.h" |
4201 | 21 #include "../../libdha/pci_ids.h" |
22 #include "../../libdha/pci_names.h" | |
3996 | 23 #include "../vidix.h" |
24 #include "../fourcc.h" | |
25 #include "../../libdha/libdha.h" | |
26 #include "radeon.h" | |
27 | |
12286 | 28 #ifdef HAVE_X11 |
29 #include <X11/Xlib.h> | |
30 #endif | |
31 | |
3996 | 32 #ifdef RAGE128 |
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33 #define RADEON_MSG "[rage128]" |
3996 | 34 #define X_ADJUST 0 |
35 #else | |
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36 #define RADEON_MSG "[radeon]" |
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37 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 38 #ifndef RADEON |
39 #define RADEON | |
40 #endif | |
41 #endif | |
42 | |
4030 | 43 static int __verbose = 0; |
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44 #ifdef RADEON |
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45 static int is_shift_required = 0; |
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46 #endif |
4015 | 47 |
3996 | 48 typedef struct bes_registers_s |
49 { | |
50 /* base address of yuv framebuffer */ | |
51 uint32_t yuv_base; | |
52 uint32_t fourcc; | |
53 uint32_t dest_bpp; | |
54 /* YUV BES registers */ | |
55 uint32_t reg_load_cntl; | |
56 uint32_t h_inc; | |
57 uint32_t step_by; | |
58 uint32_t y_x_start; | |
59 uint32_t y_x_end; | |
60 uint32_t v_inc; | |
61 uint32_t p1_blank_lines_at_top; | |
62 uint32_t p23_blank_lines_at_top; | |
63 uint32_t vid_buf_pitch0_value; | |
64 uint32_t vid_buf_pitch1_value; | |
65 uint32_t p1_x_start_end; | |
66 uint32_t p2_x_start_end; | |
67 uint32_t p3_x_start_end; | |
68 uint32_t base_addr; | |
4930 | 69 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
70 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
71 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
72 uint32_t vid_nbufs; | |
3996 | 73 |
74 uint32_t p1_v_accum_init; | |
75 uint32_t p1_h_accum_init; | |
76 uint32_t p23_v_accum_init; | |
77 uint32_t p23_h_accum_init; | |
78 uint32_t scale_cntl; | |
79 uint32_t exclusive_horz; | |
80 uint32_t auto_flip_cntl; | |
81 uint32_t filter_cntl; | |
82 uint32_t key_cntl; | |
83 uint32_t test; | |
84 /* Configurable stuff */ | |
85 int double_buff; | |
86 | |
87 int brightness; | |
88 int saturation; | |
89 | |
90 int ckey_on; | |
91 uint32_t graphics_key_clr; | |
92 uint32_t graphics_key_msk; | |
4869 | 93 uint32_t ckey_cntl; |
3996 | 94 |
95 int deinterlace_on; | |
96 uint32_t deinterlace_pattern; | |
97 | |
98 } bes_registers_t; | |
99 | |
100 typedef struct video_registers_s | |
101 { | |
102 const char * sname; | |
103 uint32_t name; | |
104 uint32_t value; | |
105 }video_registers_t; | |
106 | |
107 static bes_registers_t besr; | |
108 #ifndef RAGE128 | |
8855 | 109 static int RadeonFamily=100; |
3996 | 110 #endif |
111 #define DECLARE_VREG(name) { #name, name, 0 } | |
112 static video_registers_t vregs[] = | |
113 { | |
114 DECLARE_VREG(VIDEOMUX_CNTL), | |
115 DECLARE_VREG(VIPPAD_MASK), | |
116 DECLARE_VREG(VIPPAD1_A), | |
117 DECLARE_VREG(VIPPAD1_EN), | |
118 DECLARE_VREG(VIPPAD1_Y), | |
119 DECLARE_VREG(OV0_Y_X_START), | |
120 DECLARE_VREG(OV0_Y_X_END), | |
121 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
122 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
123 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
124 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
125 DECLARE_VREG(OV0_SCALE_CNTL), | |
126 DECLARE_VREG(OV0_V_INC), | |
127 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
128 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
129 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
130 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
131 #ifdef RADEON | |
132 DECLARE_VREG(OV0_BASE_ADDR), | |
133 #endif | |
134 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
135 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
136 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
137 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
138 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
139 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
140 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
141 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
142 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
143 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
144 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
145 DECLARE_VREG(OV0_H_INC), | |
146 DECLARE_VREG(OV0_STEP_BY), | |
147 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
148 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
149 DECLARE_VREG(OV0_P1_X_START_END), | |
150 DECLARE_VREG(OV0_P2_X_START_END), | |
151 DECLARE_VREG(OV0_P3_X_START_END), | |
152 DECLARE_VREG(OV0_FILTER_CNTL), | |
153 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
154 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
155 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
156 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
157 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
158 DECLARE_VREG(OV0_FLAG_CNTL), | |
159 #ifdef RAGE128 | |
160 DECLARE_VREG(OV0_COLOUR_CNTL), | |
161 #else | |
162 DECLARE_VREG(OV0_SLICE_CNTL), | |
163 #endif | |
164 DECLARE_VREG(OV0_VID_KEY_CLR), | |
165 DECLARE_VREG(OV0_VID_KEY_MSK), | |
166 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
167 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
168 DECLARE_VREG(OV0_KEY_CNTL), | |
169 DECLARE_VREG(OV0_TEST), | |
170 DECLARE_VREG(OV0_LIN_TRANS_A), | |
171 DECLARE_VREG(OV0_LIN_TRANS_B), | |
172 DECLARE_VREG(OV0_LIN_TRANS_C), | |
173 DECLARE_VREG(OV0_LIN_TRANS_D), | |
174 DECLARE_VREG(OV0_LIN_TRANS_E), | |
175 DECLARE_VREG(OV0_LIN_TRANS_F), | |
176 DECLARE_VREG(OV0_GAMMA_0_F), | |
177 DECLARE_VREG(OV0_GAMMA_10_1F), | |
178 DECLARE_VREG(OV0_GAMMA_20_3F), | |
179 DECLARE_VREG(OV0_GAMMA_40_7F), | |
180 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
181 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
182 DECLARE_VREG(SUBPIC_CNTL), | |
183 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
184 DECLARE_VREG(SUBPIC_Y_X_START), | |
185 DECLARE_VREG(SUBPIC_Y_X_END), | |
186 DECLARE_VREG(SUBPIC_V_INC), | |
187 DECLARE_VREG(SUBPIC_H_INC), | |
188 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
189 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
190 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
191 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
192 DECLARE_VREG(SUBPIC_PITCH), | |
193 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
194 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
195 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
196 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
197 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
198 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
199 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
200 DECLARE_VREG(IDCT_RUNS), | |
201 DECLARE_VREG(IDCT_LEVELS), | |
202 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
203 DECLARE_VREG(IDCT_AUTH), | |
9044 | 204 DECLARE_VREG(IDCT_CONTROL), |
205 DECLARE_VREG(CONFIG_CNTL) | |
3996 | 206 }; |
4030 | 207 |
12286 | 208 #ifdef HAVE_X11 |
209 static uint32_t firegl_shift = 0; | |
210 #endif | |
3996 | 211 static void * radeon_mmio_base = 0; |
212 static void * radeon_mem_base = 0; | |
213 static int32_t radeon_overlay_off = 0; | |
214 static uint32_t radeon_ram_size = 0; | |
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215 /* Restore on exit */ |
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216 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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217 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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218 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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219 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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220 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
9044 | 221 #if defined(RAGE128) && (WORDS_BIGENDIAN) |
222 static uint32_t SAVED_CONFIG_CNTL = 0; | |
223 #define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) | |
224 #define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) | |
225 #endif | |
3996 | 226 |
4012 | 227 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
228 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
229 | |
230 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
231 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
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232 |
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233 static inline uint32_t INREG (uint32_t addr) { |
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234 uint32_t tmp = GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr); |
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235 return le2me_32(tmp); |
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236 } |
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237 //#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) |
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238 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,le2me_32(val)) |
3996 | 239 #define OUTREGP(addr,val,mask) \ |
240 do { \ | |
241 unsigned int _tmp = INREG(addr); \ | |
242 _tmp &= (mask); \ | |
243 _tmp |= (val); \ | |
244 OUTREG(addr, _tmp); \ | |
245 } while (0) | |
246 | |
4666 | 247 static __inline__ uint32_t INPLL(uint32_t addr) |
248 { | |
249 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
250 return (INREG(CLOCK_CNTL_DATA)); | |
251 } | |
252 | |
253 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
254 OUTREG(CLOCK_CNTL_DATA, val) | |
255 #define OUTPLLP(addr,val,mask) \ | |
256 do { \ | |
257 unsigned int _tmp = INPLL(addr); \ | |
258 _tmp &= (mask); \ | |
259 _tmp |= (val); \ | |
260 OUTPLL(addr, _tmp); \ | |
261 } while (0) | |
262 | |
3996 | 263 static uint32_t radeon_vid_get_dbpp( void ) |
264 { | |
265 uint32_t dbpp,retval; | |
266 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
267 switch(dbpp) | |
268 { | |
269 case DST_8BPP: retval = 8; break; | |
270 case DST_15BPP: retval = 15; break; | |
271 case DST_16BPP: retval = 16; break; | |
272 case DST_24BPP: retval = 24; break; | |
273 default: retval=32; break; | |
274 } | |
275 return retval; | |
276 } | |
277 | |
278 static int radeon_is_dbl_scan( void ) | |
279 { | |
280 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
281 } | |
282 | |
283 static int radeon_is_interlace( void ) | |
284 { | |
285 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
286 } | |
287 | |
4666 | 288 static uint32_t radeon_get_xres( void ) |
289 { | |
290 /* FIXME: currently we extract that from CRTC!!!*/ | |
291 uint32_t xres,h_total; | |
292 h_total = INREG(CRTC_H_TOTAL_DISP); | |
293 xres = (h_total >> 16) & 0xffff; | |
294 return (xres + 1)*8; | |
295 } | |
296 | |
297 static uint32_t radeon_get_yres( void ) | |
298 { | |
299 /* FIXME: currently we extract that from CRTC!!!*/ | |
300 uint32_t yres,v_total; | |
301 v_total = INREG(CRTC_V_TOTAL_DISP); | |
302 yres = (v_total >> 16) & 0xffff; | |
303 return yres + 1; | |
304 } | |
305 | |
4689 | 306 static void radeon_wait_vsync(void) |
307 { | |
308 int i; | |
309 | |
310 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
311 for (i = 0; i < 2000000; i++) | |
312 { | |
313 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
314 } | |
315 } | |
316 | |
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317 #ifdef RAGE128 |
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318 static void _radeon_engine_idle(void); |
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319 static void _radeon_fifo_wait(unsigned); |
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320 #define radeon_engine_idle() _radeon_engine_idle() |
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321 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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322 /* Flush all dirty data in the Pixel Cache to memory. */ |
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323 static __inline__ void radeon_engine_flush ( void ) |
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324 { |
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325 unsigned i; |
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326 |
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327 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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328 for (i = 0; i < 2000000; i++) { |
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329 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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330 } |
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331 } |
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332 |
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333 /* Reset graphics card to known state. */ |
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334 static void radeon_engine_reset( void ) |
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335 { |
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336 uint32_t clock_cntl_index; |
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337 uint32_t mclk_cntl; |
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338 uint32_t gen_reset_cntl; |
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339 |
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340 radeon_engine_flush(); |
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341 |
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342 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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343 mclk_cntl = INPLL(MCLK_CNTL); |
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344 |
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345 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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346 |
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347 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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348 |
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349 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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350 INREG(GEN_RESET_CNTL); |
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351 OUTREG(GEN_RESET_CNTL, |
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352 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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353 INREG(GEN_RESET_CNTL); |
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354 |
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355 OUTPLL(MCLK_CNTL, mclk_cntl); |
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356 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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357 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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358 } |
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359 #else |
4689 | 360 |
3996 | 361 static __inline__ void radeon_engine_flush ( void ) |
362 { | |
363 int i; | |
364 | |
365 /* initiate flush */ | |
366 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
367 ~RB2D_DC_FLUSH_ALL); | |
368 | |
369 for (i=0; i < 2000000; i++) { | |
370 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
371 break; | |
372 } | |
373 } | |
374 | |
4666 | 375 static void _radeon_engine_idle(void); |
376 static void _radeon_fifo_wait(unsigned); | |
377 #define radeon_engine_idle() _radeon_engine_idle() | |
378 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 379 |
4666 | 380 static void radeon_engine_reset( void ) |
3996 | 381 { |
4666 | 382 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
383 | |
384 radeon_engine_flush (); | |
385 | |
386 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
387 mclk_cntl = INPLL(MCLK_CNTL); | |
388 | |
389 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
390 FORCEON_MCLKA | | |
391 FORCEON_MCLKB | | |
392 FORCEON_YCLKA | | |
393 FORCEON_YCLKB | | |
394 FORCEON_MC | | |
395 FORCEON_AIC)); | |
396 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 397 |
4666 | 398 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
399 SOFT_RESET_CP | | |
400 SOFT_RESET_HI | | |
401 SOFT_RESET_SE | | |
402 SOFT_RESET_RE | | |
403 SOFT_RESET_PP | | |
404 SOFT_RESET_E2 | | |
405 SOFT_RESET_RB | | |
406 SOFT_RESET_HDP); | |
407 INREG(RBBM_SOFT_RESET); | |
408 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
409 ~(SOFT_RESET_CP | | |
410 SOFT_RESET_HI | | |
411 SOFT_RESET_SE | | |
412 SOFT_RESET_RE | | |
413 SOFT_RESET_PP | | |
414 SOFT_RESET_E2 | | |
415 SOFT_RESET_RB | | |
416 SOFT_RESET_HDP)); | |
417 INREG(RBBM_SOFT_RESET); | |
418 | |
419 OUTPLL(MCLK_CNTL, mclk_cntl); | |
420 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
421 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
422 | |
423 return; | |
3996 | 424 } |
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425 #endif |
4666 | 426 static void radeon_engine_restore( void ) |
3996 | 427 { |
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428 #ifndef RAGE128 |
4666 | 429 int pitch64; |
430 uint32_t xres,yres,bpp; | |
431 radeon_fifo_wait(1); | |
432 xres = radeon_get_xres(); | |
433 yres = radeon_get_yres(); | |
434 bpp = radeon_vid_get_dbpp(); | |
435 /* turn of all automatic flushing - we'll do it all */ | |
436 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
437 | |
438 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
439 | |
440 radeon_fifo_wait(1); | |
441 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
442 (pitch64 << 22)); | |
443 | |
444 radeon_fifo_wait(1); | |
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445 #if defined(WORDS_BIGENDIAN) |
9044 | 446 #ifdef RADEON |
447 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
448 #endif | |
4666 | 449 #else |
450 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
451 #endif | |
452 | |
453 radeon_fifo_wait(1); | |
454 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
455 | DEFAULT_SC_BOTTOM_MAX)); | |
456 radeon_fifo_wait(1); | |
457 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
458 | GMC_BRUSH_SOLID_COLOR | |
459 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 460 |
4666 | 461 radeon_fifo_wait(7); |
462 OUTREG(DST_LINE_START, 0); | |
463 OUTREG(DST_LINE_END, 0); | |
464 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
465 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
466 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
467 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
468 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
469 | |
470 radeon_engine_idle(); | |
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471 #endif |
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472 } |
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473 #ifdef RAGE128 |
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474 static void _radeon_fifo_wait (unsigned entries) |
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475 { |
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476 unsigned i; |
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477 |
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478 for(;;) |
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479 { |
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480 for (i=0; i<2000000; i++) |
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481 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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482 return; |
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483 radeon_engine_reset(); |
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484 radeon_engine_restore(); |
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485 } |
4666 | 486 } |
487 | |
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488 static void _radeon_engine_idle ( void ) |
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489 { |
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490 unsigned i; |
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491 |
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492 /* ensure FIFO is empty before waiting for idle */ |
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493 radeon_fifo_wait (64); |
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494 for(;;) |
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495 { |
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496 for (i=0; i<2000000; i++) { |
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497 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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498 radeon_engine_flush (); |
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499 return; |
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500 } |
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501 } |
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502 radeon_engine_reset(); |
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503 radeon_engine_restore(); |
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504 } |
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505 } |
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506 #else |
4666 | 507 static void _radeon_fifo_wait (unsigned entries) |
508 { | |
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509 unsigned i; |
3996 | 510 |
4666 | 511 for(;;) |
512 { | |
513 for (i=0; i<2000000; i++) | |
514 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
515 return; | |
516 radeon_engine_reset(); | |
517 radeon_engine_restore(); | |
518 } | |
519 } | |
520 static void _radeon_engine_idle ( void ) | |
521 { | |
522 int i; | |
523 | |
524 /* ensure FIFO is empty before waiting for idle */ | |
525 radeon_fifo_wait (64); | |
526 for(;;) | |
527 { | |
3996 | 528 for (i=0; i<2000000; i++) { |
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529 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 530 radeon_engine_flush (); |
531 return; | |
532 } | |
533 } | |
4666 | 534 radeon_engine_reset(); |
535 radeon_engine_restore(); | |
536 } | |
3996 | 537 } |
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538 #endif |
3996 | 539 |
540 #ifndef RAGE128 | |
541 /* Reference color space transform data */ | |
542 typedef struct tagREF_TRANSFORM | |
543 { | |
544 float RefLuma; | |
545 float RefRCb; | |
546 float RefRCr; | |
547 float RefGCb; | |
548 float RefGCr; | |
549 float RefBCb; | |
550 float RefBCr; | |
551 } REF_TRANSFORM; | |
552 | |
553 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
554 REF_TRANSFORM trans[2] = | |
555 { | |
556 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
557 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
558 }; | |
559 /**************************************************************************** | |
560 * SetTransform * | |
561 * Function: Calculates and sets color space transform from supplied * | |
562 * reference transform, gamma, brightness, contrast, hue and * | |
563 * saturation. * | |
564 * Inputs: bright - brightness * | |
565 * cont - contrast * | |
566 * sat - saturation * | |
567 * hue - hue * | |
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568 * red_intensity - intense of red component * |
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569 * green_intensity - intense of green component * |
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570 * blue_intensity - intense of blue component * |
3996 | 571 * ref - index to the table of refernce transforms * |
572 * Outputs: NONE * | |
573 ****************************************************************************/ | |
574 | |
575 static void radeon_set_transform(float bright, float cont, float sat, | |
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576 float hue, float red_intensity, |
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577 float green_intensity,float blue_intensity, |
4284 | 578 unsigned ref) |
3996 | 579 { |
580 float OvHueSin, OvHueCos; | |
581 float CAdjLuma, CAdjOff; | |
4284 | 582 float RedAdj,GreenAdj,BlueAdj; |
3996 | 583 float CAdjRCb, CAdjRCr; |
584 float CAdjGCb, CAdjGCr; | |
585 float CAdjBCb, CAdjBCr; | |
586 float OvLuma, OvROff, OvGOff, OvBOff; | |
587 float OvRCb, OvRCr; | |
588 float OvGCb, OvGCr; | |
589 float OvBCb, OvBCr; | |
590 float Loff = 64.0; | |
591 float Coff = 512.0f; | |
592 | |
593 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
594 uint32_t dwOvRCb, dwOvRCr; | |
595 uint32_t dwOvGCb, dwOvGCr; | |
596 uint32_t dwOvBCb, dwOvBCr; | |
597 | |
598 if (ref >= 2) return; | |
599 | |
600 OvHueSin = sin((double)hue); | |
601 OvHueCos = cos((double)hue); | |
602 | |
603 CAdjLuma = cont * trans[ref].RefLuma; | |
604 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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605 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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606 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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607 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 608 |
609 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
610 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
611 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
612 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
613 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
614 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
615 | |
616 #if 0 /* default constants */ | |
617 CAdjLuma = 1.16455078125; | |
618 | |
619 CAdjRCb = 0.0; | |
620 CAdjRCr = 1.59619140625; | |
621 CAdjGCb = -0.39111328125; | |
622 CAdjGCr = -0.8125; | |
623 CAdjBCb = 2.01708984375; | |
624 CAdjBCr = 0; | |
625 #endif | |
626 OvLuma = CAdjLuma; | |
627 OvRCb = CAdjRCb; | |
628 OvRCr = CAdjRCr; | |
629 OvGCb = CAdjGCb; | |
630 OvGCr = CAdjGCr; | |
631 OvBCb = CAdjBCb; | |
632 OvBCr = CAdjBCr; | |
4284 | 633 OvROff = RedAdj + CAdjOff - |
3996 | 634 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 635 OvGOff = GreenAdj + CAdjOff - |
3996 | 636 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 637 OvBOff = BlueAdj + CAdjOff - |
3996 | 638 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
639 #if 0 /* default constants */ | |
640 OvROff = -888.5; | |
641 OvGOff = 545; | |
642 OvBOff = -1104; | |
643 #endif | |
644 | |
645 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
646 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
647 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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648 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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649 as in Radeon is a lie */ |
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650 #if 0 |
8855 | 651 if(RadeonFamily == 100) |
3996 | 652 { |
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653 #endif |
3996 | 654 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
655 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
656 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
657 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
658 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
659 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
660 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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661 #if 0 |
3996 | 662 } |
663 else | |
664 { | |
665 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
666 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
667 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
668 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
669 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
670 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
671 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
672 } | |
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673 #endif |
3996 | 674 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
675 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
676 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
677 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
678 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
679 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
680 } | |
681 | |
682 /* Gamma curve definition */ | |
683 typedef struct | |
684 { | |
685 unsigned int gammaReg; | |
686 unsigned int gammaSlope; | |
687 unsigned int gammaOffset; | |
688 }GAMMA_SETTINGS; | |
689 | |
690 /* Recommended gamma curve parameters */ | |
691 GAMMA_SETTINGS r200_def_gamma[18] = | |
692 { | |
693 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
694 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
695 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
696 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
697 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
698 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
699 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
700 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
701 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
702 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
703 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
704 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
705 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
706 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
707 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
708 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
709 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
710 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
711 }; | |
712 | |
713 GAMMA_SETTINGS r100_def_gamma[6] = | |
714 { | |
715 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
716 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
717 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
718 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
719 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
720 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
721 }; | |
722 | |
723 static void make_default_gamma_correction( void ) | |
724 { | |
725 size_t i; | |
8855 | 726 if(RadeonFamily == 100) { |
3996 | 727 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
728 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
729 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
730 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
731 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
732 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
733 for(i=0; i<6; i++){ | |
734 OUTREG(r100_def_gamma[i].gammaReg, | |
735 (r100_def_gamma[i].gammaSlope<<16) | | |
736 r100_def_gamma[i].gammaOffset); | |
737 } | |
738 } | |
739 else{ | |
740 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
741 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
742 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
743 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
744 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
745 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
746 | |
747 /* Default Gamma, | |
748 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
749 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
750 for(i=0; i<18; i++){ | |
751 OUTREG(r200_def_gamma[i].gammaReg, | |
752 (r200_def_gamma[i].gammaSlope<<16) | | |
753 r200_def_gamma[i].gammaOffset); | |
754 } | |
755 } | |
756 } | |
757 #endif | |
758 | |
759 static void radeon_vid_make_default(void) | |
760 { | |
761 #ifdef RAGE128 | |
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762 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 763 #else |
764 make_default_gamma_correction(); | |
765 #endif | |
766 besr.deinterlace_pattern = 0x900AAAAA; | |
767 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
768 besr.deinterlace_on=1; | |
769 besr.double_buff=1; | |
4869 | 770 besr.ckey_on=0; |
771 besr.graphics_key_msk=0; | |
772 besr.graphics_key_clr=0; | |
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773 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 774 } |
775 | |
776 | |
777 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
778 | |
4107 | 779 static unsigned short ati_card_ids[] = |
3996 | 780 { |
781 #ifdef RAGE128 | |
782 /* | |
783 This driver should be compatible with Rage128 (pro) chips. | |
784 (include adaptive deinterlacing!!!). | |
785 Moreover: the same logic can be used with Mach64 chips. | |
786 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
787 but they are incompatible by i/o ports. So if enthusiasts will want | |
788 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
789 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
790 fourccs (422 and 420 formats only). | |
791 */ | |
792 /* Rage128 Pro GL */ | |
4107 | 793 DEVICE_ATI_RAGE_128_PA_PRO, |
794 DEVICE_ATI_RAGE_128_PB_PRO, | |
795 DEVICE_ATI_RAGE_128_PC_PRO, | |
796 DEVICE_ATI_RAGE_128_PD_PRO, | |
797 DEVICE_ATI_RAGE_128_PE_PRO, | |
798 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 799 /* Rage128 Pro VR */ |
4107 | 800 DEVICE_ATI_RAGE_128_PG_PRO, |
801 DEVICE_ATI_RAGE_128_PH_PRO, | |
802 DEVICE_ATI_RAGE_128_PI_PRO, | |
803 DEVICE_ATI_RAGE_128_PJ_PRO, | |
804 DEVICE_ATI_RAGE_128_PK_PRO, | |
805 DEVICE_ATI_RAGE_128_PL_PRO, | |
806 DEVICE_ATI_RAGE_128_PM_PRO, | |
807 DEVICE_ATI_RAGE_128_PN_PRO, | |
808 DEVICE_ATI_RAGE_128_PO_PRO, | |
809 DEVICE_ATI_RAGE_128_PP_PRO, | |
810 DEVICE_ATI_RAGE_128_PQ_PRO, | |
811 DEVICE_ATI_RAGE_128_PR_PRO, | |
812 DEVICE_ATI_RAGE_128_PS_PRO, | |
813 DEVICE_ATI_RAGE_128_PT_PRO, | |
814 DEVICE_ATI_RAGE_128_PU_PRO, | |
815 DEVICE_ATI_RAGE_128_PV_PRO, | |
816 DEVICE_ATI_RAGE_128_PW_PRO, | |
817 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 818 /* Rage128 GL */ |
4107 | 819 DEVICE_ATI_RAGE_128_RE_SG, |
820 DEVICE_ATI_RAGE_128_RF_SG, | |
821 DEVICE_ATI_RAGE_128_RG, | |
822 DEVICE_ATI_RAGE_128_RK_VR, | |
823 DEVICE_ATI_RAGE_128_RL_VR, | |
824 DEVICE_ATI_RAGE_128_SE_4X, | |
825 DEVICE_ATI_RAGE_128_SF_4X, | |
826 DEVICE_ATI_RAGE_128_SG_4X, | |
8854 | 827 DEVICE_ATI_RAGE_128_SH, |
4107 | 828 DEVICE_ATI_RAGE_128_SK_4X, |
829 DEVICE_ATI_RAGE_128_SL_4X, | |
830 DEVICE_ATI_RAGE_128_SM_4X, | |
8854 | 831 DEVICE_ATI_RAGE_128_4X, |
4107 | 832 DEVICE_ATI_RAGE_128_PRO, |
833 DEVICE_ATI_RAGE_128_PRO2, | |
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|
834 DEVICE_ATI_RAGE_128_PRO3, |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
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|
835 /* these seem to be based on rage 128 instead of mach64 */ |
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836 DEVICE_ATI_RAGE_MOBILITY_M3, |
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837 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 838 #else |
839 /* Radeons (indeed: Rage 256 Pro ;) */ | |
8855 | 840 DEVICE_ATI_RADEON_R100_QD, |
841 DEVICE_ATI_RADEON_R100_QE, | |
842 DEVICE_ATI_RADEON_R100_QF, | |
843 DEVICE_ATI_RADEON_R100_QG, | |
844 DEVICE_ATI_RADEON_VE_QY, | |
845 DEVICE_ATI_RADEON_VE_QZ, | |
8854 | 846 DEVICE_ATI_RADEON_MOBILITY_M7, |
847 DEVICE_ATI_RADEON_MOBILITY_M72, | |
4107 | 848 DEVICE_ATI_RADEON_MOBILITY_M6, |
849 DEVICE_ATI_RADEON_MOBILITY_M62, | |
10332 | 850 DEVICE_ATI_RADEON_MOBILITY_U1, |
8855 | 851 DEVICE_ATI_RADEON_R200_BB, |
852 DEVICE_ATI_RADEON_R200_QH, | |
853 DEVICE_ATI_RADEON_R200_QI, | |
854 DEVICE_ATI_RADEON_R200_QJ, | |
855 DEVICE_ATI_RADEON_R200_QK, | |
8854 | 856 DEVICE_ATI_RADEON_R200_QL, |
8855 | 857 DEVICE_ATI_RADEON_R200_QH2, |
858 DEVICE_ATI_RADEON_R200_QI2, | |
859 DEVICE_ATI_RADEON_R200_QJ2, | |
860 DEVICE_ATI_RADEON_R200_QK2, | |
8854 | 861 DEVICE_ATI_RADEON_RV200_QW, |
8855 | 862 DEVICE_ATI_RADEON_RV200_QX, |
863 DEVICE_ATI_RADEON_R250_ID, | |
864 DEVICE_ATI_RADEON_R250_IE, | |
865 DEVICE_ATI_RADEON_R250_IF, | |
866 DEVICE_ATI_RADEON_R250_IG, | |
867 DEVICE_ATI_RADEON_R250_LD, | |
868 DEVICE_ATI_RADEON_R250_LE, | |
869 DEVICE_ATI_RADEON_R250_LF, | |
870 DEVICE_ATI_RADEON_R250_LG, | |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
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|
871 DEVICE_ATI_RV250_5C61_RADEON, |
070fc453a20b
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faust3
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|
872 DEVICE_ATI_RV250_5C63_RADEON, |
070fc453a20b
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|
873 DEVICE_ATI_RV280_RADEON_9200, |
070fc453a20b
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faust3
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|
874 DEVICE_ATI_RV280_RADEON_92002, |
070fc453a20b
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faust3
parents:
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diff
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|
875 DEVICE_ATI_RV280_RADEON_92003, |
070fc453a20b
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876 DEVICE_ATI_RV280_RADEON_92004, |
070fc453a20b
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|
877 DEVICE_ATI_RV280_RADEON_92005, |
8855 | 878 DEVICE_ATI_RADEON_R300_ND, |
879 DEVICE_ATI_RADEON_R300_NE, | |
880 DEVICE_ATI_RADEON_R300_NF, | |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
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|
881 DEVICE_ATI_RADEON_R300_NG, |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
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|
882 DEVICE_ATI_RADEON_R300_AE, |
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faust3
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|
883 DEVICE_ATI_RADEON_R300_AF, |
11658
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
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884 DEVICE_ATI_RADEON_RV350_AP, |
12361
a84160d660af
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|
885 DEVICE_ATI_RADEON_RV350_AR, |
12060 | 886 DEVICE_ATI_RADEON_R350_NH, |
887 DEVICE_ATI_RV350_MOBILITY_RADEON, | |
888 DEVICE_ATI_RV350_MOBILITY_RADEON2 | |
3996 | 889 #endif |
890 }; | |
891 | |
892 static int find_chip(unsigned chip_id) | |
893 { | |
894 unsigned i; | |
4107 | 895 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 896 { |
4107 | 897 if(chip_id == ati_card_ids[i]) return i; |
3996 | 898 } |
899 return -1; | |
900 } | |
901 | |
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902 static pciinfo_t pci_info; |
3996 | 903 static int probed=0; |
904 | |
905 vidix_capability_t def_cap = | |
906 { | |
907 #ifdef RAGE128 | |
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908 "BES driver for Rage128 cards", |
3996 | 909 #else |
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910 "BES driver for Radeon cards", |
3996 | 911 #endif |
4327 | 912 "Nick Kurshev", |
3996 | 913 TYPE_OUTPUT | TYPE_FX, |
4191 | 914 { 0, 0, 0, 0 }, |
4282 | 915 2048, |
916 2048, | |
3996 | 917 4, |
918 4, | |
919 -1, | |
4264 | 920 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 921 VENDOR_ATI, |
3996 | 922 0, |
923 { 0, 0, 0, 0} | |
924 }; | |
925 | |
12286 | 926 #ifdef HAVE_X11 |
927 void probe_fireGL_driver() { | |
928 Display *dp = XOpenDisplay ((void*)0); | |
929 int n = 0; | |
930 char **extlist = XListExtensions (dp, &n); | |
931 XCloseDisplay (dp); | |
932 if (extlist) { | |
933 int i; | |
934 int ext_fgl = 0, ext_fglrx = 0; | |
935 for (i = 0; i < n; i++) { | |
936 if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1; | |
937 if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1; | |
938 } | |
939 if (ext_fgl) { | |
940 printf(RADEON_MSG" ATI FireGl driver detected"); | |
941 firegl_shift = 0x500000; | |
942 if (!ext_fglrx) { | |
943 printf(", but DRI seems not to be activated\n"); | |
944 printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!"); | |
945 } | |
946 printf("\n"); | |
947 } | |
948 } | |
949 } | |
950 #endif | |
3996 | 951 |
4191 | 952 int vixProbe( int verbose,int force ) |
3996 | 953 { |
954 pciinfo_t lst[MAX_PCI_DEVICES]; | |
955 unsigned i,num_pci; | |
956 int err; | |
4030 | 957 __verbose = verbose; |
3996 | 958 err = pci_scan(lst,&num_pci); |
959 if(err) | |
960 { | |
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961 printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err)); |
3996 | 962 return err; |
963 } | |
964 else | |
965 { | |
966 err = ENXIO; | |
967 for(i=0;i<num_pci;i++) | |
968 { | |
4107 | 969 if(lst[i].vendor == VENDOR_ATI) |
3996 | 970 { |
971 int idx; | |
4191 | 972 const char *dname; |
3996 | 973 idx = find_chip(lst[i].device); |
4191 | 974 if(idx == -1 && force == PROBE_NORMAL) continue; |
975 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
976 dname = dname ? dname : "Unknown chip"; | |
977 printf(RADEON_MSG" Found chip: %s\n",dname); | |
9767
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Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
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978 if ((lst[i].command & PCI_COMMAND_IO) == 0) |
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Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
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|
979 { |
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Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
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|
980 printf("[radeon] Device is disabled, ignoring\n"); |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
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981 continue; |
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982 } |
3996 | 983 #ifndef RAGE128 |
4191 | 984 if(idx != -1) |
12286 | 985 #ifdef HAVE_X11 |
986 probe_fireGL_driver(); | |
987 #endif | |
8855 | 988 { |
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026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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diff
changeset
|
989 switch(ati_card_ids[idx]) { |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
990 /* Original radeon */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
991 case DEVICE_ATI_RADEON_R100_QD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
992 case DEVICE_ATI_RADEON_R100_QE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
993 case DEVICE_ATI_RADEON_R100_QF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
994 case DEVICE_ATI_RADEON_R100_QG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
995 RadeonFamily = 100; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
996 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
997 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
998 /* Radeon VE / Radeon Mobility */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
999 case DEVICE_ATI_RADEON_VE_QY: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1000 case DEVICE_ATI_RADEON_VE_QZ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1001 case DEVICE_ATI_RADEON_MOBILITY_M6: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1002 case DEVICE_ATI_RADEON_MOBILITY_M62: |
10332 | 1003 case DEVICE_ATI_RADEON_MOBILITY_U1: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1004 RadeonFamily = 120; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1005 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1006 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1007 /* Radeon 7500 / Radeon Mobility 7500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1008 case DEVICE_ATI_RADEON_RV200_QW: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1009 case DEVICE_ATI_RADEON_RV200_QX: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1010 case DEVICE_ATI_RADEON_MOBILITY_M7: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1011 case DEVICE_ATI_RADEON_MOBILITY_M72: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1012 RadeonFamily = 150; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1013 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1014 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1015 /* Radeon 8500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1016 case DEVICE_ATI_RADEON_R200_BB: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1017 case DEVICE_ATI_RADEON_R200_QH: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1018 case DEVICE_ATI_RADEON_R200_QI: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1019 case DEVICE_ATI_RADEON_R200_QJ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1020 case DEVICE_ATI_RADEON_R200_QK: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1021 case DEVICE_ATI_RADEON_R200_QL: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1022 case DEVICE_ATI_RADEON_R200_QH2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1023 case DEVICE_ATI_RADEON_R200_QI2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1024 case DEVICE_ATI_RADEON_R200_QJ2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1025 case DEVICE_ATI_RADEON_R200_QK2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1026 RadeonFamily = 200; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1027 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1028 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1029 /* Radeon 9000 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1030 case DEVICE_ATI_RADEON_R250_ID: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1031 case DEVICE_ATI_RADEON_R250_IE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1032 case DEVICE_ATI_RADEON_R250_IF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1033 case DEVICE_ATI_RADEON_R250_IG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1034 case DEVICE_ATI_RADEON_R250_LD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1035 case DEVICE_ATI_RADEON_R250_LE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1036 case DEVICE_ATI_RADEON_R250_LF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1037 case DEVICE_ATI_RADEON_R250_LG: |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1038 case DEVICE_ATI_RV250_5C61_RADEON: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1039 case DEVICE_ATI_RV250_5C63_RADEON: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1040 RadeonFamily = 250; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1041 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1042 |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1043 /* Radeon 9200 */ |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1044 case DEVICE_ATI_RV280_RADEON_9200: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1045 case DEVICE_ATI_RV280_RADEON_92002: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1046 case DEVICE_ATI_RV280_RADEON_92003: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1047 case DEVICE_ATI_RV280_RADEON_92004: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1048 case DEVICE_ATI_RV280_RADEON_92005: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1049 RadeonFamily = 280; |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1050 break; |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1051 |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1052 /* Radeon 9700 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1053 case DEVICE_ATI_RADEON_R300_ND: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1054 case DEVICE_ATI_RADEON_R300_NE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1055 case DEVICE_ATI_RADEON_R300_NF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1056 case DEVICE_ATI_RADEON_R300_NG: |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1057 case DEVICE_ATI_RADEON_R300_AE: |
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1058 case DEVICE_ATI_RADEON_R300_AF: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1059 RadeonFamily = 300; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1060 break; |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1061 |
11658
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
wight
parents:
11371
diff
changeset
|
1062 /* Radeon 9600/9800 */ |
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
wight
parents:
11371
diff
changeset
|
1063 case DEVICE_ATI_RADEON_RV350_AP: |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1064 case DEVICE_ATI_RADEON_RV350_AR: |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1065 case DEVICE_ATI_RADEON_R350_NH: |
12060 | 1066 case DEVICE_ATI_RV350_MOBILITY_RADEON: |
1067 case DEVICE_ATI_RV350_MOBILITY_RADEON2: | |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1068 RadeonFamily = 350; |
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1069 break; |
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1070 |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1071 default: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1072 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1073 } |
8855 | 1074 } |
3996 | 1075 #endif |
4193 | 1076 if(force > PROBE_NORMAL) |
1077 { | |
1078 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
1079 if(idx == -1) | |
1080 #ifdef RAGE128 | |
4373 | 1081 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 1082 #else |
4373 | 1083 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 1084 #endif |
1085 } | |
4191 | 1086 def_cap.device_id = lst[i].device; |
3996 | 1087 err = 0; |
1088 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
1089 probed=1; | |
1090 break; | |
1091 } | |
1092 } | |
1093 } | |
1094 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
1095 return err; | |
1096 } | |
1097 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1098 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1099 |
3996 | 1100 int vixInit( void ) |
1101 { | |
4477 | 1102 int err; |
4012 | 1103 if(!probed) |
1104 { | |
1105 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
1106 return EINTR; | |
1107 } | |
1108 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 1109 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
1110 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1111 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
8942 | 1112 #ifdef RADEON |
1113 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ | |
1114 if (radeon_ram_size == 0 && | |
1115 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || | |
1116 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) | |
1117 { | |
1118 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); | |
1119 radeon_ram_size = 8192*1024; | |
1120 } | |
9240
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1121 #else |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1122 /* Rage Mobility (rage128) also has memsize bug */ |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1123 if (radeon_ram_size == 0 && |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1124 (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1125 def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1126 { |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1127 printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1128 radeon_ram_size = 8192*1024; |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1129 } |
8942 | 1130 #endif |
12072 | 1131 #ifdef WIN32 |
1132 if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024; | |
1133 #endif | |
3996 | 1134 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
1135 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 1136 radeon_vid_make_default(); |
1137 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 1138 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
1139 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1140 |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1141 radeon_fifo_wait(3); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1142 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1143 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1144 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1145 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1146 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1147 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1148 |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1149 #ifdef RADEON |
8859 | 1150 switch(RadeonFamily) |
1151 { | |
1152 case 100: | |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1153 case 120: |
8859 | 1154 case 150: |
1155 case 250: | |
1156 is_shift_required=1; | |
1157 break; | |
1158 default: | |
1159 break; | |
1160 } | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1161 #endif |
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1162 |
9044 | 1163 /* XXX: hack, but it works for me (tm) */ |
1164 #if defined(RAGE128) && (WORDS_BIGENDIAN) | |
1165 /* code from gatos */ | |
1166 { | |
1167 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); | |
1168 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & | |
1169 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); | |
1170 | |
1171 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, | |
1172 // INREG(CONFIG_CNTL)); | |
1173 } | |
1174 #endif | |
1175 | |
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652ada9f9b66
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1176 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1177 return 0; |
1178 } | |
1179 | |
1180 void vixDestroy( void ) | |
1181 { | |
6564
652ada9f9b66
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|
1182 /* remove colorkeying */ |
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|
1183 radeon_fifo_wait(3); |
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correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
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diff
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|
1184 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
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1185 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
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1186 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
d952b097c720
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|
1187 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
d952b097c720
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|
1188 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
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diff
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|
1189 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
6564
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diff
changeset
|
1190 |
9044 | 1191 #if defined(RAGE128) && (WORDS_BIGENDIAN) |
1192 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); | |
1193 // printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, | |
1194 // INREG(CONFIG_CNTL)); | |
1195 #endif | |
1196 | |
3996 | 1197 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 1198 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 1199 } |
1200 | |
1201 int vixGetCapability(vidix_capability_t *to) | |
1202 { | |
1203 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1204 return 0; | |
1205 } | |
1206 | |
6483 | 1207 /* |
1208 Full list of fourcc which are supported by Win2K redeon driver: | |
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1209 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1210 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1211 */ | |
3996 | 1212 uint32_t supported_fourcc[] = |
1213 { | |
6483 | 1214 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1215 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1216 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1217 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1218 IMGFMT_RGB16, IMGFMT_BGR16, |
1219 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1220 }; |
1221 | |
6483 | 1222 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1223 { |
6483 | 1224 unsigned int i; |
3996 | 1225 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1226 { | |
1227 if(fourcc==supported_fourcc[i]) return 1; | |
1228 } | |
1229 return 0; | |
1230 } | |
1231 | |
1232 int vixQueryFourcc(vidix_fourcc_t *to) | |
1233 { | |
1234 if(is_supported_fourcc(to->fourcc)) | |
1235 { | |
1236 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1237 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1238 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1239 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1240 VID_DEPTH_32BPP; | |
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43dc579db3d1
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diff
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|
1241 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1242 return 0; |
1243 } | |
4015 | 1244 else to->depth = to->flags = 0; |
3996 | 1245 return ENOSYS; |
1246 } | |
1247 | |
1248 static void radeon_vid_dump_regs( void ) | |
1249 { | |
1250 size_t i; | |
4015 | 1251 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1252 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1253 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1254 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1255 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1256 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1257 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1258 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1259 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1260 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1261 } |
1262 | |
1263 static void radeon_vid_stop_video( void ) | |
1264 { | |
1265 radeon_engine_idle(); | |
1266 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1267 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1268 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1269 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
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Reduce flickering on window movement (from Christophe Badina)
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|
1270 #ifdef RADEON |
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patch which removes the rage_ckey_model fix and updates
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1271 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); |
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1272 #else |
3996 | 1273 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
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1274 #endif |
3996 | 1275 OUTREG(OV0_TEST, 0); |
1276 } | |
1277 | |
1278 static void radeon_vid_display_video( void ) | |
1279 { | |
1280 int bes_flags; | |
1281 radeon_fifo_wait(2); | |
1282 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1283 radeon_engine_idle(); | |
1284 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1285 radeon_fifo_wait(15); | |
4666 | 1286 |
1287 /* Shutdown capturing */ | |
1288 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1289 OUTREG(CAP0_TRIG_CNTL, 0); | |
1290 | |
4689 | 1291 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1292 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1293 |
3996 | 1294 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1295 | |
4611 | 1296 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1297 #ifdef RAGE128 |
7493 | 1298 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1299 (((besr.saturation*31+31000)/2000) << 8) | | |
1300 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1301 #endif |
1302 radeon_fifo_wait(2); | |
4869 | 1303 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1304 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1305 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1306 |
1307 OUTREG(OV0_H_INC, besr.h_inc); | |
1308 OUTREG(OV0_STEP_BY, besr.step_by); | |
1309 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1310 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1311 OUTREG(OV0_V_INC, besr.v_inc); | |
1312 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1313 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1314 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1315 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1316 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1317 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1318 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1319 #ifdef RADEON | |
1320 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1321 #endif | |
4930 | 1322 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1323 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1324 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1325 radeon_fifo_wait(9); |
4930 | 1326 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1327 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1328 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1329 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1330 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1331 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1332 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1333 | |
6678 | 1334 #ifdef RADEON |
1335 bes_flags = SCALER_ENABLE | | |
1336 SCALER_SMART_SWITCH; | |
1337 // SCALER_HORZ_PICK_NEAREST | | |
1338 // SCALER_VERT_PICK_NEAREST | | |
1339 #endif | |
3996 | 1340 bes_flags = SCALER_ENABLE | |
1341 SCALER_SMART_SWITCH | | |
1342 SCALER_Y2R_TEMP | | |
1343 SCALER_PIX_EXPAND; | |
1344 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1345 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1346 #ifdef RAGE128 | |
1347 bes_flags |= SCALER_BURST_PER_PLANE; | |
1348 #endif | |
1349 switch(besr.fourcc) | |
1350 { | |
1351 case IMGFMT_RGB15: | |
1352 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1353 case IMGFMT_RGB16: |
3996 | 1354 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1355 /* |
3996 | 1356 case IMGFMT_RGB24: |
1357 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1358 */ |
3996 | 1359 case IMGFMT_RGB32: |
1360 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1361 /* 4:1:0 */ |
3996 | 1362 case IMGFMT_IF09: |
1363 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1364 /* 4:0:0 */ |
1365 case IMGFMT_Y800: | |
1366 case IMGFMT_Y8: | |
3996 | 1367 /* 4:2:0 */ |
1368 case IMGFMT_IYUV: | |
1369 case IMGFMT_I420: | |
6483 | 1370 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1371 /* 4:2:2 */ |
4455 | 1372 case IMGFMT_YVYU: |
3996 | 1373 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1374 case IMGFMT_YUY2: | |
1375 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1376 } | |
1377 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1378 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1379 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1380 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1381 } |
1382 | |
4456 | 1383 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1384 { |
4456 | 1385 unsigned pitch,spy,spv,spu; |
1386 spy = spv = spu = 0; | |
1387 switch(spitch->y) | |
1388 { | |
1389 case 16: | |
1390 case 32: | |
1391 case 64: | |
1392 case 128: | |
1393 case 256: spy = spitch->y; break; | |
1394 default: break; | |
1395 } | |
1396 switch(spitch->u) | |
1397 { | |
1398 case 16: | |
1399 case 32: | |
1400 case 64: | |
1401 case 128: | |
1402 case 256: spu = spitch->u; break; | |
1403 default: break; | |
1404 } | |
1405 switch(spitch->v) | |
1406 { | |
1407 case 16: | |
1408 case 32: | |
1409 case 64: | |
1410 case 128: | |
1411 case 256: spv = spitch->v; break; | |
1412 default: break; | |
1413 } | |
4009 | 1414 switch(fourcc) |
1415 { | |
1416 /* 4:2:0 */ | |
1417 case IMGFMT_IYUV: | |
1418 case IMGFMT_YV12: | |
4456 | 1419 case IMGFMT_I420: |
1420 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1421 else pitch = 32; | |
1422 break; | |
6483 | 1423 /* 4:1:0 */ |
1424 case IMGFMT_IF09: | |
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1425 case IMGFMT_YVU9: |
034b12194350
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1426 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
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changeset
|
1427 else pitch = 64; |
034b12194350
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changeset
|
1428 break; |
4456 | 1429 default: |
1430 if(spy >= 16) pitch = spy; | |
1431 else pitch = 16; | |
1432 break; | |
4009 | 1433 } |
1434 return pitch; | |
1435 } | |
1436 | |
3996 | 1437 static int radeon_vid_init_video( vidix_playback_t *config ) |
1438 { | |
4930 | 1439 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1440 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1441 radeon_vid_stop_video(); |
1442 left = config->src.x << 16; | |
1443 top = config->src.y << 16; | |
1444 src_h = config->src.h; | |
1445 src_w = config->src.w; | |
6483 | 1446 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1447 if(config->fourcc == IMGFMT_YV12 || |
1448 config->fourcc == IMGFMT_I420 || | |
1449 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1450 if(config->fourcc == IMGFMT_YVU9 || |
1451 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1452 if(config->fourcc == IMGFMT_Y800 || | |
1453 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1454 if(config->fourcc == IMGFMT_RGB32 || |
1455 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1456 if(config->fourcc == IMGFMT_RGB32 || |
1457 config->fourcc == IMGFMT_BGR32 || | |
1458 config->fourcc == IMGFMT_RGB24 || | |
1459 config->fourcc == IMGFMT_BGR24 || | |
1460 config->fourcc == IMGFMT_RGB16 || | |
1461 config->fourcc == IMGFMT_BGR16 || | |
1462 config->fourcc == IMGFMT_RGB15 || | |
1463 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1464 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1465 mpitch = best_pitch-1; |
3996 | 1466 switch(config->fourcc) |
1467 { | |
6483 | 1468 /* 4:0:0 */ |
1469 case IMGFMT_Y800: | |
1470 case IMGFMT_Y8: | |
1471 /* 4:1:0 */ | |
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1472 case IMGFMT_YVU9: |
6483 | 1473 case IMGFMT_IF09: |
3996 | 1474 /* 4:2:0 */ |
1475 case IMGFMT_IYUV: | |
1476 case IMGFMT_YV12: | |
4415 | 1477 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1478 config->dest.pitch.y = |
1479 config->dest.pitch.u = | |
4415 | 1480 config->dest.pitch.v = best_pitch; |
3996 | 1481 break; |
4416 | 1482 /* RGB 4:4:4:4 */ |
1483 case IMGFMT_RGB32: | |
1484 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1485 config->dest.pitch.y = | |
1486 config->dest.pitch.u = | |
1487 config->dest.pitch.v = best_pitch; | |
1488 break; | |
3996 | 1489 /* 4:2:2 */ |
4455 | 1490 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1491 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1492 config->dest.pitch.y = |
1493 config->dest.pitch.u = | |
4415 | 1494 config->dest.pitch.v = best_pitch; |
3996 | 1495 break; |
1496 } | |
1497 dest_w = config->dest.w; | |
1498 dest_h = config->dest.h; | |
1499 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1500 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1501 besr.fourcc = config->fourcc; | |
1502 besr.v_inc = (src_h << 20) / dest_h; | |
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changeset
|
1503 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1504 h_inc = (src_w << 12) / dest_w; |
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97f61ffa441e
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michael
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1505 |
97f61ffa441e
vidix rage128 ecp_div patch by (Magnus Damm <damm at opensource dot se>)
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1506 { |
97f61ffa441e
vidix rage128 ecp_div patch by (Magnus Damm <damm at opensource dot se>)
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1507 unsigned int ecp_div; |
97f61ffa441e
vidix rage128 ecp_div patch by (Magnus Damm <damm at opensource dot se>)
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changeset
|
1508 ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; |
97f61ffa441e
vidix rage128 ecp_div patch by (Magnus Damm <damm at opensource dot se>)
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1509 h_inc <<= ecp_div; |
97f61ffa441e
vidix rage128 ecp_div patch by (Magnus Damm <damm at opensource dot se>)
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1510 } |
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1511 |
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1512 |
3996 | 1513 step_by = 1; |
1514 while(h_inc >= (2 << 12)) { | |
1515 step_by++; | |
1516 h_inc >>= 1; | |
1517 } | |
1518 | |
1519 /* keep everything in 16.16 */ | |
4015 | 1520 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1521 config->offsets[0] = 0; |
4930 | 1522 for(i=1;i<besr.vid_nbufs;i++) |
1523 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1524 if(is_420 || is_410 || is_400) |
3996 | 1525 { |
1526 uint32_t d1line,d2line,d3line; | |
1527 d1line = top*pitch; | |
6483 | 1528 if(is_420) |
1529 { | |
1530 d2line = src_h*pitch+(d1line>>2); | |
1531 d3line = d2line+((src_h*pitch)>>2); | |
1532 } | |
1533 else | |
1534 if(is_410) | |
1535 { | |
1536 d2line = src_h*pitch+(d1line>>4); | |
1537 d3line = d2line+((src_h*pitch)>>4); | |
1538 } | |
1539 else | |
1540 { | |
1541 d2line = 0; | |
1542 d3line = 0; | |
1543 } | |
3996 | 1544 d1line += (left >> 16) & ~15; |
6483 | 1545 if(is_420) |
1546 { | |
1547 d2line += (left >> 17) & ~15; | |
1548 d3line += (left >> 17) & ~15; | |
1549 } | |
1550 else | |
1551 if(is_410) | |
1552 { | |
1553 d2line += (left >> 18) & ~15; | |
1554 d3line += (left >> 18) & ~15; | |
1555 } | |
3996 | 1556 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1557 if(is_400) |
1558 { | |
1559 config->offset.v = 0; | |
1560 config->offset.u = 0; | |
1561 } | |
1562 else | |
1563 { | |
1564 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1565 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1566 } | |
4930 | 1567 for(i=0;i<besr.vid_nbufs;i++) |
1568 { | |
1569 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1570 if(is_400) |
1571 { | |
1572 besr.vid_buf_base_adrs_v[i]=0; | |
1573 besr.vid_buf_base_adrs_u[i]=0; | |
1574 } | |
1575 else | |
1576 { | |
9892 | 1577 if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1578 { | |
1579 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1580 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1581 } | |
1582 else | |
1583 { | |
1584 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1585 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1586 } | |
6483 | 1587 } |
4930 | 1588 } |
1589 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1590 if(is_400) |
1591 { | |
1592 config->offset.v = 0; | |
1593 config->offset.u = 0; | |
1594 } | |
1595 else | |
1596 { | |
1597 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1598 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1599 } | |
3996 | 1600 } |
1601 else | |
1602 { | |
1603 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1604 for(i=0;i<besr.vid_nbufs;i++) |
1605 { | |
1606 besr.vid_buf_base_adrs_y[i] = | |
1607 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1608 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1609 } |
3996 | 1610 } |
1611 | |
1612 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1613 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1614 ((tmp << 12) & 0xf0000000); | |
1615 | |
1616 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1617 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1618 ((tmp << 12) & 0x70000000); | |
1619 tmp = (top & 0x0000ffff) + 0x00018000; | |
1620 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1621 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1622 | |
1623 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1624 besr.p23_v_accum_init = (is_420||is_410) ? |
1625 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1626 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1627 | |
6483 | 1628 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1629 left = (left >> 16) & 15; |
4571 | 1630 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1631 if(is_rgb32) |
4571 | 1632 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1633 else |
6483 | 1634 if(is_410) |
1635 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1636 else | |
4416 | 1637 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1638 besr.step_by = step_by | (step_by << 8); |
1639 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1640 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1641 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1642 if(is_420 || is_410) |
3996 | 1643 { |
6483 | 1644 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1645 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1646 } | |
1647 else besr.p23_blank_lines_at_top = 0; | |
1648 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1649 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1650 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1651 if (is_410||is_420) src_w>>=is_410?2:1; |
1652 if(is_400) | |
1653 { | |
1654 besr.p2_x_start_end = 0; | |
1655 besr.p3_x_start_end = 0; | |
1656 } | |
1657 else | |
1658 { | |
1659 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1660 besr.p3_x_start_end = besr.p2_x_start_end; | |
1661 } | |
4869 | 1662 |
3996 | 1663 return 0; |
1664 } | |
1665 | |
4009 | 1666 static void radeon_compute_framesize(vidix_playback_t *info) |
1667 { | |
4666 | 1668 unsigned pitch,awidth,dbpp; |
4456 | 1669 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1670 dbpp = radeon_vid_get_dbpp(); |
4033 | 1671 switch(info->fourcc) |
1672 { | |
1673 case IMGFMT_I420: | |
1674 case IMGFMT_YV12: | |
1675 case IMGFMT_IYUV: | |
4666 | 1676 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1677 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1678 break; |
6483 | 1679 case IMGFMT_Y800: |
1680 case IMGFMT_Y8: | |
1681 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1682 info->frame_size = awidth*info->src.h; | |
1683 break; | |
1684 case IMGFMT_IF09: | |
1685 case IMGFMT_YVU9: | |
1686 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1687 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1688 break; | |
4429 | 1689 case IMGFMT_RGB32: |
1690 case IMGFMT_BGR32: | |
4666 | 1691 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1692 info->frame_size = awidth*info->src.h; |
4429 | 1693 break; |
1694 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1695 default: |
1696 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1697 info->frame_size = awidth*info->src.h; |
4033 | 1698 break; |
1699 } | |
4009 | 1700 } |
1701 | |
3996 | 1702 int vixConfigPlayback(vidix_playback_t *info) |
1703 { | |
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1704 unsigned rgb_size,nfr; |
3996 | 1705 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1706 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1707 if(info->num_frames==1) besr.double_buff=0; |
1708 else besr.double_buff=1; | |
4009 | 1709 radeon_compute_framesize(info); |
4930 | 1710 |
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1711 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1712 nfr = info->num_frames; |
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1713 for(;nfr>0; nfr--) |
4930 | 1714 { |
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1715 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
12286 | 1716 #ifdef HAVE_X11 |
1717 radeon_overlay_off -= firegl_shift; | |
1718 #endif | |
4930 | 1719 radeon_overlay_off &= 0xffff0000; |
1720 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1721 } | |
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1722 if(nfr <= 3) |
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1723 { |
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1724 nfr = info->num_frames; |
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1725 for(;nfr>0; nfr--) |
4930 | 1726 { |
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1727 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
12286 | 1728 #ifdef HAVE_X11 |
1729 radeon_overlay_off -= firegl_shift; | |
1730 #endif | |
4930 | 1731 radeon_overlay_off &= 0xffff0000; |
1732 if(radeon_overlay_off > 0) break; | |
1733 } | |
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1734 } |
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1735 if(nfr <= 0) return EINVAL; |
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1736 info->num_frames = nfr; |
4930 | 1737 besr.vid_nbufs = info->num_frames; |
1738 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1739 radeon_vid_init_video(info); |
1740 return 0; | |
1741 } | |
1742 | |
1743 int vixPlaybackOn( void ) | |
1744 { | |
1745 radeon_vid_display_video(); | |
1746 return 0; | |
1747 } | |
1748 | |
1749 int vixPlaybackOff( void ) | |
1750 { | |
1751 radeon_vid_stop_video(); | |
1752 return 0; | |
1753 } | |
1754 | |
4033 | 1755 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1756 { |
4412 | 1757 uint32_t off[6]; |
4930 | 1758 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1759 /* |
1760 buf3-5 always should point onto second buffer for better | |
1761 deinterlacing and TV-in | |
1762 */ | |
4666 | 1763 if(!besr.double_buff) return 0; |
4930 | 1764 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1765 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1766 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1767 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1768 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1769 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1770 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1771 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1772 radeon_fifo_wait(8); |
3996 | 1773 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1774 radeon_engine_idle(); |
3996 | 1775 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1776 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1777 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1778 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1779 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1780 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1781 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1782 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1783 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1784 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1785 return 0; |
1786 } | |
1787 | |
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1788 vidix_video_eq_t equal = |
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1789 { |
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1790 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1791 #ifndef RAGE128 |
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1792 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1793 #endif |
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1794 , |
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1795 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1796 |
1797 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1798 { | |
1799 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1800 return 0; | |
1801 } | |
1802 | |
4229 | 1803 #ifndef RAGE128 |
1804 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1805 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1806 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1807 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1808 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1809 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1810 #endif | |
1811 | |
3996 | 1812 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1813 { | |
1814 #ifdef RAGE128 | |
1815 int br,sat; | |
4229 | 1816 #else |
1817 int itu_space; | |
3996 | 1818 #endif |
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1819 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1820 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1821 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1822 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1823 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1824 { |
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1825 equal.red_intensity = eq->red_intensity; |
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1826 equal.green_intensity = eq->green_intensity; |
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1827 equal.blue_intensity = eq->blue_intensity; |
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1828 } |
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1829 equal.flags = eq->flags; |
3996 | 1830 #ifdef RAGE128 |
1831 br = equal.brightness * 64 / 1000; | |
4229 | 1832 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1833 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1834 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1835 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1836 #else | |
4229 | 1837 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1838 RTFCheckParam(equal.brightness); | |
1839 RTFCheckParam(equal.saturation); | |
1840 RTFCheckParam(equal.contrast); | |
1841 RTFCheckParam(equal.hue); | |
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1842 RTFCheckParam(equal.red_intensity); |
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1843 RTFCheckParam(equal.green_intensity); |
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1844 RTFCheckParam(equal.blue_intensity); |
4229 | 1845 radeon_set_transform(RTFBrightness(equal.brightness), |
1846 RTFContrast(equal.contrast), | |
1847 RTFSaturation(equal.saturation), | |
1848 RTFHue(equal.hue), | |
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1849 RTFIntensity(equal.red_intensity), |
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1850 RTFIntensity(equal.green_intensity), |
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1851 RTFIntensity(equal.blue_intensity), |
4229 | 1852 itu_space); |
3996 | 1853 #endif |
1854 return 0; | |
1855 } | |
1856 | |
4611 | 1857 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1858 { | |
1859 unsigned sflg; | |
1860 switch(info->flags) | |
1861 { | |
1862 default: | |
1863 case CFG_NON_INTERLACED: | |
1864 besr.deinterlace_on = 0; | |
1865 break; | |
1866 case CFG_EVEN_ODD_INTERLACING: | |
1867 case CFG_INTERLACED: | |
1868 besr.deinterlace_on = 1; | |
1869 besr.deinterlace_pattern = 0x900AAAAA; | |
1870 break; | |
1871 case CFG_ODD_EVEN_INTERLACING: | |
1872 besr.deinterlace_on = 1; | |
1873 besr.deinterlace_pattern = 0x00055555; | |
1874 break; | |
1875 case CFG_UNIQUE_INTERLACING: | |
1876 besr.deinterlace_on = 1; | |
1877 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1878 break; | |
1879 } | |
1880 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1881 radeon_engine_idle(); | |
1882 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1883 radeon_fifo_wait(15); | |
1884 sflg = INREG(OV0_SCALE_CNTL); | |
1885 if(besr.deinterlace_on) | |
1886 { | |
1887 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1888 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1889 } | |
1890 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1891 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1892 return 0; | |
1893 } | |
1894 | |
1895 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1896 { | |
1897 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1898 else | |
1899 { | |
1900 info->flags = CFG_UNIQUE_INTERLACING; | |
1901 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1902 } | |
1903 return 0; | |
1904 } | |
4869 | 1905 |
1906 | |
1907 /* Graphic keys */ | |
1908 static vidix_grkey_t radeon_grkey; | |
1909 | |
1910 static void set_gr_key( void ) | |
1911 { | |
1912 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1913 { | |
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1914 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1915 besr.ckey_on=1; |
1916 | |
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1917 switch(dbpp) |
4869 | 1918 { |
1919 case 15: | |
8856 | 1920 #ifdef RADEON |
8858 | 1921 if(RadeonFamily > 100) |
8856 | 1922 besr.graphics_key_clr= |
1923 ((radeon_grkey.ckey.blue &0xF8)) | |
1924 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
1925 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1926 else | |
1927 #endif | |
4869 | 1928 besr.graphics_key_clr= |
1929 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1930 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
1931 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
1932 break; | |
1933 case 16: | |
8856 | 1934 #ifdef RADEON |
1935 /* This test may be too general/specific */ | |
8858 | 1936 if(RadeonFamily > 100) |
8856 | 1937 besr.graphics_key_clr= |
1938 ((radeon_grkey.ckey.blue &0xF8)) | |
1939 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
1940 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1941 else | |
1942 #endif | |
4869 | 1943 besr.graphics_key_clr= |
1944 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1945 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
1946 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
1947 break; | |
1948 case 24: | |
1949 besr.graphics_key_clr= | |
1950 ((radeon_grkey.ckey.blue &0xFF)) | |
1951 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1952 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1953 break; | |
1954 case 32: | |
1955 besr.graphics_key_clr= | |
1956 ((radeon_grkey.ckey.blue &0xFF)) | |
1957 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1958 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1959 break; | |
1960 default: | |
1961 besr.ckey_on=0; | |
1962 besr.graphics_key_msk=0; | |
1963 besr.graphics_key_clr=0; | |
1964 } | |
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1965 #ifdef RAGE128 |
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1966 besr.graphics_key_msk=(1<<dbpp)-1; |
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1967 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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1968 #else |
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1969 besr.graphics_key_msk=besr.graphics_key_clr; |
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1970 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; |
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1971 #endif |
4869 | 1972 } |
1973 else | |
1974 { | |
1975 besr.ckey_on=0; | |
1976 besr.graphics_key_msk=0; | |
1977 besr.graphics_key_clr=0; | |
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1978 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 1979 } |
5044
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1980 radeon_fifo_wait(3); |
4869 | 1981 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1982 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1983 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1984 } | |
1985 | |
1986 int vixGetGrKeys(vidix_grkey_t *grkey) | |
1987 { | |
1988 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
1989 return(0); | |
1990 } | |
1991 | |
1992 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
1993 { | |
1994 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
1995 set_gr_key(); | |
1996 return(0); | |
1997 } |