Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 19644:775ac4efed3c
added missing reference to radio.xml
author | Gabrov |
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date | Sat, 02 Sep 2006 21:04:06 +0000 |
parents | 26a30496ec96 |
children | 1cf4e1373d4e |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
12286 | 6 |
7 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) | |
8 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch) | |
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9 PPC support by Alex Beregszaszi |
3996 | 10 */ |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <math.h> | |
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17 #include <inttypes.h> |
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18 |
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19 #include "../../config.h" |
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20 #include "../../bswap.h" |
4201 | 21 #include "../../libdha/pci_ids.h" |
22 #include "../../libdha/pci_names.h" | |
3996 | 23 #include "../vidix.h" |
24 #include "../fourcc.h" | |
25 #include "../../libdha/libdha.h" | |
26 #include "radeon.h" | |
27 | |
12286 | 28 #ifdef HAVE_X11 |
29 #include <X11/Xlib.h> | |
30 #endif | |
31 | |
3996 | 32 #ifdef RAGE128 |
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33 #define RADEON_MSG "[rage128]" |
3996 | 34 #define X_ADJUST 0 |
35 #else | |
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36 #define RADEON_MSG "[radeon]" |
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37 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 38 #ifndef RADEON |
39 #define RADEON | |
40 #endif | |
41 #endif | |
42 | |
4030 | 43 static int __verbose = 0; |
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44 #ifdef RADEON |
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45 static int is_shift_required = 0; |
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46 #endif |
4015 | 47 |
3996 | 48 typedef struct bes_registers_s |
49 { | |
50 /* base address of yuv framebuffer */ | |
51 uint32_t yuv_base; | |
52 uint32_t fourcc; | |
53 uint32_t dest_bpp; | |
54 /* YUV BES registers */ | |
55 uint32_t reg_load_cntl; | |
56 uint32_t h_inc; | |
57 uint32_t step_by; | |
58 uint32_t y_x_start; | |
59 uint32_t y_x_end; | |
60 uint32_t v_inc; | |
61 uint32_t p1_blank_lines_at_top; | |
62 uint32_t p23_blank_lines_at_top; | |
63 uint32_t vid_buf_pitch0_value; | |
64 uint32_t vid_buf_pitch1_value; | |
65 uint32_t p1_x_start_end; | |
66 uint32_t p2_x_start_end; | |
67 uint32_t p3_x_start_end; | |
68 uint32_t base_addr; | |
4930 | 69 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
70 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
71 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
72 uint32_t vid_nbufs; | |
3996 | 73 |
74 uint32_t p1_v_accum_init; | |
75 uint32_t p1_h_accum_init; | |
76 uint32_t p23_v_accum_init; | |
77 uint32_t p23_h_accum_init; | |
78 uint32_t scale_cntl; | |
79 uint32_t exclusive_horz; | |
80 uint32_t auto_flip_cntl; | |
81 uint32_t filter_cntl; | |
82 uint32_t key_cntl; | |
83 uint32_t test; | |
84 /* Configurable stuff */ | |
85 int double_buff; | |
86 | |
87 int brightness; | |
88 int saturation; | |
89 | |
90 int ckey_on; | |
91 uint32_t graphics_key_clr; | |
92 uint32_t graphics_key_msk; | |
4869 | 93 uint32_t ckey_cntl; |
3996 | 94 |
95 int deinterlace_on; | |
96 uint32_t deinterlace_pattern; | |
97 | |
98 } bes_registers_t; | |
99 | |
100 typedef struct video_registers_s | |
101 { | |
102 const char * sname; | |
103 uint32_t name; | |
104 uint32_t value; | |
105 }video_registers_t; | |
106 | |
107 static bes_registers_t besr; | |
108 #ifndef RAGE128 | |
8855 | 109 static int RadeonFamily=100; |
3996 | 110 #endif |
111 #define DECLARE_VREG(name) { #name, name, 0 } | |
112 static video_registers_t vregs[] = | |
113 { | |
114 DECLARE_VREG(VIDEOMUX_CNTL), | |
115 DECLARE_VREG(VIPPAD_MASK), | |
116 DECLARE_VREG(VIPPAD1_A), | |
117 DECLARE_VREG(VIPPAD1_EN), | |
118 DECLARE_VREG(VIPPAD1_Y), | |
119 DECLARE_VREG(OV0_Y_X_START), | |
120 DECLARE_VREG(OV0_Y_X_END), | |
121 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
122 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
123 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
124 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
125 DECLARE_VREG(OV0_SCALE_CNTL), | |
126 DECLARE_VREG(OV0_V_INC), | |
127 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
128 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
129 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
130 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
131 #ifdef RADEON | |
132 DECLARE_VREG(OV0_BASE_ADDR), | |
133 #endif | |
134 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
135 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
136 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
137 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
138 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
139 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
140 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
141 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
142 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
143 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
144 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
145 DECLARE_VREG(OV0_H_INC), | |
146 DECLARE_VREG(OV0_STEP_BY), | |
147 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
148 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
149 DECLARE_VREG(OV0_P1_X_START_END), | |
150 DECLARE_VREG(OV0_P2_X_START_END), | |
151 DECLARE_VREG(OV0_P3_X_START_END), | |
152 DECLARE_VREG(OV0_FILTER_CNTL), | |
153 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
154 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
155 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
156 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
157 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
158 DECLARE_VREG(OV0_FLAG_CNTL), | |
159 #ifdef RAGE128 | |
160 DECLARE_VREG(OV0_COLOUR_CNTL), | |
161 #else | |
162 DECLARE_VREG(OV0_SLICE_CNTL), | |
163 #endif | |
164 DECLARE_VREG(OV0_VID_KEY_CLR), | |
165 DECLARE_VREG(OV0_VID_KEY_MSK), | |
166 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
167 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
168 DECLARE_VREG(OV0_KEY_CNTL), | |
169 DECLARE_VREG(OV0_TEST), | |
170 DECLARE_VREG(OV0_LIN_TRANS_A), | |
171 DECLARE_VREG(OV0_LIN_TRANS_B), | |
172 DECLARE_VREG(OV0_LIN_TRANS_C), | |
173 DECLARE_VREG(OV0_LIN_TRANS_D), | |
174 DECLARE_VREG(OV0_LIN_TRANS_E), | |
175 DECLARE_VREG(OV0_LIN_TRANS_F), | |
176 DECLARE_VREG(OV0_GAMMA_0_F), | |
177 DECLARE_VREG(OV0_GAMMA_10_1F), | |
178 DECLARE_VREG(OV0_GAMMA_20_3F), | |
179 DECLARE_VREG(OV0_GAMMA_40_7F), | |
180 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
181 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
182 DECLARE_VREG(SUBPIC_CNTL), | |
183 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
184 DECLARE_VREG(SUBPIC_Y_X_START), | |
185 DECLARE_VREG(SUBPIC_Y_X_END), | |
186 DECLARE_VREG(SUBPIC_V_INC), | |
187 DECLARE_VREG(SUBPIC_H_INC), | |
188 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
189 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
190 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
191 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
192 DECLARE_VREG(SUBPIC_PITCH), | |
193 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
194 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
195 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
196 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
197 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
198 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
199 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
200 DECLARE_VREG(IDCT_RUNS), | |
201 DECLARE_VREG(IDCT_LEVELS), | |
202 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
203 DECLARE_VREG(IDCT_AUTH), | |
9044 | 204 DECLARE_VREG(IDCT_CONTROL), |
205 DECLARE_VREG(CONFIG_CNTL) | |
3996 | 206 }; |
4030 | 207 |
12286 | 208 #ifdef HAVE_X11 |
209 static uint32_t firegl_shift = 0; | |
210 #endif | |
3996 | 211 static void * radeon_mmio_base = 0; |
212 static void * radeon_mem_base = 0; | |
213 static int32_t radeon_overlay_off = 0; | |
214 static uint32_t radeon_ram_size = 0; | |
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215 /* Restore on exit */ |
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216 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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217 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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218 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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219 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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220 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
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221 #ifdef WORDS_BIGENDIAN |
9044 | 222 static uint32_t SAVED_CONFIG_CNTL = 0; |
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223 #if defined(RAGE128) |
9044 | 224 #define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) |
225 #define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) | |
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226 #else |
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227 #define RADEON_SURFACE_CNTL 0x0b00 |
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228 #define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) |
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229 #define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) |
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230 #endif |
9044 | 231 #endif |
3996 | 232 |
4012 | 233 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
234 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
235 | |
14363 | 236 #define INREG8(addr) GETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr) |
237 #define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr,val) | |
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238 |
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239 static inline uint32_t INREG (uint32_t addr) { |
14363 | 240 uint32_t tmp = GETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr); |
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241 return le2me_32(tmp); |
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242 } |
14363 | 243 //#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,val) |
244 #define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,le2me_32(val)) | |
3996 | 245 #define OUTREGP(addr,val,mask) \ |
246 do { \ | |
247 unsigned int _tmp = INREG(addr); \ | |
248 _tmp &= (mask); \ | |
249 _tmp |= (val); \ | |
250 OUTREG(addr, _tmp); \ | |
251 } while (0) | |
252 | |
4666 | 253 static __inline__ uint32_t INPLL(uint32_t addr) |
254 { | |
255 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
256 return (INREG(CLOCK_CNTL_DATA)); | |
257 } | |
258 | |
259 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
260 OUTREG(CLOCK_CNTL_DATA, val) | |
261 #define OUTPLLP(addr,val,mask) \ | |
262 do { \ | |
263 unsigned int _tmp = INPLL(addr); \ | |
264 _tmp &= (mask); \ | |
265 _tmp |= (val); \ | |
266 OUTPLL(addr, _tmp); \ | |
267 } while (0) | |
268 | |
3996 | 269 static uint32_t radeon_vid_get_dbpp( void ) |
270 { | |
271 uint32_t dbpp,retval; | |
272 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
273 switch(dbpp) | |
274 { | |
275 case DST_8BPP: retval = 8; break; | |
276 case DST_15BPP: retval = 15; break; | |
277 case DST_16BPP: retval = 16; break; | |
278 case DST_24BPP: retval = 24; break; | |
279 default: retval=32; break; | |
280 } | |
281 return retval; | |
282 } | |
283 | |
284 static int radeon_is_dbl_scan( void ) | |
285 { | |
286 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
287 } | |
288 | |
289 static int radeon_is_interlace( void ) | |
290 { | |
291 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
292 } | |
293 | |
4666 | 294 static uint32_t radeon_get_xres( void ) |
295 { | |
296 /* FIXME: currently we extract that from CRTC!!!*/ | |
297 uint32_t xres,h_total; | |
298 h_total = INREG(CRTC_H_TOTAL_DISP); | |
299 xres = (h_total >> 16) & 0xffff; | |
300 return (xres + 1)*8; | |
301 } | |
302 | |
303 static uint32_t radeon_get_yres( void ) | |
304 { | |
305 /* FIXME: currently we extract that from CRTC!!!*/ | |
306 uint32_t yres,v_total; | |
307 v_total = INREG(CRTC_V_TOTAL_DISP); | |
308 yres = (v_total >> 16) & 0xffff; | |
309 return yres + 1; | |
310 } | |
311 | |
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312 /* get flat panel x resolution*/ |
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313 static uint32_t radeon_get_fp_xres( void ){ |
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314 uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16; |
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315 xres=(xres+1)*8; |
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316 return xres; |
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317 } |
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318 |
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319 /* get flat panel y resolution*/ |
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320 static uint32_t radeon_get_fp_yres( void ){ |
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321 uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12; |
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322 return yres+1; |
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323 } |
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324 |
4689 | 325 static void radeon_wait_vsync(void) |
326 { | |
327 int i; | |
328 | |
329 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
330 for (i = 0; i < 2000000; i++) | |
331 { | |
332 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
333 } | |
334 } | |
335 | |
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336 #ifdef RAGE128 |
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337 static void _radeon_engine_idle(void); |
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338 static void _radeon_fifo_wait(unsigned); |
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339 #define radeon_engine_idle() _radeon_engine_idle() |
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340 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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341 /* Flush all dirty data in the Pixel Cache to memory. */ |
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342 static __inline__ void radeon_engine_flush ( void ) |
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343 { |
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344 unsigned i; |
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345 |
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346 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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347 for (i = 0; i < 2000000; i++) { |
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348 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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349 } |
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350 } |
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351 |
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352 /* Reset graphics card to known state. */ |
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353 static void radeon_engine_reset( void ) |
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354 { |
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355 uint32_t clock_cntl_index; |
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356 uint32_t mclk_cntl; |
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357 uint32_t gen_reset_cntl; |
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358 |
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359 radeon_engine_flush(); |
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360 |
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361 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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362 mclk_cntl = INPLL(MCLK_CNTL); |
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363 |
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364 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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365 |
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366 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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367 |
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368 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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369 INREG(GEN_RESET_CNTL); |
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370 OUTREG(GEN_RESET_CNTL, |
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371 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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372 INREG(GEN_RESET_CNTL); |
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373 |
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374 OUTPLL(MCLK_CNTL, mclk_cntl); |
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375 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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376 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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377 } |
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378 #else |
4689 | 379 |
3996 | 380 static __inline__ void radeon_engine_flush ( void ) |
381 { | |
382 int i; | |
383 | |
384 /* initiate flush */ | |
385 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
386 ~RB2D_DC_FLUSH_ALL); | |
387 | |
388 for (i=0; i < 2000000; i++) { | |
389 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
390 break; | |
391 } | |
392 } | |
393 | |
4666 | 394 static void _radeon_engine_idle(void); |
395 static void _radeon_fifo_wait(unsigned); | |
396 #define radeon_engine_idle() _radeon_engine_idle() | |
397 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 398 |
4666 | 399 static void radeon_engine_reset( void ) |
3996 | 400 { |
4666 | 401 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
402 | |
403 radeon_engine_flush (); | |
404 | |
405 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
406 mclk_cntl = INPLL(MCLK_CNTL); | |
407 | |
408 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
409 FORCEON_MCLKA | | |
410 FORCEON_MCLKB | | |
411 FORCEON_YCLKA | | |
412 FORCEON_YCLKB | | |
413 FORCEON_MC | | |
414 FORCEON_AIC)); | |
415 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 416 |
4666 | 417 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
418 SOFT_RESET_CP | | |
419 SOFT_RESET_HI | | |
420 SOFT_RESET_SE | | |
421 SOFT_RESET_RE | | |
422 SOFT_RESET_PP | | |
423 SOFT_RESET_E2 | | |
424 SOFT_RESET_RB | | |
425 SOFT_RESET_HDP); | |
426 INREG(RBBM_SOFT_RESET); | |
427 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
428 ~(SOFT_RESET_CP | | |
429 SOFT_RESET_HI | | |
430 SOFT_RESET_SE | | |
431 SOFT_RESET_RE | | |
432 SOFT_RESET_PP | | |
433 SOFT_RESET_E2 | | |
434 SOFT_RESET_RB | | |
435 SOFT_RESET_HDP)); | |
436 INREG(RBBM_SOFT_RESET); | |
437 | |
438 OUTPLL(MCLK_CNTL, mclk_cntl); | |
439 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
440 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
441 | |
442 return; | |
3996 | 443 } |
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444 #endif |
4666 | 445 static void radeon_engine_restore( void ) |
3996 | 446 { |
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447 #ifndef RAGE128 |
4666 | 448 int pitch64; |
449 uint32_t xres,yres,bpp; | |
450 radeon_fifo_wait(1); | |
451 xres = radeon_get_xres(); | |
452 yres = radeon_get_yres(); | |
453 bpp = radeon_vid_get_dbpp(); | |
454 /* turn of all automatic flushing - we'll do it all */ | |
455 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
456 | |
457 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
458 | |
459 radeon_fifo_wait(1); | |
460 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
461 (pitch64 << 22)); | |
462 | |
463 radeon_fifo_wait(1); | |
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464 #if defined(WORDS_BIGENDIAN) |
9044 | 465 #ifdef RADEON |
466 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
467 #endif | |
4666 | 468 #else |
469 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
470 #endif | |
471 | |
472 radeon_fifo_wait(1); | |
473 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
474 | DEFAULT_SC_BOTTOM_MAX)); | |
475 radeon_fifo_wait(1); | |
476 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
477 | GMC_BRUSH_SOLID_COLOR | |
478 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 479 |
4666 | 480 radeon_fifo_wait(7); |
481 OUTREG(DST_LINE_START, 0); | |
482 OUTREG(DST_LINE_END, 0); | |
483 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
484 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
485 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
486 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
487 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
488 | |
489 radeon_engine_idle(); | |
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490 #endif |
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491 } |
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492 #ifdef RAGE128 |
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493 static void _radeon_fifo_wait (unsigned entries) |
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494 { |
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495 unsigned i; |
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496 |
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497 for(;;) |
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498 { |
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499 for (i=0; i<2000000; i++) |
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500 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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501 return; |
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502 radeon_engine_reset(); |
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503 radeon_engine_restore(); |
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504 } |
4666 | 505 } |
506 | |
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507 static void _radeon_engine_idle ( void ) |
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508 { |
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509 unsigned i; |
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510 |
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511 /* ensure FIFO is empty before waiting for idle */ |
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512 radeon_fifo_wait (64); |
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513 for(;;) |
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514 { |
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515 for (i=0; i<2000000; i++) { |
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516 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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517 radeon_engine_flush (); |
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518 return; |
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519 } |
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520 } |
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521 radeon_engine_reset(); |
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522 radeon_engine_restore(); |
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523 } |
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524 } |
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525 #else |
4666 | 526 static void _radeon_fifo_wait (unsigned entries) |
527 { | |
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528 unsigned i; |
3996 | 529 |
4666 | 530 for(;;) |
531 { | |
532 for (i=0; i<2000000; i++) | |
533 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
534 return; | |
535 radeon_engine_reset(); | |
536 radeon_engine_restore(); | |
537 } | |
538 } | |
539 static void _radeon_engine_idle ( void ) | |
540 { | |
541 int i; | |
542 | |
543 /* ensure FIFO is empty before waiting for idle */ | |
544 radeon_fifo_wait (64); | |
545 for(;;) | |
546 { | |
3996 | 547 for (i=0; i<2000000; i++) { |
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548 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 549 radeon_engine_flush (); |
550 return; | |
551 } | |
552 } | |
4666 | 553 radeon_engine_reset(); |
554 radeon_engine_restore(); | |
555 } | |
3996 | 556 } |
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557 #endif |
3996 | 558 |
559 #ifndef RAGE128 | |
560 /* Reference color space transform data */ | |
561 typedef struct tagREF_TRANSFORM | |
562 { | |
563 float RefLuma; | |
564 float RefRCb; | |
565 float RefRCr; | |
566 float RefGCb; | |
567 float RefGCr; | |
568 float RefBCb; | |
569 float RefBCr; | |
570 } REF_TRANSFORM; | |
571 | |
572 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
573 REF_TRANSFORM trans[2] = | |
574 { | |
575 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
576 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
577 }; | |
578 /**************************************************************************** | |
579 * SetTransform * | |
580 * Function: Calculates and sets color space transform from supplied * | |
581 * reference transform, gamma, brightness, contrast, hue and * | |
582 * saturation. * | |
583 * Inputs: bright - brightness * | |
584 * cont - contrast * | |
585 * sat - saturation * | |
586 * hue - hue * | |
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587 * red_intensity - intense of red component * |
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588 * green_intensity - intense of green component * |
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589 * blue_intensity - intense of blue component * |
3996 | 590 * ref - index to the table of refernce transforms * |
591 * Outputs: NONE * | |
592 ****************************************************************************/ | |
593 | |
594 static void radeon_set_transform(float bright, float cont, float sat, | |
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595 float hue, float red_intensity, |
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596 float green_intensity,float blue_intensity, |
4284 | 597 unsigned ref) |
3996 | 598 { |
599 float OvHueSin, OvHueCos; | |
600 float CAdjLuma, CAdjOff; | |
4284 | 601 float RedAdj,GreenAdj,BlueAdj; |
3996 | 602 float CAdjRCb, CAdjRCr; |
603 float CAdjGCb, CAdjGCr; | |
604 float CAdjBCb, CAdjBCr; | |
605 float OvLuma, OvROff, OvGOff, OvBOff; | |
606 float OvRCb, OvRCr; | |
607 float OvGCb, OvGCr; | |
608 float OvBCb, OvBCr; | |
609 float Loff = 64.0; | |
610 float Coff = 512.0f; | |
611 | |
612 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
613 uint32_t dwOvRCb, dwOvRCr; | |
614 uint32_t dwOvGCb, dwOvGCr; | |
615 uint32_t dwOvBCb, dwOvBCr; | |
616 | |
617 if (ref >= 2) return; | |
618 | |
619 OvHueSin = sin((double)hue); | |
620 OvHueCos = cos((double)hue); | |
621 | |
622 CAdjLuma = cont * trans[ref].RefLuma; | |
623 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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624 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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625 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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626 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 627 |
628 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
629 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
630 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
631 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
632 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
633 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
634 | |
635 #if 0 /* default constants */ | |
636 CAdjLuma = 1.16455078125; | |
637 | |
638 CAdjRCb = 0.0; | |
639 CAdjRCr = 1.59619140625; | |
640 CAdjGCb = -0.39111328125; | |
641 CAdjGCr = -0.8125; | |
642 CAdjBCb = 2.01708984375; | |
643 CAdjBCr = 0; | |
644 #endif | |
645 OvLuma = CAdjLuma; | |
646 OvRCb = CAdjRCb; | |
647 OvRCr = CAdjRCr; | |
648 OvGCb = CAdjGCb; | |
649 OvGCr = CAdjGCr; | |
650 OvBCb = CAdjBCb; | |
651 OvBCr = CAdjBCr; | |
4284 | 652 OvROff = RedAdj + CAdjOff - |
3996 | 653 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 654 OvGOff = GreenAdj + CAdjOff - |
3996 | 655 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 656 OvBOff = BlueAdj + CAdjOff - |
3996 | 657 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
658 #if 0 /* default constants */ | |
659 OvROff = -888.5; | |
660 OvGOff = 545; | |
661 OvBOff = -1104; | |
662 #endif | |
663 | |
664 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
665 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
666 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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667 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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668 as in Radeon is a lie */ |
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669 #if 0 |
8855 | 670 if(RadeonFamily == 100) |
3996 | 671 { |
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672 #endif |
3996 | 673 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
674 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
675 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
676 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
677 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
678 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
679 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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680 #if 0 |
3996 | 681 } |
682 else | |
683 { | |
684 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
685 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
686 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
687 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
688 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
689 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
690 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
691 } | |
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692 #endif |
3996 | 693 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
694 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
695 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
696 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
697 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
698 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
699 } | |
700 | |
701 /* Gamma curve definition */ | |
702 typedef struct | |
703 { | |
704 unsigned int gammaReg; | |
705 unsigned int gammaSlope; | |
706 unsigned int gammaOffset; | |
707 }GAMMA_SETTINGS; | |
708 | |
709 /* Recommended gamma curve parameters */ | |
710 GAMMA_SETTINGS r200_def_gamma[18] = | |
711 { | |
712 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
713 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
714 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
715 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
716 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
717 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
718 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
719 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
720 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
721 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
722 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
723 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
724 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
725 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
726 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
727 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
728 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
729 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
730 }; | |
731 | |
732 GAMMA_SETTINGS r100_def_gamma[6] = | |
733 { | |
734 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
735 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
736 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
737 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
738 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
739 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
740 }; | |
741 | |
742 static void make_default_gamma_correction( void ) | |
743 { | |
744 size_t i; | |
8855 | 745 if(RadeonFamily == 100) { |
3996 | 746 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
747 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
748 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
749 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
750 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
751 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
752 for(i=0; i<6; i++){ | |
753 OUTREG(r100_def_gamma[i].gammaReg, | |
754 (r100_def_gamma[i].gammaSlope<<16) | | |
755 r100_def_gamma[i].gammaOffset); | |
756 } | |
757 } | |
758 else{ | |
759 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
760 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
761 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
762 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
763 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
764 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
765 | |
766 /* Default Gamma, | |
767 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
768 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
769 for(i=0; i<18; i++){ | |
770 OUTREG(r200_def_gamma[i].gammaReg, | |
771 (r200_def_gamma[i].gammaSlope<<16) | | |
772 r200_def_gamma[i].gammaOffset); | |
773 } | |
774 } | |
775 } | |
776 #endif | |
777 | |
778 static void radeon_vid_make_default(void) | |
779 { | |
780 #ifdef RAGE128 | |
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781 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 782 #else |
783 make_default_gamma_correction(); | |
784 #endif | |
785 besr.deinterlace_pattern = 0x900AAAAA; | |
786 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
787 besr.deinterlace_on=1; | |
788 besr.double_buff=1; | |
4869 | 789 besr.ckey_on=0; |
790 besr.graphics_key_msk=0; | |
791 besr.graphics_key_clr=0; | |
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792 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 793 } |
794 | |
795 | |
796 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
797 | |
4107 | 798 static unsigned short ati_card_ids[] = |
3996 | 799 { |
800 #ifdef RAGE128 | |
801 /* | |
802 This driver should be compatible with Rage128 (pro) chips. | |
803 (include adaptive deinterlacing!!!). | |
804 Moreover: the same logic can be used with Mach64 chips. | |
805 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
806 but they are incompatible by i/o ports. So if enthusiasts will want | |
807 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
808 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
809 fourccs (422 and 420 formats only). | |
810 */ | |
811 /* Rage128 Pro GL */ | |
4107 | 812 DEVICE_ATI_RAGE_128_PA_PRO, |
813 DEVICE_ATI_RAGE_128_PB_PRO, | |
814 DEVICE_ATI_RAGE_128_PC_PRO, | |
815 DEVICE_ATI_RAGE_128_PD_PRO, | |
816 DEVICE_ATI_RAGE_128_PE_PRO, | |
817 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 818 /* Rage128 Pro VR */ |
4107 | 819 DEVICE_ATI_RAGE_128_PG_PRO, |
820 DEVICE_ATI_RAGE_128_PH_PRO, | |
821 DEVICE_ATI_RAGE_128_PI_PRO, | |
822 DEVICE_ATI_RAGE_128_PJ_PRO, | |
823 DEVICE_ATI_RAGE_128_PK_PRO, | |
824 DEVICE_ATI_RAGE_128_PL_PRO, | |
825 DEVICE_ATI_RAGE_128_PM_PRO, | |
826 DEVICE_ATI_RAGE_128_PN_PRO, | |
827 DEVICE_ATI_RAGE_128_PO_PRO, | |
828 DEVICE_ATI_RAGE_128_PP_PRO, | |
829 DEVICE_ATI_RAGE_128_PQ_PRO, | |
830 DEVICE_ATI_RAGE_128_PR_PRO, | |
831 DEVICE_ATI_RAGE_128_PS_PRO, | |
832 DEVICE_ATI_RAGE_128_PT_PRO, | |
833 DEVICE_ATI_RAGE_128_PU_PRO, | |
834 DEVICE_ATI_RAGE_128_PV_PRO, | |
835 DEVICE_ATI_RAGE_128_PW_PRO, | |
836 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 837 /* Rage128 GL */ |
4107 | 838 DEVICE_ATI_RAGE_128_RE_SG, |
839 DEVICE_ATI_RAGE_128_RF_SG, | |
840 DEVICE_ATI_RAGE_128_RG, | |
841 DEVICE_ATI_RAGE_128_RK_VR, | |
842 DEVICE_ATI_RAGE_128_RL_VR, | |
843 DEVICE_ATI_RAGE_128_SE_4X, | |
844 DEVICE_ATI_RAGE_128_SF_4X, | |
845 DEVICE_ATI_RAGE_128_SG_4X, | |
8854 | 846 DEVICE_ATI_RAGE_128_SH, |
4107 | 847 DEVICE_ATI_RAGE_128_SK_4X, |
848 DEVICE_ATI_RAGE_128_SL_4X, | |
849 DEVICE_ATI_RAGE_128_SM_4X, | |
8854 | 850 DEVICE_ATI_RAGE_128_4X, |
4107 | 851 DEVICE_ATI_RAGE_128_PRO, |
852 DEVICE_ATI_RAGE_128_PRO2, | |
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853 DEVICE_ATI_RAGE_128_PRO3, |
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854 /* these seem to be based on rage 128 instead of mach64 */ |
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855 DEVICE_ATI_RAGE_MOBILITY_M3, |
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856 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 857 #else |
858 /* Radeons (indeed: Rage 256 Pro ;) */ | |
8855 | 859 DEVICE_ATI_RADEON_R100_QD, |
860 DEVICE_ATI_RADEON_R100_QE, | |
861 DEVICE_ATI_RADEON_R100_QF, | |
862 DEVICE_ATI_RADEON_R100_QG, | |
863 DEVICE_ATI_RADEON_VE_QY, | |
864 DEVICE_ATI_RADEON_VE_QZ, | |
8854 | 865 DEVICE_ATI_RADEON_MOBILITY_M7, |
866 DEVICE_ATI_RADEON_MOBILITY_M72, | |
4107 | 867 DEVICE_ATI_RADEON_MOBILITY_M6, |
868 DEVICE_ATI_RADEON_MOBILITY_M62, | |
10332 | 869 DEVICE_ATI_RADEON_MOBILITY_U1, |
8855 | 870 DEVICE_ATI_RADEON_R200_BB, |
871 DEVICE_ATI_RADEON_R200_QH, | |
872 DEVICE_ATI_RADEON_R200_QI, | |
873 DEVICE_ATI_RADEON_R200_QJ, | |
874 DEVICE_ATI_RADEON_R200_QK, | |
8854 | 875 DEVICE_ATI_RADEON_R200_QL, |
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876 DEVICE_ATI_RADEON_R200_QM, |
8855 | 877 DEVICE_ATI_RADEON_R200_QH2, |
878 DEVICE_ATI_RADEON_R200_QI2, | |
879 DEVICE_ATI_RADEON_R200_QJ2, | |
880 DEVICE_ATI_RADEON_R200_QK2, | |
8854 | 881 DEVICE_ATI_RADEON_RV200_QW, |
8855 | 882 DEVICE_ATI_RADEON_RV200_QX, |
883 DEVICE_ATI_RADEON_R250_ID, | |
884 DEVICE_ATI_RADEON_R250_IE, | |
885 DEVICE_ATI_RADEON_R250_IF, | |
886 DEVICE_ATI_RADEON_R250_IG, | |
887 DEVICE_ATI_RADEON_R250_LD, | |
888 DEVICE_ATI_RADEON_R250_LE, | |
889 DEVICE_ATI_RADEON_R250_LF, | |
890 DEVICE_ATI_RADEON_R250_LG, | |
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891 DEVICE_ATI_RV370_5B60_RADEON, |
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892 DEVICE_ATI_RV250_5C61_RADEON, |
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893 DEVICE_ATI_RV250_5C63_RADEON, |
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894 DEVICE_ATI_RV280_RADEON_9200, |
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895 DEVICE_ATI_RV280_RADEON_92002, |
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896 DEVICE_ATI_RV280_RADEON_92003, |
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897 DEVICE_ATI_RV280_RADEON_92004, |
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898 DEVICE_ATI_RV280_RADEON_92005, |
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899 DEVICE_ATI_RV280_RADEON_92006, |
8855 | 900 DEVICE_ATI_RADEON_R300_ND, |
901 DEVICE_ATI_RADEON_R300_NE, | |
902 DEVICE_ATI_RADEON_R300_NF, | |
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903 DEVICE_ATI_RADEON_R300_NG, |
12361
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904 DEVICE_ATI_RADEON_R300_AE, |
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905 DEVICE_ATI_RADEON_R300_AF, |
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906 DEVICE_ATI_RADEON_RV350_AP, |
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907 DEVICE_ATI_RADEON_RV350_AR, |
17350 | 908 DEVICE_ATI_RADEON_RV350_BK, |
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909 DEVICE_ATI_RADEON_R350_AH, |
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910 DEVICE_ATI_RADEON_R350_AI, |
12060 | 911 DEVICE_ATI_RADEON_R350_NH, |
12459 | 912 DEVICE_ATI_RADEON_R360_NJ, |
12060 | 913 DEVICE_ATI_RV350_MOBILITY_RADEON, |
914 DEVICE_ATI_RV350_MOBILITY_RADEON2 | |
3996 | 915 #endif |
916 }; | |
917 | |
918 static int find_chip(unsigned chip_id) | |
919 { | |
920 unsigned i; | |
4107 | 921 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 922 { |
4107 | 923 if(chip_id == ati_card_ids[i]) return i; |
3996 | 924 } |
925 return -1; | |
926 } | |
927 | |
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928 static pciinfo_t pci_info; |
3996 | 929 static int probed=0; |
930 | |
931 vidix_capability_t def_cap = | |
932 { | |
933 #ifdef RAGE128 | |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
934 "BES driver for Rage128 cards", |
3996 | 935 #else |
8564
e1329263197b
fixed a 10l, some cosmetics, and initial ppc (bigendian) support
alex
parents:
8562
diff
changeset
|
936 "BES driver for Radeon cards", |
3996 | 937 #endif |
4327 | 938 "Nick Kurshev", |
3996 | 939 TYPE_OUTPUT | TYPE_FX, |
4191 | 940 { 0, 0, 0, 0 }, |
4282 | 941 2048, |
942 2048, | |
3996 | 943 4, |
944 4, | |
945 -1, | |
4264 | 946 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 947 VENDOR_ATI, |
3996 | 948 0, |
949 { 0, 0, 0, 0} | |
950 }; | |
951 | |
12286 | 952 #ifdef HAVE_X11 |
19066
26a30496ec96
marks several function without a prototype which arent used outside its sourcefile as static, Patch by Stefan Huehner - stefan AT huehner-org
reynaldo
parents:
17566
diff
changeset
|
953 static void probe_fireGL_driver(void) { |
12286 | 954 Display *dp = XOpenDisplay ((void*)0); |
955 int n = 0; | |
12466
b5e7d2464c00
segfault fix by Jarrod Johnson <jbj-zl@ura.dnsalias.org>
diego
parents:
12459
diff
changeset
|
956 char **extlist; |
b5e7d2464c00
segfault fix by Jarrod Johnson <jbj-zl@ura.dnsalias.org>
diego
parents:
12459
diff
changeset
|
957 if (dp==NULL) { |
b5e7d2464c00
segfault fix by Jarrod Johnson <jbj-zl@ura.dnsalias.org>
diego
parents:
12459
diff
changeset
|
958 return; |
b5e7d2464c00
segfault fix by Jarrod Johnson <jbj-zl@ura.dnsalias.org>
diego
parents:
12459
diff
changeset
|
959 } |
b5e7d2464c00
segfault fix by Jarrod Johnson <jbj-zl@ura.dnsalias.org>
diego
parents:
12459
diff
changeset
|
960 extlist = XListExtensions (dp, &n); |
12286 | 961 XCloseDisplay (dp); |
962 if (extlist) { | |
963 int i; | |
964 int ext_fgl = 0, ext_fglrx = 0; | |
965 for (i = 0; i < n; i++) { | |
966 if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1; | |
967 if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1; | |
968 } | |
969 if (ext_fgl) { | |
970 printf(RADEON_MSG" ATI FireGl driver detected"); | |
971 firegl_shift = 0x500000; | |
972 if (!ext_fglrx) { | |
973 printf(", but DRI seems not to be activated\n"); | |
974 printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!"); | |
975 } | |
976 printf("\n"); | |
977 } | |
978 } | |
979 } | |
980 #endif | |
3996 | 981 |
4191 | 982 int vixProbe( int verbose,int force ) |
3996 | 983 { |
984 pciinfo_t lst[MAX_PCI_DEVICES]; | |
985 unsigned i,num_pci; | |
986 int err; | |
4030 | 987 __verbose = verbose; |
3996 | 988 err = pci_scan(lst,&num_pci); |
989 if(err) | |
990 { | |
11678
972d1998bde9
occured --> occurred typo patch by Clinton Roy <croy@dstc.edu.au>
diego
parents:
11658
diff
changeset
|
991 printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err)); |
3996 | 992 return err; |
993 } | |
994 else | |
995 { | |
996 err = ENXIO; | |
997 for(i=0;i<num_pci;i++) | |
998 { | |
4107 | 999 if(lst[i].vendor == VENDOR_ATI) |
3996 | 1000 { |
1001 int idx; | |
4191 | 1002 const char *dname; |
3996 | 1003 idx = find_chip(lst[i].device); |
4191 | 1004 if(idx == -1 && force == PROBE_NORMAL) continue; |
1005 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
1006 dname = dname ? dname : "Unknown chip"; | |
1007 printf(RADEON_MSG" Found chip: %s\n",dname); | |
9767
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
1008 if ((lst[i].command & PCI_COMMAND_IO) == 0) |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
1009 { |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
1010 printf("[radeon] Device is disabled, ignoring\n"); |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
1011 continue; |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
1012 } |
3996 | 1013 #ifndef RAGE128 |
4191 | 1014 if(idx != -1) |
12286 | 1015 #ifdef HAVE_X11 |
1016 probe_fireGL_driver(); | |
1017 #endif | |
8855 | 1018 { |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1019 switch(ati_card_ids[idx]) { |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1020 /* Original radeon */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1021 case DEVICE_ATI_RADEON_R100_QD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1022 case DEVICE_ATI_RADEON_R100_QE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1023 case DEVICE_ATI_RADEON_R100_QF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1024 case DEVICE_ATI_RADEON_R100_QG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1025 RadeonFamily = 100; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1026 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1027 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1028 /* Radeon VE / Radeon Mobility */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1029 case DEVICE_ATI_RADEON_VE_QY: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1030 case DEVICE_ATI_RADEON_VE_QZ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1031 case DEVICE_ATI_RADEON_MOBILITY_M6: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1032 case DEVICE_ATI_RADEON_MOBILITY_M62: |
10332 | 1033 case DEVICE_ATI_RADEON_MOBILITY_U1: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1034 RadeonFamily = 120; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1035 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1036 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1037 /* Radeon 7500 / Radeon Mobility 7500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1038 case DEVICE_ATI_RADEON_RV200_QW: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1039 case DEVICE_ATI_RADEON_RV200_QX: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1040 case DEVICE_ATI_RADEON_MOBILITY_M7: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1041 case DEVICE_ATI_RADEON_MOBILITY_M72: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1042 RadeonFamily = 150; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1043 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1044 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1045 /* Radeon 8500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1046 case DEVICE_ATI_RADEON_R200_BB: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1047 case DEVICE_ATI_RADEON_R200_QH: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1048 case DEVICE_ATI_RADEON_R200_QI: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1049 case DEVICE_ATI_RADEON_R200_QJ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1050 case DEVICE_ATI_RADEON_R200_QK: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1051 case DEVICE_ATI_RADEON_R200_QL: |
14195
1061d4dea7b7
Radeon R200 QM (Radeon 9100) support patch by Simone <beniamino.scanzoni at fastwebnet.it>
faust3
parents:
13594
diff
changeset
|
1052 case DEVICE_ATI_RADEON_R200_QM: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1053 case DEVICE_ATI_RADEON_R200_QH2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1054 case DEVICE_ATI_RADEON_R200_QI2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1055 case DEVICE_ATI_RADEON_R200_QJ2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1056 case DEVICE_ATI_RADEON_R200_QK2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1057 RadeonFamily = 200; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1058 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1059 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1060 /* Radeon 9000 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1061 case DEVICE_ATI_RADEON_R250_ID: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1062 case DEVICE_ATI_RADEON_R250_IE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1063 case DEVICE_ATI_RADEON_R250_IF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1064 case DEVICE_ATI_RADEON_R250_IG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1065 case DEVICE_ATI_RADEON_R250_LD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1066 case DEVICE_ATI_RADEON_R250_LE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1067 case DEVICE_ATI_RADEON_R250_LF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1068 case DEVICE_ATI_RADEON_R250_LG: |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1069 case DEVICE_ATI_RV250_5C61_RADEON: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1070 case DEVICE_ATI_RV250_5C63_RADEON: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1071 RadeonFamily = 250; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1072 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1073 |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1074 /* Radeon 9200 */ |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1075 case DEVICE_ATI_RV280_RADEON_9200: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1076 case DEVICE_ATI_RV280_RADEON_92002: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1077 case DEVICE_ATI_RV280_RADEON_92003: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1078 case DEVICE_ATI_RV280_RADEON_92004: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1079 case DEVICE_ATI_RV280_RADEON_92005: |
15108
16bc84938c4b
add support for one more radeon 9200 model (the one included in the Mac Mini)
aurel
parents:
14363
diff
changeset
|
1080 case DEVICE_ATI_RV280_RADEON_92006: |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1081 RadeonFamily = 280; |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1082 break; |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1083 |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1084 /* Radeon 9700 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1085 case DEVICE_ATI_RADEON_R300_ND: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1086 case DEVICE_ATI_RADEON_R300_NE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1087 case DEVICE_ATI_RADEON_R300_NF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1088 case DEVICE_ATI_RADEON_R300_NG: |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1089 case DEVICE_ATI_RADEON_R300_AE: |
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1090 case DEVICE_ATI_RADEON_R300_AF: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1091 RadeonFamily = 300; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1092 break; |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1093 |
11658
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
wight
parents:
11371
diff
changeset
|
1094 /* Radeon 9600/9800 */ |
15920
e5bc2812c4a0
radeon x300 support patch by Christophe Preaud <cpreaud at free.fr>
faust3
parents:
15109
diff
changeset
|
1095 case DEVICE_ATI_RV370_5B60_RADEON: |
11658
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
wight
parents:
11371
diff
changeset
|
1096 case DEVICE_ATI_RADEON_RV350_AP: |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1097 case DEVICE_ATI_RADEON_RV350_AR: |
17350 | 1098 case DEVICE_ATI_RADEON_RV350_BK: |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1099 case DEVICE_ATI_RADEON_R350_NH: |
12454
83a18b230e8c
Add support for a few more Radeons, patch by Nyk Tarr.
diego
parents:
12361
diff
changeset
|
1100 case DEVICE_ATI_RADEON_R350_AH: |
83a18b230e8c
Add support for a few more Radeons, patch by Nyk Tarr.
diego
parents:
12361
diff
changeset
|
1101 case DEVICE_ATI_RADEON_R350_AI: |
12459 | 1102 case DEVICE_ATI_RADEON_R360_NJ: |
12060 | 1103 case DEVICE_ATI_RV350_MOBILITY_RADEON: |
1104 case DEVICE_ATI_RV350_MOBILITY_RADEON2: | |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1105 RadeonFamily = 350; |
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1106 break; |
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1107 |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1108 default: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1109 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1110 } |
8855 | 1111 } |
3996 | 1112 #endif |
4193 | 1113 if(force > PROBE_NORMAL) |
1114 { | |
1115 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
1116 if(idx == -1) | |
1117 #ifdef RAGE128 | |
4373 | 1118 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 1119 #else |
4373 | 1120 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 1121 #endif |
1122 } | |
4191 | 1123 def_cap.device_id = lst[i].device; |
3996 | 1124 err = 0; |
1125 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
1126 probed=1; | |
1127 break; | |
1128 } | |
1129 } | |
1130 } | |
1131 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
1132 return err; | |
1133 } | |
1134 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1135 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1136 |
3996 | 1137 int vixInit( void ) |
1138 { | |
4477 | 1139 int err; |
4012 | 1140 if(!probed) |
1141 { | |
1142 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
1143 return EINTR; | |
1144 } | |
1145 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 1146 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
1147 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1148 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
8942 | 1149 #ifdef RADEON |
1150 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ | |
1151 if (radeon_ram_size == 0 && | |
1152 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || | |
1153 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) | |
1154 { | |
1155 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); | |
1156 radeon_ram_size = 8192*1024; | |
1157 } | |
9240
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1158 #else |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1159 /* Rage Mobility (rage128) also has memsize bug */ |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1160 if (radeon_ram_size == 0 && |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1161 (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || |
15109
2a5d9229b60d
override memory size detection bug on rage 128 RL/VR
aurel
parents:
15108
diff
changeset
|
1162 def_cap.device_id == DEVICE_ATI_RAGE_128_RL_VR || |
9240
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1163 def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1164 { |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1165 printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1166 radeon_ram_size = 8192*1024; |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1167 } |
8942 | 1168 #endif |
12072 | 1169 #ifdef WIN32 |
1170 if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024; | |
1171 #endif | |
3996 | 1172 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
1173 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 1174 radeon_vid_make_default(); |
1175 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 1176 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
1177 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1178 |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1179 radeon_fifo_wait(3); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1180 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1181 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1182 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1183 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1184 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1185 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1186 |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1187 #ifdef RADEON |
8859 | 1188 switch(RadeonFamily) |
1189 { | |
1190 case 100: | |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1191 case 120: |
8859 | 1192 case 150: |
1193 case 250: | |
12642 | 1194 case 280: |
8859 | 1195 is_shift_required=1; |
1196 break; | |
1197 default: | |
1198 break; | |
1199 } | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
1200 #endif |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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diff
changeset
|
1201 |
9044 | 1202 /* XXX: hack, but it works for me (tm) */ |
13167
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
12642
diff
changeset
|
1203 #ifdef WORDS_BIGENDIAN |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
changeset
|
1204 #if defined(RAGE128) |
9044 | 1205 /* code from gatos */ |
1206 { | |
1207 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); | |
1208 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & | |
1209 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); | |
1210 | |
1211 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, | |
1212 // INREG(CONFIG_CNTL)); | |
1213 } | |
13167
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1214 #else |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1215 /*code from radeon_video.c*/ |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
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diff
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|
1216 { |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
changeset
|
1217 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1218 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
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diff
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|
1219 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
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|
1220 */ |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1221 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1222 | RADEON_NONSURF_AP0_SWP_16BPP)); |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1223 |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
changeset
|
1224 /* |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1225 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
12642
diff
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|
1226 & ~RADEON_NONSURF_AP0_SWP_16BPP); |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
changeset
|
1227 */ |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
12642
diff
changeset
|
1228 } |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
changeset
|
1229 #endif |
9044 | 1230 #endif |
1231 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1232 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1233 return 0; |
1234 } | |
1235 | |
1236 void vixDestroy( void ) | |
1237 { | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1238 /* remove colorkeying */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1239 radeon_fifo_wait(3); |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1240 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1241 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
1242 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1243 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1244 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
1245 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1246 |
13167
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
12642
diff
changeset
|
1247 #ifdef WORDS_BIGENDIAN |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
12642
diff
changeset
|
1248 #if defined(RAGE128) |
9044 | 1249 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); |
1250 // printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, | |
1251 // INREG(CONFIG_CNTL)); | |
13167
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
12642
diff
changeset
|
1252 #else |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
changeset
|
1253 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL); |
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
parents:
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diff
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|
1254 #endif |
9044 | 1255 #endif |
1256 | |
3996 | 1257 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 1258 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 1259 } |
1260 | |
1261 int vixGetCapability(vidix_capability_t *to) | |
1262 { | |
1263 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1264 return 0; | |
1265 } | |
1266 | |
6483 | 1267 /* |
1268 Full list of fourcc which are supported by Win2K redeon driver: | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
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diff
changeset
|
1269 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1270 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1271 */ | |
3996 | 1272 uint32_t supported_fourcc[] = |
1273 { | |
6483 | 1274 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1275 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1276 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1277 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1278 IMGFMT_RGB16, IMGFMT_BGR16, |
1279 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1280 }; |
1281 | |
6483 | 1282 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1283 { |
6483 | 1284 unsigned int i; |
3996 | 1285 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1286 { | |
1287 if(fourcc==supported_fourcc[i]) return 1; | |
1288 } | |
1289 return 0; | |
1290 } | |
1291 | |
1292 int vixQueryFourcc(vidix_fourcc_t *to) | |
1293 { | |
1294 if(is_supported_fourcc(to->fourcc)) | |
1295 { | |
1296 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1297 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1298 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1299 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1300 VID_DEPTH_32BPP; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
changeset
|
1301 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1302 return 0; |
1303 } | |
4015 | 1304 else to->depth = to->flags = 0; |
3996 | 1305 return ENOSYS; |
1306 } | |
1307 | |
1308 static void radeon_vid_dump_regs( void ) | |
1309 { | |
1310 size_t i; | |
4015 | 1311 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1312 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1313 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1314 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1315 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1316 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
13594
acfe017b6195
correct scaling when the screen resolution is smaller than the flat panel resolution
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parents:
13337
diff
changeset
|
1317 printf(RADEON_MSG"flatpanel size: %ux%u\n",radeon_get_fp_xres(),radeon_get_fp_yres()); |
4015 | 1318 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1319 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1320 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1321 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1322 } |
1323 | |
1324 static void radeon_vid_stop_video( void ) | |
1325 { | |
1326 radeon_engine_idle(); | |
1327 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1328 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1329 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1330 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
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a2710e35e2cc
Reduce flickering on window movement (from Christophe Badina)
arpi
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|
1331 #ifdef RADEON |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1332 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); |
8857
a2710e35e2cc
Reduce flickering on window movement (from Christophe Badina)
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parents:
8856
diff
changeset
|
1333 #else |
3996 | 1334 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
8857
a2710e35e2cc
Reduce flickering on window movement (from Christophe Badina)
arpi
parents:
8856
diff
changeset
|
1335 #endif |
3996 | 1336 OUTREG(OV0_TEST, 0); |
1337 } | |
1338 | |
1339 static void radeon_vid_display_video( void ) | |
1340 { | |
1341 int bes_flags; | |
13337 | 1342 /** workaround for Xorg-6.8 not saving the surface registers on bigendian architectures */ |
13335
6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
faust3
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13167
diff
changeset
|
1343 #ifdef WORDS_BIGENDIAN |
6c002b4462ae
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faust3
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|
1344 #if defined(RAGE128) |
6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
faust3
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diff
changeset
|
1345 /* code from gatos */ |
6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
faust3
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changeset
|
1346 { |
6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
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diff
changeset
|
1347 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); |
6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
faust3
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changeset
|
1348 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & |
6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
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1349 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); |
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1350 |
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1351 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, |
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1352 // INREG(CONFIG_CNTL)); |
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1353 } |
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1354 #else |
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1355 /*code from radeon_video.c*/ |
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1356 { |
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1357 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); |
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1358 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | |
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1359 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); |
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1360 */ |
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1361 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP |
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1362 | RADEON_NONSURF_AP0_SWP_16BPP)); |
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1363 |
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1364 /* |
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1365 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) |
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1366 & ~RADEON_NONSURF_AP0_SWP_16BPP); |
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1367 */ |
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1368 } |
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1369 #endif |
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1370 #endif |
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1371 |
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1372 |
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1373 |
3996 | 1374 radeon_fifo_wait(2); |
1375 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1376 radeon_engine_idle(); | |
1377 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1378 radeon_fifo_wait(15); | |
4666 | 1379 |
1380 /* Shutdown capturing */ | |
1381 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1382 OUTREG(CAP0_TRIG_CNTL, 0); | |
1383 | |
4689 | 1384 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1385 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1386 |
3996 | 1387 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1388 | |
4611 | 1389 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1390 #ifdef RAGE128 |
7493 | 1391 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1392 (((besr.saturation*31+31000)/2000) << 8) | | |
1393 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1394 #endif |
1395 radeon_fifo_wait(2); | |
4869 | 1396 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1397 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1398 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1399 |
1400 OUTREG(OV0_H_INC, besr.h_inc); | |
1401 OUTREG(OV0_STEP_BY, besr.step_by); | |
1402 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1403 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1404 OUTREG(OV0_V_INC, besr.v_inc); | |
1405 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1406 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1407 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1408 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1409 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1410 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1411 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1412 #ifdef RADEON | |
1413 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1414 #endif | |
4930 | 1415 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1416 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1417 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1418 radeon_fifo_wait(9); |
4930 | 1419 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1420 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1421 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1422 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1423 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1424 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1425 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1426 | |
6678 | 1427 #ifdef RADEON |
1428 bes_flags = SCALER_ENABLE | | |
1429 SCALER_SMART_SWITCH; | |
1430 // SCALER_HORZ_PICK_NEAREST | | |
1431 // SCALER_VERT_PICK_NEAREST | | |
1432 #endif | |
3996 | 1433 bes_flags = SCALER_ENABLE | |
1434 SCALER_SMART_SWITCH | | |
1435 SCALER_Y2R_TEMP | | |
1436 SCALER_PIX_EXPAND; | |
1437 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1438 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1439 #ifdef RAGE128 | |
1440 bes_flags |= SCALER_BURST_PER_PLANE; | |
1441 #endif | |
1442 switch(besr.fourcc) | |
1443 { | |
1444 case IMGFMT_RGB15: | |
1445 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1446 case IMGFMT_RGB16: |
3996 | 1447 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1448 /* |
3996 | 1449 case IMGFMT_RGB24: |
1450 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1451 */ |
3996 | 1452 case IMGFMT_RGB32: |
1453 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1454 /* 4:1:0 */ |
3996 | 1455 case IMGFMT_IF09: |
1456 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1457 /* 4:0:0 */ |
1458 case IMGFMT_Y800: | |
1459 case IMGFMT_Y8: | |
3996 | 1460 /* 4:2:0 */ |
1461 case IMGFMT_IYUV: | |
1462 case IMGFMT_I420: | |
6483 | 1463 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1464 /* 4:2:2 */ |
4455 | 1465 case IMGFMT_YVYU: |
3996 | 1466 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1467 case IMGFMT_YUY2: | |
1468 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1469 } | |
1470 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1471 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1472 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1473 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1474 } |
1475 | |
4456 | 1476 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1477 { |
4456 | 1478 unsigned pitch,spy,spv,spu; |
1479 spy = spv = spu = 0; | |
1480 switch(spitch->y) | |
1481 { | |
1482 case 16: | |
1483 case 32: | |
1484 case 64: | |
1485 case 128: | |
1486 case 256: spy = spitch->y; break; | |
1487 default: break; | |
1488 } | |
1489 switch(spitch->u) | |
1490 { | |
1491 case 16: | |
1492 case 32: | |
1493 case 64: | |
1494 case 128: | |
1495 case 256: spu = spitch->u; break; | |
1496 default: break; | |
1497 } | |
1498 switch(spitch->v) | |
1499 { | |
1500 case 16: | |
1501 case 32: | |
1502 case 64: | |
1503 case 128: | |
1504 case 256: spv = spitch->v; break; | |
1505 default: break; | |
1506 } | |
4009 | 1507 switch(fourcc) |
1508 { | |
1509 /* 4:2:0 */ | |
1510 case IMGFMT_IYUV: | |
1511 case IMGFMT_YV12: | |
4456 | 1512 case IMGFMT_I420: |
1513 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1514 else pitch = 32; | |
1515 break; | |
6483 | 1516 /* 4:1:0 */ |
1517 case IMGFMT_IF09: | |
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1518 case IMGFMT_YVU9: |
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1519 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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1520 else pitch = 64; |
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1521 break; |
4456 | 1522 default: |
1523 if(spy >= 16) pitch = spy; | |
1524 else pitch = 16; | |
1525 break; | |
4009 | 1526 } |
1527 return pitch; | |
1528 } | |
1529 | |
3996 | 1530 static int radeon_vid_init_video( vidix_playback_t *config ) |
1531 { | |
4930 | 1532 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1533 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1534 radeon_vid_stop_video(); |
1535 left = config->src.x << 16; | |
1536 top = config->src.y << 16; | |
1537 src_h = config->src.h; | |
1538 src_w = config->src.w; | |
6483 | 1539 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1540 if(config->fourcc == IMGFMT_YV12 || |
1541 config->fourcc == IMGFMT_I420 || | |
1542 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1543 if(config->fourcc == IMGFMT_YVU9 || |
1544 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1545 if(config->fourcc == IMGFMT_Y800 || | |
1546 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1547 if(config->fourcc == IMGFMT_RGB32 || |
1548 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1549 if(config->fourcc == IMGFMT_RGB32 || |
1550 config->fourcc == IMGFMT_BGR32 || | |
1551 config->fourcc == IMGFMT_RGB24 || | |
1552 config->fourcc == IMGFMT_BGR24 || | |
1553 config->fourcc == IMGFMT_RGB16 || | |
1554 config->fourcc == IMGFMT_BGR16 || | |
1555 config->fourcc == IMGFMT_RGB15 || | |
1556 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1557 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1558 mpitch = best_pitch-1; |
3996 | 1559 switch(config->fourcc) |
1560 { | |
6483 | 1561 /* 4:0:0 */ |
1562 case IMGFMT_Y800: | |
1563 case IMGFMT_Y8: | |
1564 /* 4:1:0 */ | |
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1565 case IMGFMT_YVU9: |
6483 | 1566 case IMGFMT_IF09: |
3996 | 1567 /* 4:2:0 */ |
1568 case IMGFMT_IYUV: | |
1569 case IMGFMT_YV12: | |
4415 | 1570 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1571 config->dest.pitch.y = |
1572 config->dest.pitch.u = | |
4415 | 1573 config->dest.pitch.v = best_pitch; |
3996 | 1574 break; |
4416 | 1575 /* RGB 4:4:4:4 */ |
1576 case IMGFMT_RGB32: | |
1577 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1578 config->dest.pitch.y = | |
1579 config->dest.pitch.u = | |
1580 config->dest.pitch.v = best_pitch; | |
1581 break; | |
3996 | 1582 /* 4:2:2 */ |
4455 | 1583 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1584 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1585 config->dest.pitch.y = |
1586 config->dest.pitch.u = | |
4415 | 1587 config->dest.pitch.v = best_pitch; |
3996 | 1588 break; |
1589 } | |
1590 dest_w = config->dest.w; | |
1591 dest_h = config->dest.h; | |
1592 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1593 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1594 besr.fourcc = config->fourcc; | |
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1595 |
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1596 /* flat panel */ |
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1597 if(INREG(FP_VERT_STRETCH)&VERT_STRETCH_ENABLE){ |
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1598 besr.v_inc = (src_h * radeon_get_yres() / radeon_get_fp_yres() << 20) / dest_h; |
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1599 } |
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1600 else besr.v_inc = (src_h << 20) / dest_h; |
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1601 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1602 h_inc = (src_w << 12) / dest_w; |
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1603 |
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1604 { |
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1605 unsigned int ecp_div; |
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1606 ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; |
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1607 h_inc <<= ecp_div; |
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1608 } |
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1609 |
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1610 |
3996 | 1611 step_by = 1; |
1612 while(h_inc >= (2 << 12)) { | |
1613 step_by++; | |
1614 h_inc >>= 1; | |
1615 } | |
1616 | |
1617 /* keep everything in 16.16 */ | |
4015 | 1618 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1619 config->offsets[0] = 0; |
4930 | 1620 for(i=1;i<besr.vid_nbufs;i++) |
1621 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1622 if(is_420 || is_410 || is_400) |
3996 | 1623 { |
1624 uint32_t d1line,d2line,d3line; | |
1625 d1line = top*pitch; | |
6483 | 1626 if(is_420) |
1627 { | |
1628 d2line = src_h*pitch+(d1line>>2); | |
1629 d3line = d2line+((src_h*pitch)>>2); | |
1630 } | |
1631 else | |
1632 if(is_410) | |
1633 { | |
1634 d2line = src_h*pitch+(d1line>>4); | |
1635 d3line = d2line+((src_h*pitch)>>4); | |
1636 } | |
1637 else | |
1638 { | |
1639 d2line = 0; | |
1640 d3line = 0; | |
1641 } | |
3996 | 1642 d1line += (left >> 16) & ~15; |
6483 | 1643 if(is_420) |
1644 { | |
1645 d2line += (left >> 17) & ~15; | |
1646 d3line += (left >> 17) & ~15; | |
1647 } | |
1648 else | |
1649 if(is_410) | |
1650 { | |
1651 d2line += (left >> 18) & ~15; | |
1652 d3line += (left >> 18) & ~15; | |
1653 } | |
3996 | 1654 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1655 if(is_400) |
1656 { | |
1657 config->offset.v = 0; | |
1658 config->offset.u = 0; | |
1659 } | |
1660 else | |
1661 { | |
1662 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1663 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1664 } | |
4930 | 1665 for(i=0;i<besr.vid_nbufs;i++) |
1666 { | |
1667 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1668 if(is_400) |
1669 { | |
1670 besr.vid_buf_base_adrs_v[i]=0; | |
1671 besr.vid_buf_base_adrs_u[i]=0; | |
1672 } | |
1673 else | |
1674 { | |
9892 | 1675 if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1676 { | |
1677 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1678 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1679 } | |
1680 else | |
1681 { | |
1682 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1683 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1684 } | |
6483 | 1685 } |
4930 | 1686 } |
1687 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1688 if(is_400) |
1689 { | |
1690 config->offset.v = 0; | |
1691 config->offset.u = 0; | |
1692 } | |
1693 else | |
1694 { | |
1695 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1696 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1697 } | |
3996 | 1698 } |
1699 else | |
1700 { | |
1701 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1702 for(i=0;i<besr.vid_nbufs;i++) |
1703 { | |
1704 besr.vid_buf_base_adrs_y[i] = | |
1705 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1706 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1707 } |
3996 | 1708 } |
1709 | |
1710 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1711 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1712 ((tmp << 12) & 0xf0000000); | |
1713 | |
1714 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1715 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1716 ((tmp << 12) & 0x70000000); | |
1717 tmp = (top & 0x0000ffff) + 0x00018000; | |
1718 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1719 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1720 | |
1721 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1722 besr.p23_v_accum_init = (is_420||is_410) ? |
1723 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1724 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1725 | |
6483 | 1726 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1727 left = (left >> 16) & 15; |
4571 | 1728 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1729 if(is_rgb32) |
4571 | 1730 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1731 else |
6483 | 1732 if(is_410) |
1733 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1734 else | |
4416 | 1735 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1736 besr.step_by = step_by | (step_by << 8); |
1737 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1738 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1739 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1740 if(is_420 || is_410) |
3996 | 1741 { |
6483 | 1742 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1743 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1744 } | |
1745 else besr.p23_blank_lines_at_top = 0; | |
1746 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1747 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1748 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1749 if (is_410||is_420) src_w>>=is_410?2:1; |
1750 if(is_400) | |
1751 { | |
1752 besr.p2_x_start_end = 0; | |
1753 besr.p3_x_start_end = 0; | |
1754 } | |
1755 else | |
1756 { | |
1757 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1758 besr.p3_x_start_end = besr.p2_x_start_end; | |
1759 } | |
4869 | 1760 |
3996 | 1761 return 0; |
1762 } | |
1763 | |
4009 | 1764 static void radeon_compute_framesize(vidix_playback_t *info) |
1765 { | |
4666 | 1766 unsigned pitch,awidth,dbpp; |
4456 | 1767 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1768 dbpp = radeon_vid_get_dbpp(); |
4033 | 1769 switch(info->fourcc) |
1770 { | |
1771 case IMGFMT_I420: | |
1772 case IMGFMT_YV12: | |
1773 case IMGFMT_IYUV: | |
4666 | 1774 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1775 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1776 break; |
6483 | 1777 case IMGFMT_Y800: |
1778 case IMGFMT_Y8: | |
1779 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1780 info->frame_size = awidth*info->src.h; | |
1781 break; | |
1782 case IMGFMT_IF09: | |
1783 case IMGFMT_YVU9: | |
1784 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1785 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1786 break; | |
4429 | 1787 case IMGFMT_RGB32: |
1788 case IMGFMT_BGR32: | |
4666 | 1789 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1790 info->frame_size = awidth*info->src.h; |
4429 | 1791 break; |
1792 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1793 default: |
1794 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1795 info->frame_size = awidth*info->src.h; |
4033 | 1796 break; |
1797 } | |
4009 | 1798 } |
1799 | |
3996 | 1800 int vixConfigPlayback(vidix_playback_t *info) |
1801 { | |
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1802 unsigned rgb_size,nfr; |
3996 | 1803 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1804 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1805 if(info->num_frames==1) besr.double_buff=0; |
1806 else besr.double_buff=1; | |
4009 | 1807 radeon_compute_framesize(info); |
4930 | 1808 |
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1809 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1810 nfr = info->num_frames; |
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1811 for(;nfr>0; nfr--) |
4930 | 1812 { |
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1813 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
12286 | 1814 #ifdef HAVE_X11 |
1815 radeon_overlay_off -= firegl_shift; | |
1816 #endif | |
4930 | 1817 radeon_overlay_off &= 0xffff0000; |
1818 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1819 } | |
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1820 if(nfr <= 3) |
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1821 { |
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1822 nfr = info->num_frames; |
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1823 for(;nfr>0; nfr--) |
4930 | 1824 { |
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1825 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
12286 | 1826 #ifdef HAVE_X11 |
1827 radeon_overlay_off -= firegl_shift; | |
1828 #endif | |
4930 | 1829 radeon_overlay_off &= 0xffff0000; |
1830 if(radeon_overlay_off > 0) break; | |
1831 } | |
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1832 } |
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1833 if(nfr <= 0) return EINVAL; |
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1834 info->num_frames = nfr; |
4930 | 1835 besr.vid_nbufs = info->num_frames; |
1836 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1837 radeon_vid_init_video(info); |
1838 return 0; | |
1839 } | |
1840 | |
1841 int vixPlaybackOn( void ) | |
1842 { | |
1843 radeon_vid_display_video(); | |
1844 return 0; | |
1845 } | |
1846 | |
1847 int vixPlaybackOff( void ) | |
1848 { | |
1849 radeon_vid_stop_video(); | |
1850 return 0; | |
1851 } | |
1852 | |
4033 | 1853 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1854 { |
4412 | 1855 uint32_t off[6]; |
4930 | 1856 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1857 /* |
1858 buf3-5 always should point onto second buffer for better | |
1859 deinterlacing and TV-in | |
1860 */ | |
4666 | 1861 if(!besr.double_buff) return 0; |
4930 | 1862 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1863 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1864 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1865 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1866 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1867 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1868 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1869 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1870 radeon_fifo_wait(8); |
3996 | 1871 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1872 radeon_engine_idle(); |
3996 | 1873 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1874 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1875 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1876 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1877 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1878 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1879 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1880 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1881 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1882 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1883 return 0; |
1884 } | |
1885 | |
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1886 vidix_video_eq_t equal = |
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1887 { |
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1888 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1889 #ifndef RAGE128 |
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1890 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1891 #endif |
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1892 , |
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1893 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1894 |
1895 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1896 { | |
1897 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1898 return 0; | |
1899 } | |
1900 | |
4229 | 1901 #ifndef RAGE128 |
1902 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1903 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1904 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1905 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1906 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1907 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1908 #endif | |
1909 | |
3996 | 1910 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1911 { | |
1912 #ifdef RAGE128 | |
1913 int br,sat; | |
4229 | 1914 #else |
1915 int itu_space; | |
3996 | 1916 #endif |
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1917 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1918 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1919 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1920 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1921 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1922 { |
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1923 equal.red_intensity = eq->red_intensity; |
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1924 equal.green_intensity = eq->green_intensity; |
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1925 equal.blue_intensity = eq->blue_intensity; |
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1926 } |
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1927 equal.flags = eq->flags; |
3996 | 1928 #ifdef RAGE128 |
1929 br = equal.brightness * 64 / 1000; | |
4229 | 1930 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1931 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1932 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1933 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1934 #else | |
4229 | 1935 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1936 RTFCheckParam(equal.brightness); | |
1937 RTFCheckParam(equal.saturation); | |
1938 RTFCheckParam(equal.contrast); | |
1939 RTFCheckParam(equal.hue); | |
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1940 RTFCheckParam(equal.red_intensity); |
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1941 RTFCheckParam(equal.green_intensity); |
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1942 RTFCheckParam(equal.blue_intensity); |
4229 | 1943 radeon_set_transform(RTFBrightness(equal.brightness), |
1944 RTFContrast(equal.contrast), | |
1945 RTFSaturation(equal.saturation), | |
1946 RTFHue(equal.hue), | |
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1947 RTFIntensity(equal.red_intensity), |
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1948 RTFIntensity(equal.green_intensity), |
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1949 RTFIntensity(equal.blue_intensity), |
4229 | 1950 itu_space); |
3996 | 1951 #endif |
1952 return 0; | |
1953 } | |
1954 | |
4611 | 1955 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1956 { | |
1957 unsigned sflg; | |
1958 switch(info->flags) | |
1959 { | |
1960 default: | |
1961 case CFG_NON_INTERLACED: | |
1962 besr.deinterlace_on = 0; | |
1963 break; | |
1964 case CFG_EVEN_ODD_INTERLACING: | |
1965 case CFG_INTERLACED: | |
1966 besr.deinterlace_on = 1; | |
1967 besr.deinterlace_pattern = 0x900AAAAA; | |
1968 break; | |
1969 case CFG_ODD_EVEN_INTERLACING: | |
1970 besr.deinterlace_on = 1; | |
1971 besr.deinterlace_pattern = 0x00055555; | |
1972 break; | |
1973 case CFG_UNIQUE_INTERLACING: | |
1974 besr.deinterlace_on = 1; | |
1975 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1976 break; | |
1977 } | |
1978 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1979 radeon_engine_idle(); | |
1980 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1981 radeon_fifo_wait(15); | |
1982 sflg = INREG(OV0_SCALE_CNTL); | |
1983 if(besr.deinterlace_on) | |
1984 { | |
1985 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1986 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1987 } | |
1988 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1989 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1990 return 0; | |
1991 } | |
1992 | |
1993 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1994 { | |
1995 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1996 else | |
1997 { | |
1998 info->flags = CFG_UNIQUE_INTERLACING; | |
1999 info->deinterlace_pattern = besr.deinterlace_pattern; | |
2000 } | |
2001 return 0; | |
2002 } | |
4869 | 2003 |
2004 | |
2005 /* Graphic keys */ | |
2006 static vidix_grkey_t radeon_grkey; | |
2007 | |
2008 static void set_gr_key( void ) | |
2009 { | |
2010 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
2011 { | |
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changeset
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2012 int dbpp=radeon_vid_get_dbpp(); |
4869 | 2013 besr.ckey_on=1; |
2014 | |
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parents:
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diff
changeset
|
2015 switch(dbpp) |
4869 | 2016 { |
2017 case 15: | |
8856 | 2018 #ifdef RADEON |
8858 | 2019 if(RadeonFamily > 100) |
8856 | 2020 besr.graphics_key_clr= |
2021 ((radeon_grkey.ckey.blue &0xF8)) | |
2022 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
2023 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
2024 else | |
2025 #endif | |
4869 | 2026 besr.graphics_key_clr= |
2027 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
2028 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
2029 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
2030 break; | |
2031 case 16: | |
8856 | 2032 #ifdef RADEON |
2033 /* This test may be too general/specific */ | |
8858 | 2034 if(RadeonFamily > 100) |
8856 | 2035 besr.graphics_key_clr= |
2036 ((radeon_grkey.ckey.blue &0xF8)) | |
2037 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
2038 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
2039 else | |
2040 #endif | |
4869 | 2041 besr.graphics_key_clr= |
2042 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
2043 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
2044 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
2045 break; | |
2046 case 24: | |
2047 besr.graphics_key_clr= | |
2048 ((radeon_grkey.ckey.blue &0xFF)) | |
2049 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
2050 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
2051 break; | |
2052 case 32: | |
2053 besr.graphics_key_clr= | |
2054 ((radeon_grkey.ckey.blue &0xFF)) | |
2055 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
2056 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
2057 break; | |
2058 default: | |
2059 besr.ckey_on=0; | |
2060 besr.graphics_key_msk=0; | |
2061 besr.graphics_key_clr=0; | |
2062 } | |
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arpi
parents:
5165
diff
changeset
|
2063 #ifdef RAGE128 |
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parents:
5165
diff
changeset
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2064 besr.graphics_key_msk=(1<<dbpp)-1; |
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arpi
parents:
5165
diff
changeset
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2065 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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arpi
parents:
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diff
changeset
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2066 #else |
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arpi
parents:
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changeset
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2067 besr.graphics_key_msk=besr.graphics_key_clr; |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
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diff
changeset
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2068 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; |
6254
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arpi
parents:
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diff
changeset
|
2069 #endif |
4869 | 2070 } |
2071 else | |
2072 { | |
2073 besr.ckey_on=0; | |
2074 besr.graphics_key_msk=0; | |
2075 besr.graphics_key_clr=0; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
changeset
|
2076 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 2077 } |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
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diff
changeset
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2078 radeon_fifo_wait(3); |
4869 | 2079 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
2080 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
2081 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
2082 } | |
2083 | |
2084 int vixGetGrKeys(vidix_grkey_t *grkey) | |
2085 { | |
2086 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
2087 return(0); | |
2088 } | |
2089 | |
2090 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
2091 { | |
2092 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
2093 set_gr_key(); | |
2094 return(0); | |
2095 } |