Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 13335:6c002b4462ae
workaround for Xorg-6.8 not saving the surface registers on bigendian
architectures, patch by Luca Barbato <lu_zero at gentoo.org>
author | faust3 |
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date | Tue, 14 Sep 2004 20:43:39 +0000 |
parents | a6f958139ab8 |
children | c2cd3374a1cb |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
12286 | 6 |
7 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) | |
8 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch) | |
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9 PPC support by Alex Beregszaszi |
3996 | 10 */ |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <math.h> | |
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17 #include <inttypes.h> |
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18 |
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19 #include "../../config.h" |
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20 #include "../../bswap.h" |
4201 | 21 #include "../../libdha/pci_ids.h" |
22 #include "../../libdha/pci_names.h" | |
3996 | 23 #include "../vidix.h" |
24 #include "../fourcc.h" | |
25 #include "../../libdha/libdha.h" | |
26 #include "radeon.h" | |
27 | |
12286 | 28 #ifdef HAVE_X11 |
29 #include <X11/Xlib.h> | |
30 #endif | |
31 | |
3996 | 32 #ifdef RAGE128 |
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33 #define RADEON_MSG "[rage128]" |
3996 | 34 #define X_ADJUST 0 |
35 #else | |
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36 #define RADEON_MSG "[radeon]" |
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37 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 38 #ifndef RADEON |
39 #define RADEON | |
40 #endif | |
41 #endif | |
42 | |
4030 | 43 static int __verbose = 0; |
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44 #ifdef RADEON |
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45 static int is_shift_required = 0; |
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46 #endif |
4015 | 47 |
3996 | 48 typedef struct bes_registers_s |
49 { | |
50 /* base address of yuv framebuffer */ | |
51 uint32_t yuv_base; | |
52 uint32_t fourcc; | |
53 uint32_t dest_bpp; | |
54 /* YUV BES registers */ | |
55 uint32_t reg_load_cntl; | |
56 uint32_t h_inc; | |
57 uint32_t step_by; | |
58 uint32_t y_x_start; | |
59 uint32_t y_x_end; | |
60 uint32_t v_inc; | |
61 uint32_t p1_blank_lines_at_top; | |
62 uint32_t p23_blank_lines_at_top; | |
63 uint32_t vid_buf_pitch0_value; | |
64 uint32_t vid_buf_pitch1_value; | |
65 uint32_t p1_x_start_end; | |
66 uint32_t p2_x_start_end; | |
67 uint32_t p3_x_start_end; | |
68 uint32_t base_addr; | |
4930 | 69 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
70 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
71 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
72 uint32_t vid_nbufs; | |
3996 | 73 |
74 uint32_t p1_v_accum_init; | |
75 uint32_t p1_h_accum_init; | |
76 uint32_t p23_v_accum_init; | |
77 uint32_t p23_h_accum_init; | |
78 uint32_t scale_cntl; | |
79 uint32_t exclusive_horz; | |
80 uint32_t auto_flip_cntl; | |
81 uint32_t filter_cntl; | |
82 uint32_t key_cntl; | |
83 uint32_t test; | |
84 /* Configurable stuff */ | |
85 int double_buff; | |
86 | |
87 int brightness; | |
88 int saturation; | |
89 | |
90 int ckey_on; | |
91 uint32_t graphics_key_clr; | |
92 uint32_t graphics_key_msk; | |
4869 | 93 uint32_t ckey_cntl; |
3996 | 94 |
95 int deinterlace_on; | |
96 uint32_t deinterlace_pattern; | |
97 | |
98 } bes_registers_t; | |
99 | |
100 typedef struct video_registers_s | |
101 { | |
102 const char * sname; | |
103 uint32_t name; | |
104 uint32_t value; | |
105 }video_registers_t; | |
106 | |
107 static bes_registers_t besr; | |
108 #ifndef RAGE128 | |
8855 | 109 static int RadeonFamily=100; |
3996 | 110 #endif |
111 #define DECLARE_VREG(name) { #name, name, 0 } | |
112 static video_registers_t vregs[] = | |
113 { | |
114 DECLARE_VREG(VIDEOMUX_CNTL), | |
115 DECLARE_VREG(VIPPAD_MASK), | |
116 DECLARE_VREG(VIPPAD1_A), | |
117 DECLARE_VREG(VIPPAD1_EN), | |
118 DECLARE_VREG(VIPPAD1_Y), | |
119 DECLARE_VREG(OV0_Y_X_START), | |
120 DECLARE_VREG(OV0_Y_X_END), | |
121 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
122 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
123 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
124 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
125 DECLARE_VREG(OV0_SCALE_CNTL), | |
126 DECLARE_VREG(OV0_V_INC), | |
127 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
128 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
129 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
130 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
131 #ifdef RADEON | |
132 DECLARE_VREG(OV0_BASE_ADDR), | |
133 #endif | |
134 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
135 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
136 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
137 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
138 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
139 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
140 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
141 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
142 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
143 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
144 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
145 DECLARE_VREG(OV0_H_INC), | |
146 DECLARE_VREG(OV0_STEP_BY), | |
147 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
148 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
149 DECLARE_VREG(OV0_P1_X_START_END), | |
150 DECLARE_VREG(OV0_P2_X_START_END), | |
151 DECLARE_VREG(OV0_P3_X_START_END), | |
152 DECLARE_VREG(OV0_FILTER_CNTL), | |
153 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
154 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
155 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
156 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
157 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
158 DECLARE_VREG(OV0_FLAG_CNTL), | |
159 #ifdef RAGE128 | |
160 DECLARE_VREG(OV0_COLOUR_CNTL), | |
161 #else | |
162 DECLARE_VREG(OV0_SLICE_CNTL), | |
163 #endif | |
164 DECLARE_VREG(OV0_VID_KEY_CLR), | |
165 DECLARE_VREG(OV0_VID_KEY_MSK), | |
166 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
167 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
168 DECLARE_VREG(OV0_KEY_CNTL), | |
169 DECLARE_VREG(OV0_TEST), | |
170 DECLARE_VREG(OV0_LIN_TRANS_A), | |
171 DECLARE_VREG(OV0_LIN_TRANS_B), | |
172 DECLARE_VREG(OV0_LIN_TRANS_C), | |
173 DECLARE_VREG(OV0_LIN_TRANS_D), | |
174 DECLARE_VREG(OV0_LIN_TRANS_E), | |
175 DECLARE_VREG(OV0_LIN_TRANS_F), | |
176 DECLARE_VREG(OV0_GAMMA_0_F), | |
177 DECLARE_VREG(OV0_GAMMA_10_1F), | |
178 DECLARE_VREG(OV0_GAMMA_20_3F), | |
179 DECLARE_VREG(OV0_GAMMA_40_7F), | |
180 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
181 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
182 DECLARE_VREG(SUBPIC_CNTL), | |
183 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
184 DECLARE_VREG(SUBPIC_Y_X_START), | |
185 DECLARE_VREG(SUBPIC_Y_X_END), | |
186 DECLARE_VREG(SUBPIC_V_INC), | |
187 DECLARE_VREG(SUBPIC_H_INC), | |
188 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
189 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
190 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
191 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
192 DECLARE_VREG(SUBPIC_PITCH), | |
193 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
194 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
195 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
196 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
197 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
198 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
199 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
200 DECLARE_VREG(IDCT_RUNS), | |
201 DECLARE_VREG(IDCT_LEVELS), | |
202 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
203 DECLARE_VREG(IDCT_AUTH), | |
9044 | 204 DECLARE_VREG(IDCT_CONTROL), |
205 DECLARE_VREG(CONFIG_CNTL) | |
3996 | 206 }; |
4030 | 207 |
12286 | 208 #ifdef HAVE_X11 |
209 static uint32_t firegl_shift = 0; | |
210 #endif | |
3996 | 211 static void * radeon_mmio_base = 0; |
212 static void * radeon_mem_base = 0; | |
213 static int32_t radeon_overlay_off = 0; | |
214 static uint32_t radeon_ram_size = 0; | |
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215 /* Restore on exit */ |
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216 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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217 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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218 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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219 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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220 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
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221 #ifdef WORDS_BIGENDIAN |
9044 | 222 static uint32_t SAVED_CONFIG_CNTL = 0; |
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223 #if defined(RAGE128) |
9044 | 224 #define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) |
225 #define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) | |
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226 #else |
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227 #define RADEON_SURFACE_CNTL 0x0b00 |
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228 #define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) |
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229 #define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) |
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230 #endif |
9044 | 231 #endif |
3996 | 232 |
4012 | 233 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
234 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
235 | |
236 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
237 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
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238 |
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239 static inline uint32_t INREG (uint32_t addr) { |
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240 uint32_t tmp = GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr); |
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241 return le2me_32(tmp); |
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242 } |
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243 //#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) |
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244 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,le2me_32(val)) |
3996 | 245 #define OUTREGP(addr,val,mask) \ |
246 do { \ | |
247 unsigned int _tmp = INREG(addr); \ | |
248 _tmp &= (mask); \ | |
249 _tmp |= (val); \ | |
250 OUTREG(addr, _tmp); \ | |
251 } while (0) | |
252 | |
4666 | 253 static __inline__ uint32_t INPLL(uint32_t addr) |
254 { | |
255 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
256 return (INREG(CLOCK_CNTL_DATA)); | |
257 } | |
258 | |
259 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
260 OUTREG(CLOCK_CNTL_DATA, val) | |
261 #define OUTPLLP(addr,val,mask) \ | |
262 do { \ | |
263 unsigned int _tmp = INPLL(addr); \ | |
264 _tmp &= (mask); \ | |
265 _tmp |= (val); \ | |
266 OUTPLL(addr, _tmp); \ | |
267 } while (0) | |
268 | |
3996 | 269 static uint32_t radeon_vid_get_dbpp( void ) |
270 { | |
271 uint32_t dbpp,retval; | |
272 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
273 switch(dbpp) | |
274 { | |
275 case DST_8BPP: retval = 8; break; | |
276 case DST_15BPP: retval = 15; break; | |
277 case DST_16BPP: retval = 16; break; | |
278 case DST_24BPP: retval = 24; break; | |
279 default: retval=32; break; | |
280 } | |
281 return retval; | |
282 } | |
283 | |
284 static int radeon_is_dbl_scan( void ) | |
285 { | |
286 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
287 } | |
288 | |
289 static int radeon_is_interlace( void ) | |
290 { | |
291 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
292 } | |
293 | |
4666 | 294 static uint32_t radeon_get_xres( void ) |
295 { | |
296 /* FIXME: currently we extract that from CRTC!!!*/ | |
297 uint32_t xres,h_total; | |
298 h_total = INREG(CRTC_H_TOTAL_DISP); | |
299 xres = (h_total >> 16) & 0xffff; | |
300 return (xres + 1)*8; | |
301 } | |
302 | |
303 static uint32_t radeon_get_yres( void ) | |
304 { | |
305 /* FIXME: currently we extract that from CRTC!!!*/ | |
306 uint32_t yres,v_total; | |
307 v_total = INREG(CRTC_V_TOTAL_DISP); | |
308 yres = (v_total >> 16) & 0xffff; | |
309 return yres + 1; | |
310 } | |
311 | |
4689 | 312 static void radeon_wait_vsync(void) |
313 { | |
314 int i; | |
315 | |
316 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
317 for (i = 0; i < 2000000; i++) | |
318 { | |
319 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
320 } | |
321 } | |
322 | |
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323 #ifdef RAGE128 |
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324 static void _radeon_engine_idle(void); |
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325 static void _radeon_fifo_wait(unsigned); |
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326 #define radeon_engine_idle() _radeon_engine_idle() |
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327 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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328 /* Flush all dirty data in the Pixel Cache to memory. */ |
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329 static __inline__ void radeon_engine_flush ( void ) |
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330 { |
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331 unsigned i; |
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332 |
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333 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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334 for (i = 0; i < 2000000; i++) { |
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335 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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336 } |
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337 } |
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338 |
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339 /* Reset graphics card to known state. */ |
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340 static void radeon_engine_reset( void ) |
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341 { |
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342 uint32_t clock_cntl_index; |
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343 uint32_t mclk_cntl; |
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344 uint32_t gen_reset_cntl; |
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345 |
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346 radeon_engine_flush(); |
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347 |
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348 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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349 mclk_cntl = INPLL(MCLK_CNTL); |
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350 |
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351 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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352 |
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353 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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354 |
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355 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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356 INREG(GEN_RESET_CNTL); |
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357 OUTREG(GEN_RESET_CNTL, |
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358 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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359 INREG(GEN_RESET_CNTL); |
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360 |
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361 OUTPLL(MCLK_CNTL, mclk_cntl); |
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362 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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363 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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364 } |
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365 #else |
4689 | 366 |
3996 | 367 static __inline__ void radeon_engine_flush ( void ) |
368 { | |
369 int i; | |
370 | |
371 /* initiate flush */ | |
372 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
373 ~RB2D_DC_FLUSH_ALL); | |
374 | |
375 for (i=0; i < 2000000; i++) { | |
376 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
377 break; | |
378 } | |
379 } | |
380 | |
4666 | 381 static void _radeon_engine_idle(void); |
382 static void _radeon_fifo_wait(unsigned); | |
383 #define radeon_engine_idle() _radeon_engine_idle() | |
384 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 385 |
4666 | 386 static void radeon_engine_reset( void ) |
3996 | 387 { |
4666 | 388 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
389 | |
390 radeon_engine_flush (); | |
391 | |
392 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
393 mclk_cntl = INPLL(MCLK_CNTL); | |
394 | |
395 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
396 FORCEON_MCLKA | | |
397 FORCEON_MCLKB | | |
398 FORCEON_YCLKA | | |
399 FORCEON_YCLKB | | |
400 FORCEON_MC | | |
401 FORCEON_AIC)); | |
402 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 403 |
4666 | 404 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
405 SOFT_RESET_CP | | |
406 SOFT_RESET_HI | | |
407 SOFT_RESET_SE | | |
408 SOFT_RESET_RE | | |
409 SOFT_RESET_PP | | |
410 SOFT_RESET_E2 | | |
411 SOFT_RESET_RB | | |
412 SOFT_RESET_HDP); | |
413 INREG(RBBM_SOFT_RESET); | |
414 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
415 ~(SOFT_RESET_CP | | |
416 SOFT_RESET_HI | | |
417 SOFT_RESET_SE | | |
418 SOFT_RESET_RE | | |
419 SOFT_RESET_PP | | |
420 SOFT_RESET_E2 | | |
421 SOFT_RESET_RB | | |
422 SOFT_RESET_HDP)); | |
423 INREG(RBBM_SOFT_RESET); | |
424 | |
425 OUTPLL(MCLK_CNTL, mclk_cntl); | |
426 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
427 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
428 | |
429 return; | |
3996 | 430 } |
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431 #endif |
4666 | 432 static void radeon_engine_restore( void ) |
3996 | 433 { |
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434 #ifndef RAGE128 |
4666 | 435 int pitch64; |
436 uint32_t xres,yres,bpp; | |
437 radeon_fifo_wait(1); | |
438 xres = radeon_get_xres(); | |
439 yres = radeon_get_yres(); | |
440 bpp = radeon_vid_get_dbpp(); | |
441 /* turn of all automatic flushing - we'll do it all */ | |
442 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
443 | |
444 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
445 | |
446 radeon_fifo_wait(1); | |
447 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
448 (pitch64 << 22)); | |
449 | |
450 radeon_fifo_wait(1); | |
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451 #if defined(WORDS_BIGENDIAN) |
9044 | 452 #ifdef RADEON |
453 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
454 #endif | |
4666 | 455 #else |
456 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
457 #endif | |
458 | |
459 radeon_fifo_wait(1); | |
460 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
461 | DEFAULT_SC_BOTTOM_MAX)); | |
462 radeon_fifo_wait(1); | |
463 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
464 | GMC_BRUSH_SOLID_COLOR | |
465 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 466 |
4666 | 467 radeon_fifo_wait(7); |
468 OUTREG(DST_LINE_START, 0); | |
469 OUTREG(DST_LINE_END, 0); | |
470 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
471 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
472 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
473 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
474 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
475 | |
476 radeon_engine_idle(); | |
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477 #endif |
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478 } |
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479 #ifdef RAGE128 |
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480 static void _radeon_fifo_wait (unsigned entries) |
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481 { |
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482 unsigned i; |
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483 |
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484 for(;;) |
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485 { |
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486 for (i=0; i<2000000; i++) |
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487 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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488 return; |
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489 radeon_engine_reset(); |
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490 radeon_engine_restore(); |
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491 } |
4666 | 492 } |
493 | |
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494 static void _radeon_engine_idle ( void ) |
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495 { |
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496 unsigned i; |
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497 |
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498 /* ensure FIFO is empty before waiting for idle */ |
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499 radeon_fifo_wait (64); |
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500 for(;;) |
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501 { |
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502 for (i=0; i<2000000; i++) { |
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503 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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504 radeon_engine_flush (); |
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505 return; |
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506 } |
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507 } |
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508 radeon_engine_reset(); |
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509 radeon_engine_restore(); |
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510 } |
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511 } |
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512 #else |
4666 | 513 static void _radeon_fifo_wait (unsigned entries) |
514 { | |
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515 unsigned i; |
3996 | 516 |
4666 | 517 for(;;) |
518 { | |
519 for (i=0; i<2000000; i++) | |
520 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
521 return; | |
522 radeon_engine_reset(); | |
523 radeon_engine_restore(); | |
524 } | |
525 } | |
526 static void _radeon_engine_idle ( void ) | |
527 { | |
528 int i; | |
529 | |
530 /* ensure FIFO is empty before waiting for idle */ | |
531 radeon_fifo_wait (64); | |
532 for(;;) | |
533 { | |
3996 | 534 for (i=0; i<2000000; i++) { |
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535 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 536 radeon_engine_flush (); |
537 return; | |
538 } | |
539 } | |
4666 | 540 radeon_engine_reset(); |
541 radeon_engine_restore(); | |
542 } | |
3996 | 543 } |
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544 #endif |
3996 | 545 |
546 #ifndef RAGE128 | |
547 /* Reference color space transform data */ | |
548 typedef struct tagREF_TRANSFORM | |
549 { | |
550 float RefLuma; | |
551 float RefRCb; | |
552 float RefRCr; | |
553 float RefGCb; | |
554 float RefGCr; | |
555 float RefBCb; | |
556 float RefBCr; | |
557 } REF_TRANSFORM; | |
558 | |
559 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
560 REF_TRANSFORM trans[2] = | |
561 { | |
562 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
563 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
564 }; | |
565 /**************************************************************************** | |
566 * SetTransform * | |
567 * Function: Calculates and sets color space transform from supplied * | |
568 * reference transform, gamma, brightness, contrast, hue and * | |
569 * saturation. * | |
570 * Inputs: bright - brightness * | |
571 * cont - contrast * | |
572 * sat - saturation * | |
573 * hue - hue * | |
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574 * red_intensity - intense of red component * |
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575 * green_intensity - intense of green component * |
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576 * blue_intensity - intense of blue component * |
3996 | 577 * ref - index to the table of refernce transforms * |
578 * Outputs: NONE * | |
579 ****************************************************************************/ | |
580 | |
581 static void radeon_set_transform(float bright, float cont, float sat, | |
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582 float hue, float red_intensity, |
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583 float green_intensity,float blue_intensity, |
4284 | 584 unsigned ref) |
3996 | 585 { |
586 float OvHueSin, OvHueCos; | |
587 float CAdjLuma, CAdjOff; | |
4284 | 588 float RedAdj,GreenAdj,BlueAdj; |
3996 | 589 float CAdjRCb, CAdjRCr; |
590 float CAdjGCb, CAdjGCr; | |
591 float CAdjBCb, CAdjBCr; | |
592 float OvLuma, OvROff, OvGOff, OvBOff; | |
593 float OvRCb, OvRCr; | |
594 float OvGCb, OvGCr; | |
595 float OvBCb, OvBCr; | |
596 float Loff = 64.0; | |
597 float Coff = 512.0f; | |
598 | |
599 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
600 uint32_t dwOvRCb, dwOvRCr; | |
601 uint32_t dwOvGCb, dwOvGCr; | |
602 uint32_t dwOvBCb, dwOvBCr; | |
603 | |
604 if (ref >= 2) return; | |
605 | |
606 OvHueSin = sin((double)hue); | |
607 OvHueCos = cos((double)hue); | |
608 | |
609 CAdjLuma = cont * trans[ref].RefLuma; | |
610 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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611 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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612 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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|
613 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 614 |
615 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
616 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
617 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
618 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
619 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
620 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
621 | |
622 #if 0 /* default constants */ | |
623 CAdjLuma = 1.16455078125; | |
624 | |
625 CAdjRCb = 0.0; | |
626 CAdjRCr = 1.59619140625; | |
627 CAdjGCb = -0.39111328125; | |
628 CAdjGCr = -0.8125; | |
629 CAdjBCb = 2.01708984375; | |
630 CAdjBCr = 0; | |
631 #endif | |
632 OvLuma = CAdjLuma; | |
633 OvRCb = CAdjRCb; | |
634 OvRCr = CAdjRCr; | |
635 OvGCb = CAdjGCb; | |
636 OvGCr = CAdjGCr; | |
637 OvBCb = CAdjBCb; | |
638 OvBCr = CAdjBCr; | |
4284 | 639 OvROff = RedAdj + CAdjOff - |
3996 | 640 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 641 OvGOff = GreenAdj + CAdjOff - |
3996 | 642 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 643 OvBOff = BlueAdj + CAdjOff - |
3996 | 644 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
645 #if 0 /* default constants */ | |
646 OvROff = -888.5; | |
647 OvGOff = 545; | |
648 OvBOff = -1104; | |
649 #endif | |
650 | |
651 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
652 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
653 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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654 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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655 as in Radeon is a lie */ |
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656 #if 0 |
8855 | 657 if(RadeonFamily == 100) |
3996 | 658 { |
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659 #endif |
3996 | 660 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
661 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
662 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
663 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
664 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
665 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
666 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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667 #if 0 |
3996 | 668 } |
669 else | |
670 { | |
671 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
672 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
673 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
674 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
675 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
676 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
677 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
678 } | |
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679 #endif |
3996 | 680 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
681 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
682 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
683 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
684 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
685 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
686 } | |
687 | |
688 /* Gamma curve definition */ | |
689 typedef struct | |
690 { | |
691 unsigned int gammaReg; | |
692 unsigned int gammaSlope; | |
693 unsigned int gammaOffset; | |
694 }GAMMA_SETTINGS; | |
695 | |
696 /* Recommended gamma curve parameters */ | |
697 GAMMA_SETTINGS r200_def_gamma[18] = | |
698 { | |
699 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
700 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
701 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
702 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
703 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
704 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
705 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
706 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
707 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
708 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
709 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
710 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
711 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
712 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
713 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
714 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
715 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
716 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
717 }; | |
718 | |
719 GAMMA_SETTINGS r100_def_gamma[6] = | |
720 { | |
721 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
722 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
723 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
724 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
725 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
726 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
727 }; | |
728 | |
729 static void make_default_gamma_correction( void ) | |
730 { | |
731 size_t i; | |
8855 | 732 if(RadeonFamily == 100) { |
3996 | 733 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); |
734 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
735 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
736 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
737 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
738 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
739 for(i=0; i<6; i++){ | |
740 OUTREG(r100_def_gamma[i].gammaReg, | |
741 (r100_def_gamma[i].gammaSlope<<16) | | |
742 r100_def_gamma[i].gammaOffset); | |
743 } | |
744 } | |
745 else{ | |
746 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
747 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
748 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
749 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
750 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
751 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
752 | |
753 /* Default Gamma, | |
754 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
755 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
756 for(i=0; i<18; i++){ | |
757 OUTREG(r200_def_gamma[i].gammaReg, | |
758 (r200_def_gamma[i].gammaSlope<<16) | | |
759 r200_def_gamma[i].gammaOffset); | |
760 } | |
761 } | |
762 } | |
763 #endif | |
764 | |
765 static void radeon_vid_make_default(void) | |
766 { | |
767 #ifdef RAGE128 | |
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768 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 769 #else |
770 make_default_gamma_correction(); | |
771 #endif | |
772 besr.deinterlace_pattern = 0x900AAAAA; | |
773 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
774 besr.deinterlace_on=1; | |
775 besr.double_buff=1; | |
4869 | 776 besr.ckey_on=0; |
777 besr.graphics_key_msk=0; | |
778 besr.graphics_key_clr=0; | |
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779 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 780 } |
781 | |
782 | |
783 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
784 | |
4107 | 785 static unsigned short ati_card_ids[] = |
3996 | 786 { |
787 #ifdef RAGE128 | |
788 /* | |
789 This driver should be compatible with Rage128 (pro) chips. | |
790 (include adaptive deinterlacing!!!). | |
791 Moreover: the same logic can be used with Mach64 chips. | |
792 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
793 but they are incompatible by i/o ports. So if enthusiasts will want | |
794 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
795 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
796 fourccs (422 and 420 formats only). | |
797 */ | |
798 /* Rage128 Pro GL */ | |
4107 | 799 DEVICE_ATI_RAGE_128_PA_PRO, |
800 DEVICE_ATI_RAGE_128_PB_PRO, | |
801 DEVICE_ATI_RAGE_128_PC_PRO, | |
802 DEVICE_ATI_RAGE_128_PD_PRO, | |
803 DEVICE_ATI_RAGE_128_PE_PRO, | |
804 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 805 /* Rage128 Pro VR */ |
4107 | 806 DEVICE_ATI_RAGE_128_PG_PRO, |
807 DEVICE_ATI_RAGE_128_PH_PRO, | |
808 DEVICE_ATI_RAGE_128_PI_PRO, | |
809 DEVICE_ATI_RAGE_128_PJ_PRO, | |
810 DEVICE_ATI_RAGE_128_PK_PRO, | |
811 DEVICE_ATI_RAGE_128_PL_PRO, | |
812 DEVICE_ATI_RAGE_128_PM_PRO, | |
813 DEVICE_ATI_RAGE_128_PN_PRO, | |
814 DEVICE_ATI_RAGE_128_PO_PRO, | |
815 DEVICE_ATI_RAGE_128_PP_PRO, | |
816 DEVICE_ATI_RAGE_128_PQ_PRO, | |
817 DEVICE_ATI_RAGE_128_PR_PRO, | |
818 DEVICE_ATI_RAGE_128_PS_PRO, | |
819 DEVICE_ATI_RAGE_128_PT_PRO, | |
820 DEVICE_ATI_RAGE_128_PU_PRO, | |
821 DEVICE_ATI_RAGE_128_PV_PRO, | |
822 DEVICE_ATI_RAGE_128_PW_PRO, | |
823 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 824 /* Rage128 GL */ |
4107 | 825 DEVICE_ATI_RAGE_128_RE_SG, |
826 DEVICE_ATI_RAGE_128_RF_SG, | |
827 DEVICE_ATI_RAGE_128_RG, | |
828 DEVICE_ATI_RAGE_128_RK_VR, | |
829 DEVICE_ATI_RAGE_128_RL_VR, | |
830 DEVICE_ATI_RAGE_128_SE_4X, | |
831 DEVICE_ATI_RAGE_128_SF_4X, | |
832 DEVICE_ATI_RAGE_128_SG_4X, | |
8854 | 833 DEVICE_ATI_RAGE_128_SH, |
4107 | 834 DEVICE_ATI_RAGE_128_SK_4X, |
835 DEVICE_ATI_RAGE_128_SL_4X, | |
836 DEVICE_ATI_RAGE_128_SM_4X, | |
8854 | 837 DEVICE_ATI_RAGE_128_4X, |
4107 | 838 DEVICE_ATI_RAGE_128_PRO, |
839 DEVICE_ATI_RAGE_128_PRO2, | |
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840 DEVICE_ATI_RAGE_128_PRO3, |
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841 /* these seem to be based on rage 128 instead of mach64 */ |
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842 DEVICE_ATI_RAGE_MOBILITY_M3, |
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843 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 844 #else |
845 /* Radeons (indeed: Rage 256 Pro ;) */ | |
8855 | 846 DEVICE_ATI_RADEON_R100_QD, |
847 DEVICE_ATI_RADEON_R100_QE, | |
848 DEVICE_ATI_RADEON_R100_QF, | |
849 DEVICE_ATI_RADEON_R100_QG, | |
850 DEVICE_ATI_RADEON_VE_QY, | |
851 DEVICE_ATI_RADEON_VE_QZ, | |
8854 | 852 DEVICE_ATI_RADEON_MOBILITY_M7, |
853 DEVICE_ATI_RADEON_MOBILITY_M72, | |
4107 | 854 DEVICE_ATI_RADEON_MOBILITY_M6, |
855 DEVICE_ATI_RADEON_MOBILITY_M62, | |
10332 | 856 DEVICE_ATI_RADEON_MOBILITY_U1, |
8855 | 857 DEVICE_ATI_RADEON_R200_BB, |
858 DEVICE_ATI_RADEON_R200_QH, | |
859 DEVICE_ATI_RADEON_R200_QI, | |
860 DEVICE_ATI_RADEON_R200_QJ, | |
861 DEVICE_ATI_RADEON_R200_QK, | |
8854 | 862 DEVICE_ATI_RADEON_R200_QL, |
8855 | 863 DEVICE_ATI_RADEON_R200_QH2, |
864 DEVICE_ATI_RADEON_R200_QI2, | |
865 DEVICE_ATI_RADEON_R200_QJ2, | |
866 DEVICE_ATI_RADEON_R200_QK2, | |
8854 | 867 DEVICE_ATI_RADEON_RV200_QW, |
8855 | 868 DEVICE_ATI_RADEON_RV200_QX, |
869 DEVICE_ATI_RADEON_R250_ID, | |
870 DEVICE_ATI_RADEON_R250_IE, | |
871 DEVICE_ATI_RADEON_R250_IF, | |
872 DEVICE_ATI_RADEON_R250_IG, | |
873 DEVICE_ATI_RADEON_R250_LD, | |
874 DEVICE_ATI_RADEON_R250_LE, | |
875 DEVICE_ATI_RADEON_R250_LF, | |
876 DEVICE_ATI_RADEON_R250_LG, | |
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faust3
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|
877 DEVICE_ATI_RV250_5C61_RADEON, |
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|
878 DEVICE_ATI_RV250_5C63_RADEON, |
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879 DEVICE_ATI_RV280_RADEON_9200, |
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880 DEVICE_ATI_RV280_RADEON_92002, |
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881 DEVICE_ATI_RV280_RADEON_92003, |
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882 DEVICE_ATI_RV280_RADEON_92004, |
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883 DEVICE_ATI_RV280_RADEON_92005, |
8855 | 884 DEVICE_ATI_RADEON_R300_ND, |
885 DEVICE_ATI_RADEON_R300_NE, | |
886 DEVICE_ATI_RADEON_R300_NF, | |
11371
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attila
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|
887 DEVICE_ATI_RADEON_R300_NG, |
12361
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888 DEVICE_ATI_RADEON_R300_AE, |
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|
889 DEVICE_ATI_RADEON_R300_AF, |
11658
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|
890 DEVICE_ATI_RADEON_RV350_AP, |
12361
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891 DEVICE_ATI_RADEON_RV350_AR, |
12454
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892 DEVICE_ATI_RADEON_R350_AH, |
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893 DEVICE_ATI_RADEON_R350_AI, |
12060 | 894 DEVICE_ATI_RADEON_R350_NH, |
12459 | 895 DEVICE_ATI_RADEON_R360_NJ, |
12060 | 896 DEVICE_ATI_RV350_MOBILITY_RADEON, |
897 DEVICE_ATI_RV350_MOBILITY_RADEON2 | |
3996 | 898 #endif |
899 }; | |
900 | |
901 static int find_chip(unsigned chip_id) | |
902 { | |
903 unsigned i; | |
4107 | 904 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 905 { |
4107 | 906 if(chip_id == ati_card_ids[i]) return i; |
3996 | 907 } |
908 return -1; | |
909 } | |
910 | |
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911 static pciinfo_t pci_info; |
3996 | 912 static int probed=0; |
913 | |
914 vidix_capability_t def_cap = | |
915 { | |
916 #ifdef RAGE128 | |
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917 "BES driver for Rage128 cards", |
3996 | 918 #else |
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919 "BES driver for Radeon cards", |
3996 | 920 #endif |
4327 | 921 "Nick Kurshev", |
3996 | 922 TYPE_OUTPUT | TYPE_FX, |
4191 | 923 { 0, 0, 0, 0 }, |
4282 | 924 2048, |
925 2048, | |
3996 | 926 4, |
927 4, | |
928 -1, | |
4264 | 929 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 930 VENDOR_ATI, |
3996 | 931 0, |
932 { 0, 0, 0, 0} | |
933 }; | |
934 | |
12286 | 935 #ifdef HAVE_X11 |
936 void probe_fireGL_driver() { | |
937 Display *dp = XOpenDisplay ((void*)0); | |
938 int n = 0; | |
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|
939 char **extlist; |
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940 if (dp==NULL) { |
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|
941 return; |
b5e7d2464c00
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|
942 } |
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|
943 extlist = XListExtensions (dp, &n); |
12286 | 944 XCloseDisplay (dp); |
945 if (extlist) { | |
946 int i; | |
947 int ext_fgl = 0, ext_fglrx = 0; | |
948 for (i = 0; i < n; i++) { | |
949 if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1; | |
950 if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1; | |
951 } | |
952 if (ext_fgl) { | |
953 printf(RADEON_MSG" ATI FireGl driver detected"); | |
954 firegl_shift = 0x500000; | |
955 if (!ext_fglrx) { | |
956 printf(", but DRI seems not to be activated\n"); | |
957 printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!"); | |
958 } | |
959 printf("\n"); | |
960 } | |
961 } | |
962 } | |
963 #endif | |
3996 | 964 |
4191 | 965 int vixProbe( int verbose,int force ) |
3996 | 966 { |
967 pciinfo_t lst[MAX_PCI_DEVICES]; | |
968 unsigned i,num_pci; | |
969 int err; | |
4030 | 970 __verbose = verbose; |
3996 | 971 err = pci_scan(lst,&num_pci); |
972 if(err) | |
973 { | |
11678
972d1998bde9
occured --> occurred typo patch by Clinton Roy <croy@dstc.edu.au>
diego
parents:
11658
diff
changeset
|
974 printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err)); |
3996 | 975 return err; |
976 } | |
977 else | |
978 { | |
979 err = ENXIO; | |
980 for(i=0;i<num_pci;i++) | |
981 { | |
4107 | 982 if(lst[i].vendor == VENDOR_ATI) |
3996 | 983 { |
984 int idx; | |
4191 | 985 const char *dname; |
3996 | 986 idx = find_chip(lst[i].device); |
4191 | 987 if(idx == -1 && force == PROBE_NORMAL) continue; |
988 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
989 dname = dname ? dname : "Unknown chip"; | |
990 printf(RADEON_MSG" Found chip: %s\n",dname); | |
9767
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
991 if ((lst[i].command & PCI_COMMAND_IO) == 0) |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
992 { |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
993 printf("[radeon] Device is disabled, ignoring\n"); |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
994 continue; |
f6d2772efca3
Ignore disabled cards. (Jon Burgess <jburgess@uklinux.net>)
ranma
parents:
9544
diff
changeset
|
995 } |
3996 | 996 #ifndef RAGE128 |
4191 | 997 if(idx != -1) |
12286 | 998 #ifdef HAVE_X11 |
999 probe_fireGL_driver(); | |
1000 #endif | |
8855 | 1001 { |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1002 switch(ati_card_ids[idx]) { |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1003 /* Original radeon */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1004 case DEVICE_ATI_RADEON_R100_QD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1005 case DEVICE_ATI_RADEON_R100_QE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1006 case DEVICE_ATI_RADEON_R100_QF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1007 case DEVICE_ATI_RADEON_R100_QG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1008 RadeonFamily = 100; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1009 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1010 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1011 /* Radeon VE / Radeon Mobility */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1012 case DEVICE_ATI_RADEON_VE_QY: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1013 case DEVICE_ATI_RADEON_VE_QZ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1014 case DEVICE_ATI_RADEON_MOBILITY_M6: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1015 case DEVICE_ATI_RADEON_MOBILITY_M62: |
10332 | 1016 case DEVICE_ATI_RADEON_MOBILITY_U1: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1017 RadeonFamily = 120; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1018 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1019 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1020 /* Radeon 7500 / Radeon Mobility 7500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1021 case DEVICE_ATI_RADEON_RV200_QW: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1022 case DEVICE_ATI_RADEON_RV200_QX: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1023 case DEVICE_ATI_RADEON_MOBILITY_M7: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1024 case DEVICE_ATI_RADEON_MOBILITY_M72: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1025 RadeonFamily = 150; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1026 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1027 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1028 /* Radeon 8500 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1029 case DEVICE_ATI_RADEON_R200_BB: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1030 case DEVICE_ATI_RADEON_R200_QH: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1031 case DEVICE_ATI_RADEON_R200_QI: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1032 case DEVICE_ATI_RADEON_R200_QJ: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1033 case DEVICE_ATI_RADEON_R200_QK: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1034 case DEVICE_ATI_RADEON_R200_QL: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1035 case DEVICE_ATI_RADEON_R200_QH2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1036 case DEVICE_ATI_RADEON_R200_QI2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1037 case DEVICE_ATI_RADEON_R200_QJ2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1038 case DEVICE_ATI_RADEON_R200_QK2: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1039 RadeonFamily = 200; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1040 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1041 |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1042 /* Radeon 9000 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1043 case DEVICE_ATI_RADEON_R250_ID: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1044 case DEVICE_ATI_RADEON_R250_IE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1045 case DEVICE_ATI_RADEON_R250_IF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1046 case DEVICE_ATI_RADEON_R250_IG: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1047 case DEVICE_ATI_RADEON_R250_LD: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1048 case DEVICE_ATI_RADEON_R250_LE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1049 case DEVICE_ATI_RADEON_R250_LF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1050 case DEVICE_ATI_RADEON_R250_LG: |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1051 case DEVICE_ATI_RV250_5C61_RADEON: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1052 case DEVICE_ATI_RV250_5C63_RADEON: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1053 RadeonFamily = 250; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1054 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1055 |
12070
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1056 /* Radeon 9200 */ |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1057 case DEVICE_ATI_RV280_RADEON_9200: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1058 case DEVICE_ATI_RV280_RADEON_92002: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1059 case DEVICE_ATI_RV280_RADEON_92003: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1060 case DEVICE_ATI_RV280_RADEON_92004: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1061 case DEVICE_ATI_RV280_RADEON_92005: |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1062 RadeonFamily = 280; |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1063 break; |
070fc453a20b
support for Radeon 9200 based video boards patch by Benjamin Zores <ben at tutuxclan.org>
faust3
parents:
12060
diff
changeset
|
1064 |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1065 /* Radeon 9700 */ |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1066 case DEVICE_ATI_RADEON_R300_ND: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1067 case DEVICE_ATI_RADEON_R300_NE: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1068 case DEVICE_ATI_RADEON_R300_NF: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1069 case DEVICE_ATI_RADEON_R300_NG: |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1070 case DEVICE_ATI_RADEON_R300_AE: |
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1071 case DEVICE_ATI_RADEON_R300_AF: |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1072 RadeonFamily = 300; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1073 break; |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1074 |
11658
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
wight
parents:
11371
diff
changeset
|
1075 /* Radeon 9600/9800 */ |
73203cca1884
Makes radeon_vid work with the Radeon 9600 Pro card.
wight
parents:
11371
diff
changeset
|
1076 case DEVICE_ATI_RADEON_RV350_AP: |
12361
a84160d660af
support for a few more radeons patch by Reza Jelveh <reza.jelveh at tu-harburg.de>
faust3
parents:
12286
diff
changeset
|
1077 case DEVICE_ATI_RADEON_RV350_AR: |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1078 case DEVICE_ATI_RADEON_R350_NH: |
12454
83a18b230e8c
Add support for a few more Radeons, patch by Nyk Tarr.
diego
parents:
12361
diff
changeset
|
1079 case DEVICE_ATI_RADEON_R350_AH: |
83a18b230e8c
Add support for a few more Radeons, patch by Nyk Tarr.
diego
parents:
12361
diff
changeset
|
1080 case DEVICE_ATI_RADEON_R350_AI: |
12459 | 1081 case DEVICE_ATI_RADEON_R360_NJ: |
12060 | 1082 case DEVICE_ATI_RV350_MOBILITY_RADEON: |
1083 case DEVICE_ATI_RV350_MOBILITY_RADEON2: | |
11371
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1084 RadeonFamily = 350; |
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1085 break; |
9cd1546f26ea
patch by Vladimir Mosgalin <mosgalin@VM10124.spb.edu>
attila
parents:
10332
diff
changeset
|
1086 |
8876
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1087 default: |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1088 break; |
026ed72206ba
patch which removes the rage_ckey_model fix and updates
arpi
parents:
8859
diff
changeset
|
1089 } |
8855 | 1090 } |
3996 | 1091 #endif |
4193 | 1092 if(force > PROBE_NORMAL) |
1093 { | |
1094 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
1095 if(idx == -1) | |
1096 #ifdef RAGE128 | |
4373 | 1097 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 1098 #else |
4373 | 1099 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 1100 #endif |
1101 } | |
4191 | 1102 def_cap.device_id = lst[i].device; |
3996 | 1103 err = 0; |
1104 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
1105 probed=1; | |
1106 break; | |
1107 } | |
1108 } | |
1109 } | |
1110 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
1111 return err; | |
1112 } | |
1113 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1114 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
1115 |
3996 | 1116 int vixInit( void ) |
1117 { | |
4477 | 1118 int err; |
4012 | 1119 if(!probed) |
1120 { | |
1121 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
1122 return EINTR; | |
1123 } | |
1124 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 1125 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
1126 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1127 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
8942 | 1128 #ifdef RADEON |
1129 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ | |
1130 if (radeon_ram_size == 0 && | |
1131 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || | |
1132 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) | |
1133 { | |
1134 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); | |
1135 radeon_ram_size = 8192*1024; | |
1136 } | |
9240
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1137 #else |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1138 /* Rage Mobility (rage128) also has memsize bug */ |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1139 if (radeon_ram_size == 0 && |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1140 (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1141 def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1142 { |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1143 printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1144 radeon_ram_size = 8192*1024; |
4898cfdf582a
The patch enables the fix for rage128_vid as well as radeon_vid, and looks for the
arpi
parents:
9044
diff
changeset
|
1145 } |
8942 | 1146 #endif |
12072 | 1147 #ifdef WIN32 |
1148 if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024; | |
1149 #endif | |
3996 | 1150 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
1151 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 1152 radeon_vid_make_default(); |
1153 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 1154 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
1155 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
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8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1156 |
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1157 radeon_fifo_wait(3); |
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1158 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
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1159 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
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1160 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
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1161 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
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1162 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
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1163 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
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1164 |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1165 #ifdef RADEON |
8859 | 1166 switch(RadeonFamily) |
1167 { | |
1168 case 100: | |
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patch which removes the rage_ckey_model fix and updates
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1169 case 120: |
8859 | 1170 case 150: |
1171 case 250: | |
12642 | 1172 case 280: |
8859 | 1173 is_shift_required=1; |
1174 break; | |
1175 default: | |
1176 break; | |
1177 } | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1178 #endif |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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1179 |
9044 | 1180 /* XXX: hack, but it works for me (tm) */ |
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1181 #ifdef WORDS_BIGENDIAN |
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1182 #if defined(RAGE128) |
9044 | 1183 /* code from gatos */ |
1184 { | |
1185 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); | |
1186 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & | |
1187 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); | |
1188 | |
1189 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, | |
1190 // INREG(CONFIG_CNTL)); | |
1191 } | |
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1192 #else |
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1193 /*code from radeon_video.c*/ |
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1194 { |
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1195 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); |
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1196 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | |
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1197 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); |
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1198 */ |
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1199 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP |
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1200 | RADEON_NONSURF_AP0_SWP_16BPP)); |
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1201 |
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1202 /* |
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1203 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) |
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1204 & ~RADEON_NONSURF_AP0_SWP_16BPP); |
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1205 */ |
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|
1206 } |
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1207 #endif |
9044 | 1208 #endif |
1209 | |
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alex
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|
1210 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1211 return 0; |
1212 } | |
1213 | |
1214 void vixDestroy( void ) | |
1215 { | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
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|
1216 /* remove colorkeying */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
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|
1217 radeon_fifo_wait(3); |
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d952b097c720
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1218 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
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1219 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
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1220 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
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1221 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
d952b097c720
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1222 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
d952b097c720
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1223 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
6564
652ada9f9b66
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alex
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|
1224 |
13167
a6f958139ab8
Rough but working bigendian support for radeon cards, patch by Luca Barbato <lu_zero at gentoo.org>
faust3
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1225 #ifdef WORDS_BIGENDIAN |
a6f958139ab8
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|
1226 #if defined(RAGE128) |
9044 | 1227 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); |
1228 // printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, | |
1229 // INREG(CONFIG_CNTL)); | |
13167
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|
1230 #else |
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|
1231 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL); |
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1232 #endif |
9044 | 1233 #endif |
1234 | |
3996 | 1235 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 1236 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 1237 } |
1238 | |
1239 int vixGetCapability(vidix_capability_t *to) | |
1240 { | |
1241 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1242 return 0; | |
1243 } | |
1244 | |
6483 | 1245 /* |
1246 Full list of fourcc which are supported by Win2K redeon driver: | |
6564
652ada9f9b66
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alex
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1247 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1248 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1249 */ | |
3996 | 1250 uint32_t supported_fourcc[] = |
1251 { | |
6483 | 1252 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1253 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1254 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1255 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1256 IMGFMT_RGB16, IMGFMT_BGR16, |
1257 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1258 }; |
1259 | |
6483 | 1260 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1261 { |
6483 | 1262 unsigned int i; |
3996 | 1263 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1264 { | |
1265 if(fourcc==supported_fourcc[i]) return 1; | |
1266 } | |
1267 return 0; | |
1268 } | |
1269 | |
1270 int vixQueryFourcc(vidix_fourcc_t *to) | |
1271 { | |
1272 if(is_supported_fourcc(to->fourcc)) | |
1273 { | |
1274 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1275 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1276 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1277 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1278 VID_DEPTH_32BPP; | |
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|
1279 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1280 return 0; |
1281 } | |
4015 | 1282 else to->depth = to->flags = 0; |
3996 | 1283 return ENOSYS; |
1284 } | |
1285 | |
1286 static void radeon_vid_dump_regs( void ) | |
1287 { | |
1288 size_t i; | |
4015 | 1289 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1290 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1291 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1292 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1293 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1294 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1295 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1296 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1297 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1298 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1299 } |
1300 | |
1301 static void radeon_vid_stop_video( void ) | |
1302 { | |
1303 radeon_engine_idle(); | |
1304 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1305 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1306 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1307 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
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Reduce flickering on window movement (from Christophe Badina)
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|
1308 #ifdef RADEON |
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1309 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); |
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1310 #else |
3996 | 1311 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); |
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|
1312 #endif |
3996 | 1313 OUTREG(OV0_TEST, 0); |
1314 } | |
1315 | |
1316 static void radeon_vid_display_video( void ) | |
1317 { | |
1318 int bes_flags; | |
13335
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1319 #ifdef WORDS_BIGENDIAN |
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1320 #if defined(RAGE128) |
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1321 /* code from gatos */ |
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1322 { |
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1323 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); |
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1324 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & |
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1325 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); |
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1326 |
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1327 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, |
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1328 // INREG(CONFIG_CNTL)); |
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1329 } |
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1330 #else |
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1331 /*code from radeon_video.c*/ |
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1332 { |
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1333 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); |
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1334 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | |
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1335 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); |
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1336 */ |
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1337 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP |
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1338 | RADEON_NONSURF_AP0_SWP_16BPP)); |
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1339 |
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1340 /* |
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|
1341 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) |
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1342 & ~RADEON_NONSURF_AP0_SWP_16BPP); |
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1343 */ |
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1344 } |
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|
1345 #endif |
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1346 #endif |
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1347 |
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1348 |
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1349 |
3996 | 1350 radeon_fifo_wait(2); |
1351 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1352 radeon_engine_idle(); | |
1353 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1354 radeon_fifo_wait(15); | |
4666 | 1355 |
1356 /* Shutdown capturing */ | |
1357 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1358 OUTREG(CAP0_TRIG_CNTL, 0); | |
1359 | |
4689 | 1360 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1361 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1362 |
3996 | 1363 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1364 | |
4611 | 1365 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1366 #ifdef RAGE128 |
7493 | 1367 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1368 (((besr.saturation*31+31000)/2000) << 8) | | |
1369 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1370 #endif |
1371 radeon_fifo_wait(2); | |
4869 | 1372 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1373 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1374 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1375 |
1376 OUTREG(OV0_H_INC, besr.h_inc); | |
1377 OUTREG(OV0_STEP_BY, besr.step_by); | |
1378 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1379 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1380 OUTREG(OV0_V_INC, besr.v_inc); | |
1381 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1382 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1383 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1384 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1385 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1386 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1387 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1388 #ifdef RADEON | |
1389 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1390 #endif | |
4930 | 1391 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1392 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1393 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1394 radeon_fifo_wait(9); |
4930 | 1395 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1396 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1397 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1398 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1399 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1400 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1401 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1402 | |
6678 | 1403 #ifdef RADEON |
1404 bes_flags = SCALER_ENABLE | | |
1405 SCALER_SMART_SWITCH; | |
1406 // SCALER_HORZ_PICK_NEAREST | | |
1407 // SCALER_VERT_PICK_NEAREST | | |
1408 #endif | |
3996 | 1409 bes_flags = SCALER_ENABLE | |
1410 SCALER_SMART_SWITCH | | |
1411 SCALER_Y2R_TEMP | | |
1412 SCALER_PIX_EXPAND; | |
1413 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1414 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1415 #ifdef RAGE128 | |
1416 bes_flags |= SCALER_BURST_PER_PLANE; | |
1417 #endif | |
1418 switch(besr.fourcc) | |
1419 { | |
1420 case IMGFMT_RGB15: | |
1421 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1422 case IMGFMT_RGB16: |
3996 | 1423 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1424 /* |
3996 | 1425 case IMGFMT_RGB24: |
1426 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1427 */ |
3996 | 1428 case IMGFMT_RGB32: |
1429 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1430 /* 4:1:0 */ |
3996 | 1431 case IMGFMT_IF09: |
1432 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1433 /* 4:0:0 */ |
1434 case IMGFMT_Y800: | |
1435 case IMGFMT_Y8: | |
3996 | 1436 /* 4:2:0 */ |
1437 case IMGFMT_IYUV: | |
1438 case IMGFMT_I420: | |
6483 | 1439 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1440 /* 4:2:2 */ |
4455 | 1441 case IMGFMT_YVYU: |
3996 | 1442 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1443 case IMGFMT_YUY2: | |
1444 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1445 } | |
1446 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1447 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1448 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1449 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1450 } |
1451 | |
4456 | 1452 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1453 { |
4456 | 1454 unsigned pitch,spy,spv,spu; |
1455 spy = spv = spu = 0; | |
1456 switch(spitch->y) | |
1457 { | |
1458 case 16: | |
1459 case 32: | |
1460 case 64: | |
1461 case 128: | |
1462 case 256: spy = spitch->y; break; | |
1463 default: break; | |
1464 } | |
1465 switch(spitch->u) | |
1466 { | |
1467 case 16: | |
1468 case 32: | |
1469 case 64: | |
1470 case 128: | |
1471 case 256: spu = spitch->u; break; | |
1472 default: break; | |
1473 } | |
1474 switch(spitch->v) | |
1475 { | |
1476 case 16: | |
1477 case 32: | |
1478 case 64: | |
1479 case 128: | |
1480 case 256: spv = spitch->v; break; | |
1481 default: break; | |
1482 } | |
4009 | 1483 switch(fourcc) |
1484 { | |
1485 /* 4:2:0 */ | |
1486 case IMGFMT_IYUV: | |
1487 case IMGFMT_YV12: | |
4456 | 1488 case IMGFMT_I420: |
1489 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1490 else pitch = 32; | |
1491 break; | |
6483 | 1492 /* 4:1:0 */ |
1493 case IMGFMT_IF09: | |
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1494 case IMGFMT_YVU9: |
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1495 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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1496 else pitch = 64; |
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1497 break; |
4456 | 1498 default: |
1499 if(spy >= 16) pitch = spy; | |
1500 else pitch = 16; | |
1501 break; | |
4009 | 1502 } |
1503 return pitch; | |
1504 } | |
1505 | |
3996 | 1506 static int radeon_vid_init_video( vidix_playback_t *config ) |
1507 { | |
4930 | 1508 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1509 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1510 radeon_vid_stop_video(); |
1511 left = config->src.x << 16; | |
1512 top = config->src.y << 16; | |
1513 src_h = config->src.h; | |
1514 src_w = config->src.w; | |
6483 | 1515 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1516 if(config->fourcc == IMGFMT_YV12 || |
1517 config->fourcc == IMGFMT_I420 || | |
1518 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1519 if(config->fourcc == IMGFMT_YVU9 || |
1520 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1521 if(config->fourcc == IMGFMT_Y800 || | |
1522 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1523 if(config->fourcc == IMGFMT_RGB32 || |
1524 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1525 if(config->fourcc == IMGFMT_RGB32 || |
1526 config->fourcc == IMGFMT_BGR32 || | |
1527 config->fourcc == IMGFMT_RGB24 || | |
1528 config->fourcc == IMGFMT_BGR24 || | |
1529 config->fourcc == IMGFMT_RGB16 || | |
1530 config->fourcc == IMGFMT_BGR16 || | |
1531 config->fourcc == IMGFMT_RGB15 || | |
1532 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1533 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1534 mpitch = best_pitch-1; |
3996 | 1535 switch(config->fourcc) |
1536 { | |
6483 | 1537 /* 4:0:0 */ |
1538 case IMGFMT_Y800: | |
1539 case IMGFMT_Y8: | |
1540 /* 4:1:0 */ | |
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1541 case IMGFMT_YVU9: |
6483 | 1542 case IMGFMT_IF09: |
3996 | 1543 /* 4:2:0 */ |
1544 case IMGFMT_IYUV: | |
1545 case IMGFMT_YV12: | |
4415 | 1546 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1547 config->dest.pitch.y = |
1548 config->dest.pitch.u = | |
4415 | 1549 config->dest.pitch.v = best_pitch; |
3996 | 1550 break; |
4416 | 1551 /* RGB 4:4:4:4 */ |
1552 case IMGFMT_RGB32: | |
1553 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1554 config->dest.pitch.y = | |
1555 config->dest.pitch.u = | |
1556 config->dest.pitch.v = best_pitch; | |
1557 break; | |
3996 | 1558 /* 4:2:2 */ |
4455 | 1559 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1560 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1561 config->dest.pitch.y = |
1562 config->dest.pitch.u = | |
4415 | 1563 config->dest.pitch.v = best_pitch; |
3996 | 1564 break; |
1565 } | |
1566 dest_w = config->dest.w; | |
1567 dest_h = config->dest.h; | |
1568 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1569 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1570 besr.fourcc = config->fourcc; | |
1571 besr.v_inc = (src_h << 20) / dest_h; | |
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1572 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1573 h_inc = (src_w << 12) / dest_w; |
9544
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1574 |
97f61ffa441e
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1575 { |
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|
1576 unsigned int ecp_div; |
97f61ffa441e
vidix rage128 ecp_div patch by (Magnus Damm <damm at opensource dot se>)
michael
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changeset
|
1577 ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; |
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1578 h_inc <<= ecp_div; |
97f61ffa441e
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michael
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|
1579 } |
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1580 |
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1581 |
3996 | 1582 step_by = 1; |
1583 while(h_inc >= (2 << 12)) { | |
1584 step_by++; | |
1585 h_inc >>= 1; | |
1586 } | |
1587 | |
1588 /* keep everything in 16.16 */ | |
4015 | 1589 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1590 config->offsets[0] = 0; |
4930 | 1591 for(i=1;i<besr.vid_nbufs;i++) |
1592 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1593 if(is_420 || is_410 || is_400) |
3996 | 1594 { |
1595 uint32_t d1line,d2line,d3line; | |
1596 d1line = top*pitch; | |
6483 | 1597 if(is_420) |
1598 { | |
1599 d2line = src_h*pitch+(d1line>>2); | |
1600 d3line = d2line+((src_h*pitch)>>2); | |
1601 } | |
1602 else | |
1603 if(is_410) | |
1604 { | |
1605 d2line = src_h*pitch+(d1line>>4); | |
1606 d3line = d2line+((src_h*pitch)>>4); | |
1607 } | |
1608 else | |
1609 { | |
1610 d2line = 0; | |
1611 d3line = 0; | |
1612 } | |
3996 | 1613 d1line += (left >> 16) & ~15; |
6483 | 1614 if(is_420) |
1615 { | |
1616 d2line += (left >> 17) & ~15; | |
1617 d3line += (left >> 17) & ~15; | |
1618 } | |
1619 else | |
1620 if(is_410) | |
1621 { | |
1622 d2line += (left >> 18) & ~15; | |
1623 d3line += (left >> 18) & ~15; | |
1624 } | |
3996 | 1625 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1626 if(is_400) |
1627 { | |
1628 config->offset.v = 0; | |
1629 config->offset.u = 0; | |
1630 } | |
1631 else | |
1632 { | |
1633 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1634 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1635 } | |
4930 | 1636 for(i=0;i<besr.vid_nbufs;i++) |
1637 { | |
1638 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1639 if(is_400) |
1640 { | |
1641 besr.vid_buf_base_adrs_v[i]=0; | |
1642 besr.vid_buf_base_adrs_u[i]=0; | |
1643 } | |
1644 else | |
1645 { | |
9892 | 1646 if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1647 { | |
1648 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1649 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1650 } | |
1651 else | |
1652 { | |
1653 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1654 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1655 } | |
6483 | 1656 } |
4930 | 1657 } |
1658 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1659 if(is_400) |
1660 { | |
1661 config->offset.v = 0; | |
1662 config->offset.u = 0; | |
1663 } | |
1664 else | |
1665 { | |
1666 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1667 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1668 } | |
3996 | 1669 } |
1670 else | |
1671 { | |
1672 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1673 for(i=0;i<besr.vid_nbufs;i++) |
1674 { | |
1675 besr.vid_buf_base_adrs_y[i] = | |
1676 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1677 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1678 } |
3996 | 1679 } |
1680 | |
1681 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1682 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1683 ((tmp << 12) & 0xf0000000); | |
1684 | |
1685 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1686 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1687 ((tmp << 12) & 0x70000000); | |
1688 tmp = (top & 0x0000ffff) + 0x00018000; | |
1689 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1690 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1691 | |
1692 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1693 besr.p23_v_accum_init = (is_420||is_410) ? |
1694 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1695 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1696 | |
6483 | 1697 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1698 left = (left >> 16) & 15; |
4571 | 1699 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1700 if(is_rgb32) |
4571 | 1701 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1702 else |
6483 | 1703 if(is_410) |
1704 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1705 else | |
4416 | 1706 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1707 besr.step_by = step_by | (step_by << 8); |
1708 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1709 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1710 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1711 if(is_420 || is_410) |
3996 | 1712 { |
6483 | 1713 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1714 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1715 } | |
1716 else besr.p23_blank_lines_at_top = 0; | |
1717 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1718 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1719 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1720 if (is_410||is_420) src_w>>=is_410?2:1; |
1721 if(is_400) | |
1722 { | |
1723 besr.p2_x_start_end = 0; | |
1724 besr.p3_x_start_end = 0; | |
1725 } | |
1726 else | |
1727 { | |
1728 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1729 besr.p3_x_start_end = besr.p2_x_start_end; | |
1730 } | |
4869 | 1731 |
3996 | 1732 return 0; |
1733 } | |
1734 | |
4009 | 1735 static void radeon_compute_framesize(vidix_playback_t *info) |
1736 { | |
4666 | 1737 unsigned pitch,awidth,dbpp; |
4456 | 1738 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1739 dbpp = radeon_vid_get_dbpp(); |
4033 | 1740 switch(info->fourcc) |
1741 { | |
1742 case IMGFMT_I420: | |
1743 case IMGFMT_YV12: | |
1744 case IMGFMT_IYUV: | |
4666 | 1745 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1746 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1747 break; |
6483 | 1748 case IMGFMT_Y800: |
1749 case IMGFMT_Y8: | |
1750 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1751 info->frame_size = awidth*info->src.h; | |
1752 break; | |
1753 case IMGFMT_IF09: | |
1754 case IMGFMT_YVU9: | |
1755 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1756 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1757 break; | |
4429 | 1758 case IMGFMT_RGB32: |
1759 case IMGFMT_BGR32: | |
4666 | 1760 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1761 info->frame_size = awidth*info->src.h; |
4429 | 1762 break; |
1763 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1764 default: |
1765 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1766 info->frame_size = awidth*info->src.h; |
4033 | 1767 break; |
1768 } | |
4009 | 1769 } |
1770 | |
3996 | 1771 int vixConfigPlayback(vidix_playback_t *info) |
1772 { | |
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1773 unsigned rgb_size,nfr; |
3996 | 1774 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1775 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1776 if(info->num_frames==1) besr.double_buff=0; |
1777 else besr.double_buff=1; | |
4009 | 1778 radeon_compute_framesize(info); |
4930 | 1779 |
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1780 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1781 nfr = info->num_frames; |
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1782 for(;nfr>0; nfr--) |
4930 | 1783 { |
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1784 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
12286 | 1785 #ifdef HAVE_X11 |
1786 radeon_overlay_off -= firegl_shift; | |
1787 #endif | |
4930 | 1788 radeon_overlay_off &= 0xffff0000; |
1789 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1790 } | |
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1791 if(nfr <= 3) |
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1792 { |
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1793 nfr = info->num_frames; |
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1794 for(;nfr>0; nfr--) |
4930 | 1795 { |
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1796 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
12286 | 1797 #ifdef HAVE_X11 |
1798 radeon_overlay_off -= firegl_shift; | |
1799 #endif | |
4930 | 1800 radeon_overlay_off &= 0xffff0000; |
1801 if(radeon_overlay_off > 0) break; | |
1802 } | |
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1803 } |
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1804 if(nfr <= 0) return EINVAL; |
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1805 info->num_frames = nfr; |
4930 | 1806 besr.vid_nbufs = info->num_frames; |
1807 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1808 radeon_vid_init_video(info); |
1809 return 0; | |
1810 } | |
1811 | |
1812 int vixPlaybackOn( void ) | |
1813 { | |
1814 radeon_vid_display_video(); | |
1815 return 0; | |
1816 } | |
1817 | |
1818 int vixPlaybackOff( void ) | |
1819 { | |
1820 radeon_vid_stop_video(); | |
1821 return 0; | |
1822 } | |
1823 | |
4033 | 1824 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1825 { |
4412 | 1826 uint32_t off[6]; |
4930 | 1827 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1828 /* |
1829 buf3-5 always should point onto second buffer for better | |
1830 deinterlacing and TV-in | |
1831 */ | |
4666 | 1832 if(!besr.double_buff) return 0; |
4930 | 1833 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1834 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1835 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1836 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1837 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1838 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1839 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1840 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1841 radeon_fifo_wait(8); |
3996 | 1842 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1843 radeon_engine_idle(); |
3996 | 1844 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1845 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1846 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1847 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1848 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1849 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1850 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1851 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1852 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1853 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1854 return 0; |
1855 } | |
1856 | |
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1857 vidix_video_eq_t equal = |
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1858 { |
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1859 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1860 #ifndef RAGE128 |
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1861 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1862 #endif |
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1863 , |
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1864 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1865 |
1866 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1867 { | |
1868 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1869 return 0; | |
1870 } | |
1871 | |
4229 | 1872 #ifndef RAGE128 |
1873 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1874 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1875 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1876 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1877 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1878 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1879 #endif | |
1880 | |
3996 | 1881 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1882 { | |
1883 #ifdef RAGE128 | |
1884 int br,sat; | |
4229 | 1885 #else |
1886 int itu_space; | |
3996 | 1887 #endif |
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1888 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1889 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1890 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1891 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1892 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1893 { |
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1894 equal.red_intensity = eq->red_intensity; |
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1895 equal.green_intensity = eq->green_intensity; |
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1896 equal.blue_intensity = eq->blue_intensity; |
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1897 } |
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1898 equal.flags = eq->flags; |
3996 | 1899 #ifdef RAGE128 |
1900 br = equal.brightness * 64 / 1000; | |
4229 | 1901 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1902 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1903 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1904 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1905 #else | |
4229 | 1906 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1907 RTFCheckParam(equal.brightness); | |
1908 RTFCheckParam(equal.saturation); | |
1909 RTFCheckParam(equal.contrast); | |
1910 RTFCheckParam(equal.hue); | |
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1911 RTFCheckParam(equal.red_intensity); |
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1912 RTFCheckParam(equal.green_intensity); |
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1913 RTFCheckParam(equal.blue_intensity); |
4229 | 1914 radeon_set_transform(RTFBrightness(equal.brightness), |
1915 RTFContrast(equal.contrast), | |
1916 RTFSaturation(equal.saturation), | |
1917 RTFHue(equal.hue), | |
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1918 RTFIntensity(equal.red_intensity), |
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1919 RTFIntensity(equal.green_intensity), |
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1920 RTFIntensity(equal.blue_intensity), |
4229 | 1921 itu_space); |
3996 | 1922 #endif |
1923 return 0; | |
1924 } | |
1925 | |
4611 | 1926 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1927 { | |
1928 unsigned sflg; | |
1929 switch(info->flags) | |
1930 { | |
1931 default: | |
1932 case CFG_NON_INTERLACED: | |
1933 besr.deinterlace_on = 0; | |
1934 break; | |
1935 case CFG_EVEN_ODD_INTERLACING: | |
1936 case CFG_INTERLACED: | |
1937 besr.deinterlace_on = 1; | |
1938 besr.deinterlace_pattern = 0x900AAAAA; | |
1939 break; | |
1940 case CFG_ODD_EVEN_INTERLACING: | |
1941 besr.deinterlace_on = 1; | |
1942 besr.deinterlace_pattern = 0x00055555; | |
1943 break; | |
1944 case CFG_UNIQUE_INTERLACING: | |
1945 besr.deinterlace_on = 1; | |
1946 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1947 break; | |
1948 } | |
1949 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1950 radeon_engine_idle(); | |
1951 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1952 radeon_fifo_wait(15); | |
1953 sflg = INREG(OV0_SCALE_CNTL); | |
1954 if(besr.deinterlace_on) | |
1955 { | |
1956 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1957 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1958 } | |
1959 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1960 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1961 return 0; | |
1962 } | |
1963 | |
1964 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1965 { | |
1966 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1967 else | |
1968 { | |
1969 info->flags = CFG_UNIQUE_INTERLACING; | |
1970 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1971 } | |
1972 return 0; | |
1973 } | |
4869 | 1974 |
1975 | |
1976 /* Graphic keys */ | |
1977 static vidix_grkey_t radeon_grkey; | |
1978 | |
1979 static void set_gr_key( void ) | |
1980 { | |
1981 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1982 { | |
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1983 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1984 besr.ckey_on=1; |
1985 | |
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1986 switch(dbpp) |
4869 | 1987 { |
1988 case 15: | |
8856 | 1989 #ifdef RADEON |
8858 | 1990 if(RadeonFamily > 100) |
8856 | 1991 besr.graphics_key_clr= |
1992 ((radeon_grkey.ckey.blue &0xF8)) | |
1993 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
1994 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
1995 else | |
1996 #endif | |
4869 | 1997 besr.graphics_key_clr= |
1998 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1999 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
2000 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
2001 break; | |
2002 case 16: | |
8856 | 2003 #ifdef RADEON |
2004 /* This test may be too general/specific */ | |
8858 | 2005 if(RadeonFamily > 100) |
8856 | 2006 besr.graphics_key_clr= |
2007 ((radeon_grkey.ckey.blue &0xF8)) | |
2008 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
2009 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
2010 else | |
2011 #endif | |
4869 | 2012 besr.graphics_key_clr= |
2013 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
2014 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
2015 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
2016 break; | |
2017 case 24: | |
2018 besr.graphics_key_clr= | |
2019 ((radeon_grkey.ckey.blue &0xFF)) | |
2020 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
2021 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
2022 break; | |
2023 case 32: | |
2024 besr.graphics_key_clr= | |
2025 ((radeon_grkey.ckey.blue &0xFF)) | |
2026 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
2027 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
2028 break; | |
2029 default: | |
2030 besr.ckey_on=0; | |
2031 besr.graphics_key_msk=0; | |
2032 besr.graphics_key_clr=0; | |
2033 } | |
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2034 #ifdef RAGE128 |
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2035 besr.graphics_key_msk=(1<<dbpp)-1; |
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2036 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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2037 #else |
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2038 besr.graphics_key_msk=besr.graphics_key_clr; |
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2039 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; |
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2040 #endif |
4869 | 2041 } |
2042 else | |
2043 { | |
2044 besr.ckey_on=0; | |
2045 besr.graphics_key_msk=0; | |
2046 besr.graphics_key_clr=0; | |
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2047 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 2048 } |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
changeset
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2049 radeon_fifo_wait(3); |
4869 | 2050 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
2051 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
2052 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
2053 } | |
2054 | |
2055 int vixGetGrKeys(vidix_grkey_t *grkey) | |
2056 { | |
2057 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
2058 return(0); | |
2059 } | |
2060 | |
2061 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
2062 { | |
2063 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
2064 set_gr_key(); | |
2065 return(0); | |
2066 } |